JP2725839B2 - Video intermediate frequency signal processing circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video intermediate frequency signal processing circuit capable of outputting a frequency control signal for controlling a local oscillation frequency of a local oscillation circuit of a tuner.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional video inter frequency (hereinafter abbreviated as "VIF") signal processing circuit of the PLL perfect synchronous detection system. As shown in the figure,
A VIF signal obtained by converting a television broadcast signal from a TV receiver or a VTR tuner is taken into the amplifier 1 and amplified.

The amplifier 1 has an automatic gain adjustment (AGC) circuit 2
, The output of the VIF signal is always kept at an optimum constant amplitude irrespective of the amplitude fluctuation of the VIF signal.

The output of the amplifier 1 is a phase locked loop (hereinafter referred to as PLL) circuit 3, a synchronous detection circuit 4, and an automatic frequency control (Auto
matic Fine Tuning (hereinafter abbreviated as “AFT”). The PLL circuit 3 includes a voltage controlled oscillator (hereinafter, referred to as a VCO) 6 and a phase shifter 7 for advancing the output of the VCO 6 by 90 °.
A phase detection circuit 8 for comparing the phase of the output of the phase shifter 7 with the output of the amplifier 1; and a low-pass filter (hereinafter, referred to as a filter) for filtering the output of the phase detection circuit 8 and applying it to the control input of the VCO 6.
LPF. 9). When the PLL circuit 3 is locked, the output of VCO6 is a same frequency and the same phase with respect to normal picture carrier of the VIF signal (frequency f _p), given to the synchronous detection circuit 4. The synchronous detection circuit 4 synchronously detects the VIF signal output from the amplifier 1 based on this signal, and derives a video detection output.

This video detection output is output to the outside and fed back to the internal AGC circuit 2 and lock detection circuit 10. The AGC circuit 2 detects the amplitude of the video detection output, and controls the amplification factor of the amplifier 1 so that the amplitude always becomes a constant amplitude. On the other hand, the lock detection circuit 10 detects whether the PLL circuit 3 is locked or unlocked based on the video detection output, and controls the time constant of the LPF 9. That is, when unlocked, the time constant of the LPF 9 is reduced to increase the response speed, and the PLL capture range is widened. On the other hand, at the time of locking, the response is slowed by increasing the time constant of the LPF 9, and control is performed so that it is difficult to respond to noise or phase distortion inherent in the VIF signal. Such a lock detection circuit
By using the ten outputs, a more accurate video detection output can be obtained.

The AFT circuit 5 internally detects the output of the amplifier 1 by FM detection to derive an AFT voltage as shown in FIG. This A
By feeding back to the local oscillator of the tuner FT voltage through a low-pass filter or the like, the frequency of the VIF signal outputted from the tuner is always kept normal value f _p. This is the AFT function. For FM detection,
Since a reference signal that oscillates at the reference frequency is required, the AFT
The circuit 5 has a tank circuit composed of a coil and a capacitor.

[Problems to be solved by the invention]

The video intermediate frequency signal processing circuit having the AFT function of the conventional PLL perfect synchronous detection system is configured as described above.
The AFT circuit 5 must have a tank circuit including a coil and a capacitor. Also, since the VCO 6 also performs oscillation output, it was necessary to provide a tank circuit.

The tuning frequency of both 5,6 is the frequency f _p of regular almost equal VIF signal is set to 58.75Hz case of Japan.

On the other hand, as the degree of integration has been improved in recent years, the VIF signal processing circuit has been integrated into one chip. Therefore, the distance between the VCO 6 and the AFT circuit 5 is likely to be extremely short.

From the above two events, there is a problem that the possibility of mutual interference between the coil of the VCO 6 and the coil of the AFT circuit 5 becomes extremely high. For example, even when there is no input of a VIF signal, the VCO 6 oscillates at the free-running frequency, which is also the stable point of the PLL. The voltage is affected by the oscillation frequency of the VCO 6, which causes a problem that the AFT circuit 5 does not operate normally. That is, there is a problem that the integrated VIF signal processing circuit malfunctions.

Therefore, the AFT circuit 5 having the tank circuit is removed and the PLL
A method of generating the output of the LPF 9 (the control voltage of the VCO 6) in the circuit 3 as an AFT voltage can be considered. In this method, the output frequency of the VCO 6 is equal to the frequency of the VIF signal, and when the PLL circuit 3 is locked, the output of the LPF 9 which is the control voltage of the VCO 6 changes in relation to the frequency of the VIF signal as shown in FIG. That is, the output is similar to the AFT voltage of the AFT circuit 5.

However, as shown in FIG.
The control voltage of O6 becomes a constant level, and VCO6 normally oscillates at the free-running frequency. Therefore, the control voltage of VCO6 is VIF
The control voltage of VCO6 becomes AFT independent of the signal frequency.
It cannot be generated as a voltage.

To begin with, when considering an operation in the configuration including the tuner and VIF signal processing circuit, AFT function works in first in VIF signal processing circuit, VIF from the tuner of the normal frequency f _p
After controlling to output a signal, the phase is locked by the PLL circuit 3. Therefore, the PLL circuit 3
However, if the AFT function cannot be performed when unlocked, it will not be practical at all, so the method of generating the AFT voltage based only on the output of the LPF 9 will not solve the problem at all.

The present invention has been made in order to solve the above-described problems, and a PLL which does not cause a malfunction even when integrated is provided.
It is an object of the present invention to obtain a video intermediate frequency signal processing circuit having an AFT function of a completely synchronous detection system.

[Means for solving the problem]

A video intermediate frequency signal processing circuit according to the present invention is capable of outputting a frequency control signal for controlling a local oscillation frequency of a local oscillation circuit of a tuner, comprising: input means for inputting a video intermediate frequency signal; a phase detection circuit; filter,
A phase locked loop (PLL) including a voltage controlled oscillator, wherein the phase detection circuit derives a phase detection signal based on a phase difference between the video intermediate frequency signal and an oscillation output signal from the voltage controlled oscillator. When the phase detection signal is supplied as a control voltage of the voltage controlled oscillator through the low pass filter, a PLL output signal synchronized with the video intermediate frequency signal is output when locked, and the voltage controlled oscillator A free-running frequency of the oscillation output signal of the PLL circuit, in which the video intermediate frequency signal is set to be equal to a normal video carrier frequency of the video intermediate frequency signal, and the video intermediate frequency signal is synchronously detected based on the PLL output signal. A synchronous detection circuit for deriving an output, and a phase for determining a lead / lag of a phase between the phase detection output and the video detection output, and outputting a lead / lag determination signal. And only delay decision means, said PLL
A lock detection circuit for detecting a lock state and an unlock state of the circuit and outputting a lock detection signal; and taking in the lock detection signal, and when the PLL circuit is in a lock state, outputs the output of the low-pass filter in the PLL circuit. Frequency control signal output means for outputting as a frequency control signal, and outputting the advance / lag determination signal as the frequency control signal when the PLL circuit is in an unlocked state.

[Action]

The lead / lag determining means in the present invention determines the lead / lag of the phase between the phase detection output and the video detection output, and outputs a lead / lag determination signal. The above-mentioned phase detection output and video detection output are based on the oscillation output signal oscillating at the free-running frequency which is the frequency of the normal video carrier when the PLL circuit is not locked. Beat with signal.

Therefore, the lead / lag relationship between the phase of the video detection output and the phase detection output is reversed depending on whether the frequency of the video intermediate frequency signal is higher or lower than the free-running frequency. It is possible to grasp whether the frequency of the video intermediate frequency signal is higher or lower than the normal frequency.

On the other hand, when the PLL circuit is locked, the output of the low-pass filter is changed based on the frequency of the video intermediate frequency signal by the PLL function. Therefore, the frequency of the video intermediate frequency signal can be grasped from the output of the low-pass filter.

〔Example〕

FIG. 1 is a block diagram showing a video intermediate frequency signal processing circuit according to an embodiment of the present invention. Instead of the AFT circuit 5 having the conventional tank circuit, phase shift circuits 11 and 12, a phase relation detection circuit 13, an amplifier 14, and a switch 15 are newly provided.

The phase shift circuit 11 delays the phase of the output of the phase detection circuit 8 by about 30 degrees and outputs it to the phase relation detection circuit 13. On the other hand, the phase shift circuit 12 advances the phase of the output of the synchronous detection circuit 4 by about 30 degrees and outputs it to the phase relation detection circuit 13.

The phase relationship detection circuit 13 switches a positive or negative signal to the switch 15 based on the phase lead / lag relationship of the phase of the output of the phase shift circuits 11 and 12.
Output to one input. The amplifier 14 amplifies the output of the LPF 9 (the control voltage of the VCO 6) and outputs the amplified output to the other input of the switch 15.

The switch 15 grasps whether the PLL circuit 3 is in the locked state or the unlocked state by taking in the output of the lock detecting circuit 10. Then, in response to the output of the lock detection circuit 10, the output of the amplifier 14 is output as the AFT voltage when the lock state is detected, and the output of the phase difference detection circuit 13 is output when the unlock state is detected.

Note that the other configuration is the same as the conventional one, and thus the description is omitted.

The AFT operation of the VIF signal processing circuit of this embodiment having such a configuration will be described.

Operation in Locked State When the PLL circuit 3 is in the locked state, the switch 15 selects the output of the amplifier 14 as the AFT voltage. This is because, as described above, the control voltage of the VCO 6 functions equivalently to the AFT voltage when locked (see FIG. 5), so that the amplified voltage can be used as it is as the AFT voltage. Based on

Operation in Unlocked State When the PLL circuit 3 is in the unlocked state, the switch 15 selects the output of the phase relationship detection circuit 13 as the AFT voltage. Hereinafter, the fact that the output of the phase relationship detection circuit 13 can be used as an AFT voltage will be described with reference to the vector diagram of FIG.

When not locked, the control voltage of the VCO 6 is constant, VCO 6 is unchanged from exactly the same free-running frequency and the reference frequency f _p which conventional AFT circuit is used (normal video carrier frequency) oscillation to I have. The output S6 of this VCO 6 and the output of the phase shifter 7
S7 means that the output S7 is always output as shown in FIG.
The phase is 90 ° ahead of S6.

If the frequency of the VIF signal in this situation is greater than the reference frequency f _p, looking at the vector diagram of Figure 2 by fixing the output S6, S7 (a), obtained by amplifying the VIF signal at the amplifier 1 output Only S1 will rotate counterclockwise.

Therefore, in this case, as shown in FIG. 2 (b), the video detection output S4 (both outputs S1, S2) which is the low frequency component (frequency component of the difference) of the multiplication result of the output S1 and the output S6.
The phase of output S1 and output S
Low frequency component (frequency component of difference) in the result of multiplication with 7
Is always 90 ° ahead of the phase of the phase detection output S8 (understood as the beat of both outputs S1 and S7).

Then, a signal output S12 obtained by advancing the video detection output S4 by about 30 ° by the phase shift circuit 12 and a phase detection output S8 are formed by the phase circuit 1.
The signal output S11 delayed by about 30 ° by 1 is taken into the phase relationship detection circuit 13 in a phase relationship as shown in FIG. 2 (c). The phase relationship detection circuit 13 outputs the outputs S11, S1
By obtaining the multiplication value of 2, the phase comparison result PC is obtained as shown by the broken line in FIG. 2 (c). This phase comparison result PC
Is opposite in direction to the output S11, the phase relation detection circuit 1
A negative signal is output as the output S13 of 3.

On the other hand, when the frequency of the VIF signal reference frequency f _p less than, the same principle as when the frequency of the VIF signal is greater than the reference frequency f _p (FIG. 2 (d) ~ (f) refer), the phase comparison result Since the PC indicates the same direction as the output S11, a positive signal is output as the output S13 of the phase relationship detection circuit 13.

That is, during the non-locked, so that the phase relationship detection circuit 13 a positive signal at the frequency <f _p of the negative signal VIF when the VIF frequency> f _p outputs.

When the PLL circuit 3 is not locked, as shown in FIG.
Since the frequency and the reference frequency f _p of the signal it is far away, only outputs a positive / negative binary output according to the frequency of the VIF signal, sufficiently AFT using this output as AFT voltage
Actions can be taken.

Thus, without providing a tank circuit other than the VCO 6, regardless of whether the PLL circuit 3 is locked or unlocked,
A VIF signal processing circuit capable of effectively outputting the FT voltage can be obtained. For this reason, even if the VIF signal processing circuit is integrated and integrated into one chip, a malfunction does not occur due to the AFT function.

Further, a phase shift circuit 11, which is provided to have an AFT function,
12, the phase relationship detection circuit 13, the amplifier 14, and the switch 15 can all be easily integrated, so that providing them does not impair the integration of the VIF signal processing circuit.

In this embodiment, the phase shift amounts of the phase detection output S8 and the video detection output S4 by the phase shift circuits 11 and 12 are, for example, 0 to 9
As long as it is within the range of 0 °, it may vary, and it is not necessary to execute the phase shift processing with high accuracy. Also, short frequency of the VIF signal phase difference φ is 0 ° between the video detection output S4 and the phase detection output S8, depending on whether the reference frequency f _p larger or smaller than <
φ <90 ° (270 ° <φ <360 °) or 90 ° <φ <180
゜ (180 ° <φ <270 °), the present invention is not limited to the configuration of the above-described embodiment. For example, the phase detection circuit 12 or 11 is provided only for the output S4 or S8, and the video detection output S4 or the phase detection is performed. The phase shift of only the output S8 may be performed.

In this embodiment, the phase shift between the video detection output S4 and the phase detection output S8 is adjusted by the phase circuits 11 and 12 such that the phase difference φ between the two satisfies the above relationship (the phase relationship between the two is multiplied by multiplication processing). After that, the phase relation detection circuit 13 outputs a positive or negative signal based on the multiplication value of the outputs S11 and S12 of the phase shift circuits 11 and 12.
A circuit that outputs a negative signal when the video detection output S4 is ahead of the phase detection output S8 and a circuit that outputs a positive signal when the phase detection output S8 is ahead of the video detection output S4 can be used instead.

Further, in order to provide a 90 ° phase difference between the oscillation output signals of the VCO 6 input to the video detection circuit 4 and the phase detection circuit 8, the phase shifter 7 is provided between the VCO 6 and the phase detection circuit 8. A 90 ° phase shifter may be provided between the VCO 6 and the synchronous detection circuit 4 instead of between the VCO 6 and the phase detection circuit 8. In addition, VCO6,
A phase shifter is provided between the synchronous detection circuit 4 and between the VCO 6 and the phase detection circuit 8 so that the oscillation output signals of the VCO 6 input to the video detection circuit 4 and the phase detection circuit 8 have a phase difference of 90 °. Is also good.

〔The invention's effect〕

As described above, according to the present invention, the output of the low-pass filter, which is the control voltage of the VCO, is output as the AFT voltage when the PLL circuit is locked, and the phase of the video detection output and the phase detection output is output when the PLL circuit is unlocked. Since the advance / delay determination signal output by the phase advance / delay determination means is output as an AFT voltage based on the advance / delay, there is no need to provide a dedicated oscillation circuit in addition to the VCO in order to provide an AFT function. There is an effect that it is possible to obtain a video intermediate frequency signal processing circuit having an AFT function of a PLL perfect synchronous detection system which does not cause a malfunction even if it is implemented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a video intermediate frequency signal processing circuit according to an embodiment of the present invention, FIG. 2 is a vector diagram for explaining the operation of the video intermediate frequency signal processing circuit shown in FIG. 1, and FIG. FIG. 4 is a block diagram showing a conventional video intermediate frequency signal processing circuit, FIG. 4 is a graph showing an AFT voltage with respect to the frequency of a VIF signal, and FIG. 5 is a graph showing a VCO control voltage with respect to the frequency of a VIF signal. In the figure, 3 is a PLL circuit, 4 is a synchronous detection circuit, 6 is VC
O and 7 are phase shifters, 8 is a phase detection circuit, 9 is an LPF, 10 is a lock detection circuit, 11 and 12 are phase shift circuits, 13 is a phase relation detection circuit, 14 is an amplifier, and 15 is a switch. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] An image intermediate frequency signal processing circuit capable of outputting a frequency control signal for controlling a local oscillation frequency of a local oscillation circuit of a tuner, comprising: input means for inputting an image intermediate frequency signal; a phase detection circuit; A phase locked loop (PLL) including a filter and a voltage controlled oscillator, wherein the phase detection circuit generates a phase detection signal based on a phase difference between the video intermediate frequency signal and an oscillation output signal from the voltage controlled oscillator. The phase detection signal is provided as a control voltage of the voltage controlled oscillator through the low-pass filter, and outputs a PLL output signal synchronized with the video intermediate frequency signal when locked, and A PLL circuit in which the free-running frequency of the oscillation output signal of the control oscillator is set equal to the normal video carrier frequency of the video intermediate frequency signal A synchronous detection circuit that synchronously detects the video intermediate frequency signal based on the PLL output signal and derives a video detection output, and determines a lead / lag of a phase between the phase detection output and the video detection output. Phase lead / lag determining means for outputting a delay determining signal; a lock detecting circuit for detecting a locked state and an unlocked state of the PLL circuit and outputting a lock detecting signal; taking in the lock detecting signal; A frequency control signal output unit that outputs an output of the low-pass filter in the PLL circuit as the frequency control signal, and outputs the advance / delay determination signal as the frequency control signal when the PLL circuit is in an unlocked state. A video intermediate frequency signal processing circuit comprising: