JPH02137062U - - Google Patents

Info

Publication number
JPH02137062U
JPH02137062U JP4313289U JP4313289U JPH02137062U JP H02137062 U JPH02137062 U JP H02137062U JP 4313289 U JP4313289 U JP 4313289U JP 4313289 U JP4313289 U JP 4313289U JP H02137062 U JPH02137062 U JP H02137062U
Authority
JP
Japan
Prior art keywords
support plate
semiconductor element
circuit board
power semiconductor
board device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4313289U
Other languages
English (en)
Other versions
JPH0625978Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4313289U priority Critical patent/JPH0625978Y2/ja
Publication of JPH02137062U publication Critical patent/JPH02137062U/ja
Application granted granted Critical
Publication of JPH0625978Y2 publication Critical patent/JPH0625978Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Structure Of Printed Boards (AREA)
  • Mounting Of Printed Circuit Boards And The Like (AREA)

Description

【図面の簡単な説明】
第1図は本考案に係わる半導体装置の一部を示
す断面図、第2図は回路基板装置の導体層と電気
回路との関係を絶縁層を省いて示す底面図、第3
図は半導体装置を示す一部切欠断面図、第4図は
第1図の電気回路を概略的に示すブロツク図、第
5図は変形例の回路基板装置の構成を示す断面図
である。 1…支持板、2…外部リード、3…回路基板装
置、4…電力用半導体素子、8…絶縁基板、9…
電気回路、10…導体層、11,12…絶縁層、
13…接着剤層。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 放熱板を兼ねる導電性支持板と、 前記支持板上に固着された50kHz以上の周
    波数でスイツチング動作する電力用半導体素子と
    、 前記支持板上に固着された回路基板装置と、 前記支持板と前記電力用半導体素子と前記回路
    基板装置との内の少なくとも1つに電気的に接続
    された外部リードと を備えた半導体装置において、 前記電力用半導体素子が導電性を有するろう材
    によつて前記支持板に固着されており、 前記回路基板装置は、絶縁基板と、前記電力用
    半導体素子を制御するために前記絶縁基板の一方
    の主面に形成されている半導体素子制御用電気回
    路と、前記絶縁基板の他方の主面において前記電
    気回路に対向する領域に形成され且つ前記電気回
    路に電気的に接続され且つその電位が実質的に固
    定されている導体層とを備えており、 前記導体層と前記支持板との間に絶縁物層が設
    けられていることを特徴とする半導体装置。 (2) 放熱板を兼ねる導電性支持板と、 前記支持板上に固着された50kHz以上の周
    波数でスイツチング動作する電力用半導体素子と
    、 前記支持板上に固着された回路基板装置と、 前記支持板と前記電力用半導体素子と前記回路
    基板装置との内の少なくとも1つに電気的に接続
    された外部リードと を備えた半導体装置において、 前記電力用半導体素子が導電性を有するろう材
    によつて前記支持板に固着されており、 前記回路基板装置は、金属基板と、この金属基
    板の一方の主面上に形成された絶縁層と、前記電
    力用半導体素子を制御するために前記絶縁層上に
    形成されている半導体素子制御用電気回路とを備
    えており、 前記金属基板は前記電気回路に電気的に接続され
    且つその電位が実質的に固定されており、 前記金属基板と前記支持板との間に絶縁物層が
    設けられていることを特徴とする半導体装置。
JP4313289U 1989-04-13 1989-04-13 半導体装置 Expired - Lifetime JPH0625978Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4313289U JPH0625978Y2 (ja) 1989-04-13 1989-04-13 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4313289U JPH0625978Y2 (ja) 1989-04-13 1989-04-13 半導体装置

Publications (2)

Publication Number Publication Date
JPH02137062U true JPH02137062U (ja) 1990-11-15
JPH0625978Y2 JPH0625978Y2 (ja) 1994-07-06

Family

ID=31555285

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4313289U Expired - Lifetime JPH0625978Y2 (ja) 1989-04-13 1989-04-13 半導体装置

Country Status (1)

Country Link
JP (1) JPH0625978Y2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016001744A (ja) * 2009-12-25 2016-01-07 ローム株式会社 機能素子モジュール

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016001744A (ja) * 2009-12-25 2016-01-07 ローム株式会社 機能素子モジュール

Also Published As

Publication number Publication date
JPH0625978Y2 (ja) 1994-07-06

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