JPS61140544U - - Google Patents

Info

Publication number
JPS61140544U
JPS61140544U JP1985021889U JP2188985U JPS61140544U JP S61140544 U JPS61140544 U JP S61140544U JP 1985021889 U JP1985021889 U JP 1985021889U JP 2188985 U JP2188985 U JP 2188985U JP S61140544 U JPS61140544 U JP S61140544U
Authority
JP
Japan
Prior art keywords
insulating layer
heat dissipation
die attach
window hole
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985021889U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985021889U priority Critical patent/JPS61140544U/ja
Publication of JPS61140544U publication Critical patent/JPS61140544U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Description

【図面の簡単な説明】
第１図は本考案における高放熱ＩＣパツケージ
の一実施例を示す断面図、第２図は従来の高放熱
ＩＣパツケージを示す断面図である。 １１…第１絶縁層、１１ａ…放熱用スルーホー
ル、１１ｂ…信号用スルーホール、１２…ダイア
タツチ部、１３…第２絶縁層、１３ａ…窓穴、１
３ｂ…信号用スルーホール、１４…導体パターン
、１５…第３絶縁層、１９…放熱用端子パツド、
２０…放熱用端子、２１…ＩＣ端子。

Claims (1)

  1. 【実用新案登録請求の範囲】 ダイアタツチ部を上面に有する第１絶縁層、Ｉ
    Ｃ素子を収納する窓穴を有する第２絶縁層および
    第２絶縁層の窓穴より大きい窓穴を有する第３絶
    縁層を順次上面に積層形成すると共に、前記第２
    絶縁層の窓穴内で前記ダイアタツチ部上面にＩＣ
    素子を搭載し、このダイアタツチ部を介してＩＣ
    素子より発生した熱の放熱を行う高放熱ＩＣパツ
    ケージにおいて、 前記第１絶縁層にダイアタツチ部と接続しかつ
    熱伝導性および導電性に優れた素材により穴うめ
    された放熱用スルーホールを設けると共に、該ス
    ルーホールと基板とを接続するための放熱用ピン
    を設けたことを特徴とする高放熱ＩＣパツケージ
    。
JP1985021889U 1985-02-20 1985-02-20 Pending JPS61140544U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985021889U JPS61140544U (ja) 1985-02-20 1985-02-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985021889U JPS61140544U (ja) 1985-02-20 1985-02-20

Publications (1)

Publication Number Publication Date
JPS61140544U true JPS61140544U (ja) 1986-08-30

Family

ID=30513686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985021889U Pending JPS61140544U (ja) 1985-02-20 1985-02-20

Country Status (1)

Country Link
JP (1) JPS61140544U (ja)

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