JPH02111041A - Wire bonding of ic chip - Google Patents
Wire bonding of ic chipInfo
- Publication number
- JPH02111041A JPH02111041A JP63265154A JP26515488A JPH02111041A JP H02111041 A JPH02111041 A JP H02111041A JP 63265154 A JP63265154 A JP 63265154A JP 26515488 A JP26515488 A JP 26515488A JP H02111041 A JPH02111041 A JP H02111041A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- flexible printed
- circuit board
- board
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000853 adhesive Substances 0.000 claims abstract description 15
- 230000001070 adhesive effect Effects 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 7
- 230000002093 peripheral effect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（１ｇ業上の利用分野）
本発明は、フレキシブルプリント回路基板上に接着剤を
介して固着されたＩＣチップと、フレキシブルプリント
回路基板の配線パターンのり一ドパッド部の間をワイヤ
ーボンディングにより接続するＩＣチップのワイヤーボ
ンディング方法に関づるものである。Detailed Description of the Invention [Object of the Invention] (Field of Application in the 1G Industry) The present invention relates to an IC chip fixed to a flexible printed circuit board via an adhesive, and a wiring pattern adhesive for the flexible printed circuit board. The present invention relates to a wire bonding method for an IC chip that connects one pad portion to another by wire bonding.
（従来の技術）
液晶テレビ用［ジュールの駆動用及び増幅用の回路のＹ
板には、フレキシブルプリント回路基＋ｆｉ（以下、Ｆ
ＰＣＬｉ板と呼ぶ。）が多く用いられている。(Prior art) For LCD TV [Y of Joule drive and amplification circuit]
The board has a flexible printed circuit board +fi (hereinafter referred to as F
It is called a PCLi board. ) are often used.
このＦＰＣ基板（ユ、たとえば、ポリイミド等の合成樹
脂から成るベースフィルムに銅等で配線パターンを形成
したもので、このＦＰＣ尽仮に駆動機能素子や増幅機能
素子としてのＩＣチップを配（支）・固定し、さらに、
このＩＣチップとＦＰＣＮ板の配線パターンのリードパ
ッド部の間をワイヤｌ−ボンディングによりｌＹ＆続し
て、回路を形成している。This FPC board (for example, a base film made of synthetic resin such as polyimide with a wiring pattern formed with copper or the like) is used to temporarily arrange (support) an IC chip as a drive function element or an amplification function element. Fixed and further,
This IC chip and the lead pad portion of the wiring pattern of the FPCN board are connected by wire l-bonding to form a circuit.
このような回路の製造において、ＦＰＣ基板に対するＩ
Ｃチップの配置・固定は、ＦＰＣ基根上の所定位置に、
たとえば熱硬化性樹脂から成る接着剤を介して、ＩＣチ
ップを接着し、さらに、約１２０℃・２０分のキユアリ
ングつまり接着剤の硬化を行なうが、このキユアリング
を通じて、ＦＰＣＭ板の基礎材ｒ１であるベースフィル
ムのポリイミド等と配線パターンの銅等の熱膨脹係数の
差もあって、キユアリング後のＦＰＣＩｕｌｆｉに反り
を生ずる。In manufacturing such circuits, I
To place and fix the C-chip, place it in a predetermined position on the FPC base.
For example, an IC chip is bonded through an adhesive made of thermosetting resin, and then curing is performed at about 120°C for 20 minutes to harden the adhesive. There is also a difference in thermal expansion coefficient between polyimide, etc. of the base film and copper, etc. of the wiring pattern, which causes warpage in the FPCI ulfi after curing.
このため、キユアリング後のＦＰＣＪｉ板をボンディン
グ治具に装着し、ＩＣチップとＦＰＣ基板のリードパッ
ド部の間をワイヤーボンデ−ｒングにより接続しようと
するときに、ＦＰＣ基板の反りの影響で、ＦＰＣ基楢基
体全体ンディング治具に平らに密着せず、とくに、ＦＰ
ＣＭ板の周辺部がボンディング治具から浮いた状態にな
り、この状態で、ＩＣチップとＦＰＣＭ、ｌｆのリード
パッド部の間をワイヤーボンディングにより接続しよう
とした場合、ＦＰＣ基板がボンディング治具に固定され
ていないため、ボンディング用のキャピラリーが作動す
るたびに、ＦＰＣＭ板が動いてしまい、ボンディングが
できなかった。For this reason, when the FPCJi board after curing is mounted on a bonding jig and an attempt is made to connect between the IC chip and the lead pad part of the FPC board by wire bonding, due to the warpage of the FPC board, the FPC The entire base does not adhere flatly to the landing jig, especially when the FP
The peripheral part of the CM board is floating from the bonding jig, and in this state, if you try to connect the IC chip and the lead pad part of FPCM and lf by wire bonding, the FPC board will not be fixed to the bonding jig. As a result, the FPCM board moved every time the bonding capillary was activated, making it impossible to perform bonding.
そこで、ボンディング治具にＦＰＣ拮板を装着した状態
で、ＦＰＣｆｒ板のリードパッド部の外側周辺部を押圧
し、反りの無い状態にしてボンディングを実施したが、
このように反りの無い状態にしても、超音波ボンダーで
ボンディングすると、超音波ボンダーの振動によって、
ＩＣチップが上下に動いてしまい、超音波振動による加
圧力が適切に作用せず、ＩＣチップ側のボンディング箇
所におけるボンディングワイヤー先端のボール外れや、
ＦＰＣ基板側のリードパッド部におけるワイヤー跳ね等
のボンディング不良の発生という致命的な欠陥が発生し
、ボンディングができたとしても、接合強度が基準値以
下となったり、ボンディングワイヤーのループ形状が不
安定になったりすることが判明した。Therefore, with the FPC counter board attached to the bonding jig, we pressed the outer periphery of the lead pad part of the FPC fr board and bonded it in a state without warping.
Even in this state without warping, when bonding with an ultrasonic bonder, the vibration of the ultrasonic bonder causes
The IC chip moves up and down, and the pressing force from ultrasonic vibration does not work properly, causing the ball to come off at the tip of the bonding wire at the bonding location on the IC chip side.
A fatal bonding defect such as wire bounce at the lead pad on the FPC board side may occur, and even if bonding is successful, the bonding strength may be below the standard value or the loop shape of the bonding wire may be unstable. It turned out that it becomes.
このような問題に対して、ＩＣチップの１キ着後にキユ
アリングを行なっても、Ｆ Ｐ ＣＷ、 歌ｓ二反りが
発生し難くするために、たとえば、Ｆｐｃｍ板の裏面に
ガラスエポキシ板をホットプレス秀により張付けてＦＰ
Ｃ基板を補強することも考えられるが、製造［程が繁雑
になり、コスト面からも好ましくない。To solve this problem, for example, a glass epoxy plate is hot-pressed on the back side of the FPC board to prevent FPCW and double warping from occurring even if curing is performed after the IC chip is placed on the IC chip. FP attached by Hide
Although reinforcing the C-board may be considered, it would complicate the manufacturing process and is not preferable from a cost standpoint.
（発明が解決しようとするｖＲ題）
上述したように、ＦＰＣＪ３板にＩＣデツプを接着剤で
接着し、この接着剤を硬化さゼると、Ｆｐｃｘｉに反り
が発生ずるため、ＩＣチップとＦＰＣ基板のリードパッ
ド部との問のワイヤーボンディングが困難で、ＦＰＣ基
板を押えても、ＩＣチップが動いて、ワイヤーボンディ
ングができなかったり、不確実になったりするという問
題がある。(vR problem to be solved by the invention) As mentioned above, when the IC depth is bonded to the FPCJ3 board with adhesive and this adhesive is cured, the FPCXI will warp, so the IC chip and FPC board There is a problem in that wire bonding between the FPC board and the lead pad part is difficult, and even if the FPC board is held down, the IC chip moves, making wire bonding impossible or unreliable.
本発明は、このような点に鑑み成されたもので、ワイヤ
ーボンディングを、容易な手段により、確実に行なうこ
とを目的とするものである。The present invention has been made in view of these points, and an object of the present invention is to perform wire bonding reliably by a simple means.
（課題を解決するための手段）
本発明のＩＣチップのワイヤーボンディング方法は、フ
レキシブルプリント回路基板上の所定位置に接着剤を介
してＩＣチップを接着し、このフレキシブルプリント回
路基板とＩＣチップの問の接着剤を硬化させ、フレキシ
ブルプリント回路基板をボンディング治具に装着し、少
なくと−ちフレキシブルプリント回路基板上のＩＣチッ
プを押えた状態で、ＩＣチップとフレキシブルプリント
回路基板の配線パターンのＩＣチップに対するリードパ
ッド部との間をワイヤーボンディングにより接続するも
のである。(Means for Solving the Problems) The IC chip wire bonding method of the present invention involves bonding an IC chip to a predetermined position on a flexible printed circuit board via an adhesive, and bonding the IC chip to a predetermined position on a flexible printed circuit board. After curing the adhesive, attach the flexible printed circuit board to the bonding jig, and at least hold down the IC chip on the flexible printed circuit board, and attach the IC chip and the IC chip of the wiring pattern of the flexible printed circuit board. The lead pad portion is connected to the lead pad portion by wire bonding.
（ｆｌ用）
本発明のＩＣチップのワイヤーボンディング７＋法は、
フレキシブルプリント回路基板上にＩｃチップを接着し
て、接着剤を硬化させた後、フレキシブルプリント回路
Ｊｌ仮をボンディング治具に装着し、フレキシブルプリ
ント回路Ｍｋ上のＩＣチップを押えた状態で、ＩＣチッ
プとフレキシブルプリント回路基板のリードパッド部と
の間をワイヤーボンディングにより接続するので、超音
波ボンダーでボンディングする場合に振動が１３口ゎっ
ても、フレキシブルプリント回路基板上のＩＣチップが
上下に動くことがなくなる。(For fl) The wire bonding 7+ method for IC chips of the present invention is as follows:
After adhering the IC chip on the flexible printed circuit board and curing the adhesive, attach the flexible printed circuit Jl temporary to the bonding jig, and press the IC chip on the flexible printed circuit Mk. Since the lead pads of the flexible printed circuit board are connected by wire bonding, the IC chip on the flexible printed circuit board will not move up and down even if the vibration is 13 degrees when bonding with an ultrasonic bonder. It disappears.
（実施例）
本発明のＩＣチップのワイヤーボンディング方法の実施
例を図面を参照して説明する。(Example) An example of the wire bonding method for an IC chip of the present invention will be described with reference to the drawings.
第１図において、１はフレ１−シブルプリント回路基板
（以下、Ｆｐｃｍ板と呼ぶ。）で、このＦＰＣＪＪ板１
上の複数の所定位置に、それぞれＩＣデツプ２が図示し
ない熱硬化性樹脂から成る接着剤を介して接着され、こ
の接着剤が約１２０℃・２０分のキ１アリングによって
硬化している。In Fig. 1, 1 is a flexible printed circuit board (hereinafter referred to as FPCM board), and this FPCJJ board 1
The IC depths 2 are respectively bonded to a plurality of predetermined positions on the top via an adhesive made of a thermosetting resin (not shown), and this adhesive is hardened by kearing at about 120° C. for 20 minutes.
そして、５はボンディング治具で、このボンディング治
具５は、上記Ｆ Ｐ ＣＭ ＋）２１を支持位置決めす
る治具ベース６と、この治具ベース６上に上記ＦＰＣ基
板、１を介して配置される治具カバー７から成り、治具
カバー７には、上記各ＩＣチップ２とこのＩＣデツプ２
に対重ろ上記ＦＰＣ基板１の図示しない配線パターンの
リードパッド部を露出させる複数のワイヤーボンディン
グ用の間口部８が形成され、この各開口部８の周囲に位
置して、治具カバー７の下面に、上記ＦＰＣ基板１の図
示しないリードパッド部の周辺部を治具ベース６に押え
る周辺部え９が取付けられており、さらに、各開口部８
には、それぞれ上記ＩＣデツプ２の中央部を上記ＦＰＧ
基板１を介して治具ベース６に押えるＩＣチップ押え１
０が、連結片１１を介して治具カバー７と一体に形成さ
れ、この各ＩＣチップ押え１０の下面には、それぞれＩ
Ｃデツプ２を保護するための樹脂シート１２が貼着され
ている。5 is a bonding jig, and this bonding jig 5 includes a jig base 6 for supporting and positioning the F PCM +) 21, and a jig base 6 disposed on the jig base 6 via the FPC board 1. The jig cover 7 includes each of the above-mentioned IC chips 2 and this IC depth 2.
A plurality of wire bonding openings 8 are formed to expose the lead pad portions of the wiring pattern (not shown) of the FPC board 1, and are located around each of the openings 8 to open the jig cover 7. A peripheral part holder 9 for pressing the peripheral part of the lead pad part (not shown) of the FPC board 1 onto the jig base 6 is attached to the lower surface, and furthermore, each opening 8
In each case, the center part of the IC depth 2 is connected to the FPG.
IC chip presser 1 that presses onto the jig base 6 via the substrate 1
0 is formed integrally with the jig cover 7 via the connecting piece 11, and the lower surface of each IC chip holder 10 has an I
A resin sheet 12 for protecting the C-depth 2 is attached.
なお、１５はウィンドクランパー、１６は超音波ホーン
で、１７はキャピラリーである。Note that 15 is a wind clamper, 16 is an ultrasonic horn, and 17 is a capillary.
そうして、このような構成において、接る剤によりＩＣ
チップ２を固着したＦ Ｐ ＣＭＳＳｉ２、治具ベース
６上に支持位置決めし、この治具ベース６上にＦＰＣ基
板１を介して治具カバー７を配置し、この治具カバー７
の開口部８からＦ Ｐ Ｃ！３仮１上のＩＣチップ２と
ＦＰＣ！を板１の図示しない配線パターンのリードパッ
ド部を露出させ、この間口部８の周囲の周辺部え９によ
り、Ｆ ｌ） ＣＭ板１の図示しないリードパッド部の
周辺部を治具ベース６に押えるとともに、治具カバー７
のＩＣデツプ押え１０によりＩｃチップ２の中央部を上
記ＦＰＣＩ板１を介して治具ベース６に押える。Then, in such a configuration, the IC is
The F P CMSSi 2 to which the chip 2 is fixed is supported and positioned on the jig base 6, and the jig cover 7 is placed on the jig base 6 via the FPC board 1.
From opening 8 of FPC! 3 IC chip 2 and FPC on provisional 1! Expose the lead pad part of the wiring pattern (not shown) on the board 1, and attach the peripheral part of the lead pad part (not shown) of the CM board 1 to the jig base 6 using the peripheral part 9 around the opening part 8. While pressing, jig cover 7
The central portion of the IC chip 2 is pressed onto the jig base 6 via the FPCI board 1 using the IC depth presser 10.
そして、このようにして治具ベース６と治具カバー７で
ＦＰＣ基板１を１＊持したボンディング治具５は、図示
しないワイヤーボンダーのボンディングステージに搬送
され、ウィンドクランパー１５によって、治具カバー７
の開口部８付近を押えられ、超音波ホーン１６によって
保持されたキャピラリー１７の下降により、ワイヤーボ
ンディングが開始され、ＩＣチップ２とこのＩＣチップ
２に対するＦＰＣＷ板１０図示しない配線パターンのリ
ードパッド部が１ツイヤ−２１によって接続される。The bonding jig 5 holding one FPC board 1 between the jig base 6 and the jig cover 7 in this way is transported to the bonding stage of a wire bonder (not shown), and the jig cover 7 is moved by the wind clamper 15.
Wire bonding is started by the lowering of the capillary 17 held by the ultrasonic horn 16 and the IC chip 2 and the lead pad portion of the wiring pattern (not shown) on the FPCW board 10 connected to the IC chip 2. 1 gear 21.
このワイヤーボンディングの際、ＩＣチップ２は、ＩＣ
チップ押え１０により押えられているので、キャピラリ
ー１７の上背、下降及び超行波ＪＪ２！ｌＩに追随して
上下動することがなく、Ｆｐｃｇ板１とともに、ボンデ
ィング治具５に固定された状態を維持する。During this wire bonding, the IC chip 2
Since it is held down by the chip holder 10, the upper back of the capillary 17, the downward movement and the superlinear wave JJ2! It does not move up and down following lI and remains fixed to the bonding jig 5 together with the FPCG plate 1.
したがって、このようなワイヤーボンディングによって
、ＦＰＣＷ板１の反りに関係なく、ワイヤー２１の接合
強ｌαが一定でかつ適正となり、安定したループ形状が
１ｑられる。Therefore, by such wire bonding, the bonding strength lα of the wire 21 is constant and appropriate regardless of the warpage of the FPCW board 1, and a stable loop shape 1q is achieved.
なお、ＩＣチップ押え１０を連結片１１を介して治具カ
バー７と一体に形成する代わりに、第２図に示すように
、別体のＩＣチップ押え２５をねじ２６を介して治具カ
バー７に螺着するど、ＩＣデツプ押え２５の交換が可能
となる。Note that instead of forming the IC chip holder 10 integrally with the jig cover 7 via the connecting piece 11, as shown in FIG. By screwing it on, the IC deposit holder 25 can be replaced.
（発明の効果）
上述したように、本発明によれば、ワイヤーボンディン
グの際に、フレキシブルプリント回路基板の反りや超音
波振動によって生じるｌＣチップの上下動を防止できる
ので、フレキシブルプリント回路基板上で良好なワイヤ
ーボンデ−ボンダを行なうことができ、しかも、製造工
程を繁雑にすることがなく、コストアップの心配すない
。(Effects of the Invention) As described above, according to the present invention, it is possible to prevent vertical movement of the LC chip caused by warpage of the flexible printed circuit board or ultrasonic vibration during wire bonding, so Good wire bonding can be performed without complicating the manufacturing process and without worrying about cost increases.
図は本発明のＩＣチップのワイヤーボンディング方法の
実施例で、第１図はボンディング治具どフレキシブルプ
リント回路１（ｆｉとＩＣチップの関係を示す斜視図、
第２図は変形例を示すボンディング治具の一部の斜視図
である。。
１・・フレキシブルプリント回路Ｂｔ １．２・ＩＣチ
ップ、
・ボンディング治具。
昭和６３年１０月２０「］
発
明
者
藤
井
敏
秀
同
船
曳
部The figure shows an embodiment of the wire bonding method for an IC chip according to the present invention.
FIG. 2 is a perspective view of a part of a bonding jig showing a modification. . 1.Flexible printed circuit Bt 1.2.IC chip, ・Bonding jig. October 20, 1988 ``] Inventor Toshihide Fujii Ship pulling department
Claims (1)
着剤を介してＩＣチップを接着し、このフレキシブルプ
リント回路基板とＩＣチップの問の接着剤を硬化させ、
フレキシブルプリント回路基板をボンディング治具に装
着し、少なくともフレキシブルプリント回路基板上のＩ
Ｃチップを押えた状態で、ＩＣチップとフレキシブルプ
リント回路基板の配線パターンのＩＣチップに対するリ
ードパッド部との間をワイヤーボンディングにより接続
することを特徴とするＩＣチップのワイヤーボンディン
グ方法。(1) Adhering an IC chip to a predetermined position on a flexible printed circuit board via an adhesive, curing the adhesive between the flexible printed circuit board and the IC chip,
The flexible printed circuit board is mounted on the bonding jig, and at least the I on the flexible printed circuit board is
A wire bonding method for an IC chip, which comprises connecting the IC chip and a lead pad portion of a wiring pattern of a flexible printed circuit board for the IC chip by wire bonding while holding the C chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63265154A JPH02111041A (en) | 1988-10-20 | 1988-10-20 | Wire bonding of ic chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63265154A JPH02111041A (en) | 1988-10-20 | 1988-10-20 | Wire bonding of ic chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02111041A true JPH02111041A (en) | 1990-04-24 |
Family
ID=17413378
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63265154A Pending JPH02111041A (en) | 1988-10-20 | 1988-10-20 | Wire bonding of ic chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02111041A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012164918A (en) * | 2011-02-09 | 2012-08-30 | Denso Corp | Manufacturing method of wire bonding structure |
-
1988
- 1988-10-20 JP JP63265154A patent/JPH02111041A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012164918A (en) * | 2011-02-09 | 2012-08-30 | Denso Corp | Manufacturing method of wire bonding structure |
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