JP2836264B2 - Board mounting method for pad grid array package - Google Patents
Board mounting method for pad grid array packageInfo
- Publication number
- JP2836264B2 JP2836264B2 JP3011828A JP1182891A JP2836264B2 JP 2836264 B2 JP2836264 B2 JP 2836264B2 JP 3011828 A JP3011828 A JP 3011828A JP 1182891 A JP1182891 A JP 1182891A JP 2836264 B2 JP2836264 B2 JP 2836264B2
- Authority
- JP
- Japan
- Prior art keywords
- grid array
- pad
- array package
- circuit board
- pad grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はパッドグリッドアレイパ
ッケージの基板実装方法。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a pad grid array package on a substrate.
【０００２】[0002]
【従来の技術】パッドグリッドアレイパッケージ型半導
体は図４に示すように印刷回路基板に実装されて使用さ
れている。従来の表面実装用パッケージは半田による接
合を行なっていて、その接合方法は赤外線リフローおよ
びベーパーフェイズ等である。2. Description of the Related Art As shown in FIG. 4, a pad grid array package type semiconductor is mounted on a printed circuit board and used. Conventional surface mounting packages are joined by soldering, and the joining method is infrared reflow, vapor phase, or the like.
【０００３】図５はパッドグリッドアレイパッケージの
基板実装した従来の状態を説明するための図４のＡ−Ａ
線断面図である。パッドグリッドアレイパッケージ１と
印刷配線の回路基板２を電気的接続させる方法は、あら
かじめパッケージ１や回路基板２にめっきや印刷等の方
法等によって付けられている半田層を熱をかけ溶かして
半田層１０を形成しそれを介して接続している。FIG. 5 is a view for explaining a conventional state in which a pad grid array package is mounted on a substrate.
It is a line sectional view. A method of electrically connecting the pad grid array package 1 and the printed wiring circuit board 2 is to apply a heat to a solder layer previously applied to the package 1 or the circuit board 2 by plating, printing, or the like to melt the solder layer. 10 and connected through it.
【０００４】[0004]
【発明が解決しようとする課題】従来のパッドグリッド
アレイパッケージの基板実装方法は、赤外線リフローや
ベーパーフェイズで半田実装する場合に、あらかじめ印
刷回路基板の銅パッド部やパッケージのリードピンに半
田が固着していて、実装する時はその半田を２３０〜２
６０℃の高温にして溶かして接続・実装している為、パ
ッケージの反りや変形等により浮きが発生し、うまく接
続せずショート不良となる。また回路基板の銅パッド部
全体に半田が付いている為接続の確認が難かしいという
ような欠点があった。The conventional method of mounting a pad grid array package on a board uses a soldering method in which solder is previously fixed to a copper pad portion of a printed circuit board or a lead pin of the package when soldering is performed by infrared reflow or vapor phase. When mounting, the solder should be 230-2
Since connection and mounting are performed by melting at a high temperature of 60 ° C., floating occurs due to warpage or deformation of the package, and connection is not made well, resulting in a short circuit failure. In addition, since the solder is attached to the entire copper pad portion of the circuit board, it is difficult to confirm the connection.
【０００５】[0005]
【課題を解決するための手段】本発明のパッドグリッド
アレイパッケージの基板実装方法は、パッドグリッドア
レイパッケージを印刷配線回路基板に実装する際、あら
かじめ回路基板に紫外線硬化型導電樹脂を全面に塗布し
ておき、その回路基板上面より指定位置にパッドグリッ
ドアレイパッケージを乗せ、樹脂の毛細管現象及び表面
張力により樹脂がパッドグリッドアレイパッケージのス
ルーホールの表面の導体パッド上面付近まで上昇させ、
そして上部よりスルーホールを通して紫外線を当て、樹
脂を硬化させその後未硬化の箇所を取り除いて構成され
る。According to the method of mounting a pad grid array package on a substrate of the present invention, when mounting the pad grid array package on a printed wiring circuit board, an ultraviolet curing conductive resin is applied to the entire surface of the circuit board in advance. In advance, the pad grid array package is placed at a specified position from the upper surface of the circuit board, and the resin rises to the vicinity of the upper surface of the conductor pad on the surface of the through hole of the pad grid array package due to the capillary action and surface tension of the resin,
Ultraviolet rays are applied from the upper part through through holes to cure the resin, and then the uncured portions are removed.
【０００６】また本発明のパッドグリッドアレイパッケ
ージは、スルーホールの基板側の穴径が反対上面側の穴
径よりも大きく構成されている。In the pad grid array package of the present invention, the diameter of the through hole on the substrate side is larger than the diameter of the through hole on the upper surface side.
【０００７】[0007]
【実施例】次に本発明について図面を参照して説明す
る。図１（ａ），（ｂ）は本発明の一実施例を説明する
ために工程順に示したパッケージと実装基板の一部断面
図であり、図５に示した従来のＡ−Ａ線断面図に対応し
ている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIGS. 1A and 1B are partial cross-sectional views of a package and a mounting board shown in the order of steps for explaining an embodiment of the present invention, and are cross-sectional views taken along line AA of the related art shown in FIG. It corresponds to.
【０００８】パッドグリッドアレイパッケージ１は外部
と電気的接続される為に導体パッド４とスルーホール３
を有する。導体パッド４は、めっき等の方法により、Ｃ
u ，Ｎi ，Ａu により構成され、下面側にはパッケージ
を浮かせる為０．５ｍｍ以上の高さを設ける。又、スル
ーホール３は実装密着性等の点から０．３ｍｍ以上とし
ている。The pad grid array package 1 has conductor pads 4 and through holes 3 to be electrically connected to the outside.
Having. The conductor pad 4 is formed by a method such as plating.
u, Ni, and Au, and the lower surface is provided with a height of 0.5 mm or more to float the package. Also, the through hole 3 is set to 0.3 mm or more from the viewpoint of mounting adhesion and the like.
【０００９】回路基板２はパッケージ１と接続させる為
の銅パッド７と配線を保護する為のソルダーレジスト８
とベースとなるガラス布エポキシ系基板９とからなる。
その回路基板２の上面には紫外線硬化型液状導電樹脂６
をあらかじめ塗布しておく。そして回路基板２と指定位
置にパッドグリッドアレイパッケージ１を載せ、上面か
ら紫外線を当て、スルーホール３を通して下面の樹脂６
を硬化させる。その後、紫外線の当たらない未硬化の箇
所を取り除くことにより、パッドグリッドアレイパッケ
ージが実装が完了する。The circuit board 2 has a copper pad 7 for connecting to the package 1 and a solder resist 8 for protecting the wiring.
And a glass cloth epoxy-based substrate 9 serving as a base.
An ultraviolet-curable liquid conductive resin 6 is provided on the upper surface of the circuit board 2.
Is applied in advance. Then, the pad grid array package 1 is mounted on the circuit board 2 and the designated position, and ultraviolet rays are applied from the upper surface.
To cure. Thereafter, by removing uncured portions that are not exposed to ultraviolet rays, the mounting of the pad grid array package is completed.
【００１０】図３，図４は本発明の第２，第３の実施例
の一部断面図である。それぞれパッドグリッドアレイパ
ッケージ１ａ，１ｂの上面スルーホール径ｒよりも下面
スルーホール径Ｒを０．２〜０．５ｍｍ大きくすること
により紫外線の拡散によって、硬化範囲が拡がり、接続
強度が増したり導通抵抗が大きくなる効果がある。FIGS. 3 and 4 are partial sectional views of the second and third embodiments of the present invention. By making the lower surface through-hole diameter R larger than the upper surface through-hole diameter r of the pad grid array packages 1a and 1b by 0.2 to 0.5 mm, the curing range is expanded by diffusion of ultraviolet rays, thereby increasing the connection strength and increasing the conduction resistance. Has the effect of becoming larger.
【００１１】[0011]
【発明の効果】以上説明したように本発明はパッドグリ
ッドアレイパッケージを回路基板に実装する際、あらか
じめ実装基板に紫外線硬化型導電樹脂を全面に塗布して
おき、その実装基板上面の指定位置にパッドグリッドア
レイパッケージを載せ、上面よりパッケージのスルーホ
ールを通して紫外線を当てて樹脂を硬化させ、未硬化部
分を除去することにより、パッケージの反りが変形等が
多少あっても接続、実装が可能であり、又、スルーホー
ルを通して上面から接続状態を目視で判断することが可
能である為、接続信頼性が高く得られる。As described above, according to the present invention, when the pad grid array package is mounted on a circuit board, an ultraviolet-curable conductive resin is applied to the entire surface of the mounting board in advance, and the pad is placed at a designated position on the upper surface of the mounting board. By mounting the pad grid array package and applying ultraviolet light from the top surface through the through hole of the package to cure the resin and remove the uncured part, connection and mounting are possible even if the package is slightly warped or deformed. In addition, since the connection state can be visually determined from the upper surface through the through hole, the connection reliability can be improved.
【００１２】又、パッケージ上面のスルーホール径より
パッケージ下面のスルーホール径を大きくして紫外線の
拡散を利用し、接続面積を上がり接続強度を大きくし、
接続抵抗を小さくできるという効果を有する。In addition, the diameter of the through hole on the lower surface of the package is made larger than the diameter of the through hole on the upper surface of the package to utilize the diffusion of ultraviolet rays to increase the connection area and increase the connection strength.
This has the effect of reducing the connection resistance.
【図１】（ａ）及び（ｂ）は本発明の第１の実施例を説
明するための工程順に示したパッケージと実装基板の一
部断面図である。FIGS. 1A and 1B are partial cross-sectional views of a package and a mounting board, which are shown in the order of steps for explaining a first embodiment of the present invention.
【図２】本発明の第２の実施例を説明するためのパッケ
ージと回路基板の一部断面図である。FIG. 2 is a partial cross-sectional view of a package and a circuit board for explaining a second embodiment of the present invention.
【図３】本発明の第３の実施例を説明するためのパッケ
ージと回路基板の一部断面図である。FIG. 3 is a partial cross-sectional view of a package and a circuit board for explaining a third embodiment of the present invention.
【図４】パッドグリッドアレイパッケージを搭載した回
路基板の斜視図である。FIG. 4 is a perspective view of a circuit board on which a pad grid array package is mounted.
【図５】パッドグリッドアレイパッケージを回路基板に
実装した従来の状態を説明するための図４のＡ−Ａ線断
面図である。FIG. 5 is a cross-sectional view taken along line AA of FIG. 4 for explaining a conventional state in which a pad grid array package is mounted on a circuit board.
１，１ａ，１ｂ パッドグリッドアレイパッケージ ２ 回路基板 ３ スルーホール ４ 導体パッド ５ ガラス布トリアジン系基板 ６ 紫外線硬化型液状導電樹脂 ７ 銅パッド ８ ソルダーレジスト ９ ガラス布エポキシ系基板 １０ 半田層 DESCRIPTION OF SYMBOLS 1, 1a, 1b Pad grid array package 2 Circuit board 3 Through hole 4 Conductor pad 5 Glass cloth triazine-based board 6 Ultraviolet curing liquid conductive resin 7 Copper pad 8 Solder resist 9 Glass cloth epoxy-based board 10 Solder layer
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H05K 3/32 H05K 1/18──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H05K 3/32 H05K 1/18
Claims (2)
体層を介してＩＣ内蔵のパッドグリッドアレイパッケー
ジのスルホール表面の導体パッドと接続するパッドグリ
ッドアレイパッケージの基板実装方法において、まず、
前記印刷配線回路基板の全面に紫外線硬化型導電樹脂を
塗布し、次にスルーホールが前記銅パッドに対応する位
置に前記パッドグリッドアレイパッケージを載置し、次
に上面から前記スルーホールを通して紫外線を照射して
樹脂硬化をさせた後、前記紫外線硬化型導電樹脂の未硬
化部を除去する工程を有することを特徴とするパッドグ
リッドアレイパッケージの基板実装方法。1. A method of mounting a pad grid array package on a surface of a printed wiring circuit board, wherein the copper pad on the surface of the printed wiring circuit board is connected to a conductor pad on a through hole surface of a pad grid array package with a built-in IC via a conductor layer.
UV curable conductive resin is applied to the entire surface of the printed wiring circuit board, then the pad grid array package is placed at a position where the through hole corresponds to the copper pad, and then ultraviolet light is passed through the through hole from the upper surface. A method for mounting a substrate of a pad grid array package, comprising a step of removing an uncured portion of the ultraviolet-curable conductive resin after the resin is cured by irradiation.
前記導体層側の穴径が反対上面側の穴径よりも大きいこ
とを特徴とする請求項１記載のパッドグリッドアレイパ
ッケージの基板実装方法。2. The method according to claim 1, wherein a hole diameter on the conductor layer side of the pad grid array package is larger than a hole diameter on an opposite upper surface side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3011828A JP2836264B2 (en) | 1991-02-01 | 1991-02-01 | Board mounting method for pad grid array package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3011828A JP2836264B2 (en) | 1991-02-01 | 1991-02-01 | Board mounting method for pad grid array package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04246885A JPH04246885A (en) | 1992-09-02 |
| JP2836264B2 true JP2836264B2 (en) | 1998-12-14 |
Family
ID=11788627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3011828A Expired - Lifetime JP2836264B2 (en) | 1991-02-01 | 1991-02-01 | Board mounting method for pad grid array package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2836264B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203480450U (en) * | 2013-05-09 | 2014-03-12 | 宸正光电（厦门）有限公司 | Touch panel |
| JP2018514071A (en) * | 2015-01-27 | 2018-05-31 | ネーデルランドセ・オルガニサティ・フォール・トゥーヘパスト−ナトゥールウェテンスハッペライク・オンデルズーク・テーエヌオー | Flexible device module for fiber layer assembly and fabrication method |
-
1991
- 1991-02-01 JP JP3011828A patent/JP2836264B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04246885A (en) | 1992-09-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980908 |