JPH02181444A - Mounting method of ic - Google Patents

Mounting method of ic

Info

Publication number
JPH02181444A
JPH02181444A JP170689A JP170689A JPH02181444A JP H02181444 A JPH02181444 A JP H02181444A JP 170689 A JP170689 A JP 170689A JP 170689 A JP170689 A JP 170689A JP H02181444 A JPH02181444 A JP H02181444A
Authority
JP
Japan
Prior art keywords
chip
substrate
mounting
pad
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP170689A
Other languages
Japanese (ja)
Inventor
Nobuhiko Muraoka
信彦 村岡
Shinji Kanayama
金山　真司
Takahiro Endo
隆弘 遠藤
Hitoshi Nakamura
仁 中村
Shozo Minamitani
南谷　昌三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP170689A priority Critical patent/JPH02181444A/en
Publication of JPH02181444A publication Critical patent/JPH02181444A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To ensure parallelism to a substrate of an IC chip by forming protrusions in equal height at three points or more on a pad for mounting the IC of the substrate. CONSTITUTION:Protrusions 15 in equal height for keeping the parallelism of an IC chip 13 are shaped to the surface of the mounting pad 14 of the IC chip 13 formed onto a substrate 12. Adhesives 16 are applied in thickness thicker than the protrusions 15, and the IC 13 is held and fitted onto the adhesives 16 by a holding means 17. Accordingly, parallelism to the substrate of the IC chip is ensured, thus mounting the IC with high reliability.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、回路基板の表面に直接ＩＣのベアチップを装
着する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for mounting an IC bare chip directly onto the surface of a circuit board.

従来の技術 近年、ＩＣの装着方法は、ＩＣのベアチップを直接基板
に装着する、いわゆるチップオンボード（ＣＯＢ　：　
Ｃｈｉｐ　　ｏｎ　Ｂｏａｄ　）が普及するにつれ、そ
の重要性がクローズアップされている。Conventional technology In recent years, the mounting method for ICs has become so-called chip-on-board (COB:
As Chip on Board (Chip on Board) becomes more popular, its importance is being focused on.

以下図面を参照しながら、上述した従来のＩＣの装着方
法の一例について説明する。An example of the above-mentioned conventional IC mounting method will be described below with reference to the drawings.

従来のＩＣの装着方法には第２図および第３図に示すも
のがある。第２図において１は基板、２は基板上に形成
された回路、３はＩＣのベアチップ（以下ＩＣチップと
する）を装着するだめのパッド、４はＩＣチップとパッ
ド３とを接合する接合剤、５はＩＣチップ、５ａはＩＣ
チップの回路の接続パッドで、線材６Ｃによって回路２
の一端子６ｂと接続されている、６はＩＣチップを装着
する際ＩＣを保持する保持手段でおる。また第３図にお
いて７は基板、８は基板７上に形成された回路、９はＩ
Ｃチップと接続されるパッド部分、１０はＩＣチップ、
１１．はＩＣチップ１０に設けられた突起で、ＩＣチッ
プ１０と基板回路８との導通も兼ねている。Conventional IC mounting methods include those shown in FIGS. 2 and 3. In FIG. 2, 1 is a substrate, 2 is a circuit formed on the substrate, 3 is a pad for mounting an IC bare chip (hereinafter referred to as IC chip), and 4 is a bonding agent for bonding the IC chip and pad 3. , 5 is an IC chip, 5a is an IC
At the connection pad of the circuit of the chip, the circuit 2 is connected by wire 6C.
The numeral 6, which is connected to one terminal 6b of the IC chip, is a holding means for holding the IC chip when the IC chip is mounted. Further, in FIG. 3, 7 is a substrate, 8 is a circuit formed on the substrate 7, and 9 is an I
Pad part connected to C chip, 10 is IC chip,
11. is a protrusion provided on the IC chip 10, which also serves as conduction between the IC chip 10 and the board circuit 8.

第２図のＩＣチップ６の装着方法は、回路２に接合剤４
を塗布あるいは吐出し、その後、保持手段６によって保
持されたＩＣチップ５を基板１に押し付けるように、保
持手段６が基板１に対して相対的に上下し、ＩＣチップ
６が装着される。このときＩＣの回路構成部は装着面と
反対面になる。The method of mounting the IC chip 6 shown in FIG. 2 is as follows:
is applied or discharged, and then the holding means 6 moves up and down relative to the substrate 1 so as to press the IC chip 5 held by the holding means 6 against the substrate 1, and the IC chip 6 is mounted. At this time, the circuit components of the IC are on the opposite side to the mounting surface.

また、ＩＣチップ５を破損しないためにはあまり大きな
力では押し付けられない。Furthermore, in order to avoid damaging the IC chip 5, it should not be pressed with too much force.

また第３図のＩＣチップ１ｏの装着方法は、あらかじめ
ＩＣチップ１０に設けられた突起１１によって、この突
起１１がＩＣチップ１０と基板７の間にはさまれる様に
して圧接されたときに、ＩＣチップ１０と基板の回路８
との接合がされるとともに、ＩＣチップ１ｏの回路と基
板の回路８の導通も行なう。従って、ＩＣの回路構成部
と装着面は同一面となっている。Furthermore, the mounting method of the IC chip 1o shown in FIG. IC chip 10 and circuit board 8
At the same time, the circuit of the IC chip 1o and the circuit 8 of the substrate are electrically connected. Therefore, the circuit components of the IC and the mounting surface are on the same surface.

発明が解決しようとする課題 しかしながら上記のようなＩＣチップの装着方法では以
下の様な間趙がある。Problems to be Solved by the Invention However, the above-mentioned IC chip mounting method has the following drawbacks.

第２図の例では、ＩＣチップ５の装着後、ＩＣ回路と基
板の回路２の導通を行なうため、ＩＣチップ５の回路の
接続パッド６ａと基板の回路の一端子部６ｂとの間に金
やアルミニウムの細い線材５Ｃにてワイヤリングを処す
。このワイヤリング時に、ＩＣチップ５が基板１２に対
して傾いていると接続不良を起こす。このＩＣチップ６
の傾きは、工Ｃチップ６の装着の瞬間や装着後の接合剤
４の乾燥や硬化時に起こることが多い。この傾きによる
不良の様子を第４図に示す。このうち装着の瞬間の傾き
は、設備の精度同上等で対処できるが、装着後の乾燥時
に発生するものは防ぐ方法がなかった。また第３図の・
列のものでは、第２図の例の様に接合剤４を使用せず、
また直接突起１１によって導通の接続も行なうため、上
記問題は起こり得ないが、−度に多くの接続点を同時に
接合しなければならず、１だＩＣチップ１０の接続パッ
ドと基板の回路９との正確な位置合せが必要となるため
、設備が極めて高価である。In the example shown in FIG. 2, after mounting the IC chip 5, a metal layer is placed between the connection pad 6a of the circuit of the IC chip 5 and one terminal portion 6b of the circuit of the board in order to conduct the IC circuit and the circuit 2 of the board. Wiring is done using thin aluminum wire 5C. During this wiring, if the IC chip 5 is tilted with respect to the substrate 12, a connection failure will occur. This IC chip 6
The inclination often occurs at the moment of mounting the C-chip 6 or when the bonding agent 4 dries or hardens after mounting. FIG. 4 shows the appearance of defects due to this inclination. Of these, tilting at the moment of installation can be dealt with by relying on the accuracy of the equipment, but there was no way to prevent it from occurring during drying after installation. Also, in Figure 3.
In the row type, bonding agent 4 is not used as in the example in Fig. 2,
In addition, since conductive connections are made directly by the protrusions 11, the above-mentioned problem does not occur, but many connection points must be bonded at the same time, and only one connects the connection pads of the IC chip 10 and the circuit 9 of the board. The equipment is extremely expensive because accurate alignment is required.

本発明は上記問題に：薦み、ＩＣチップを基板に安価に
かつ正確に装着し、後工程での製品信頼性を向上し得る
ＩＣの装着方法を提供するものである。The present invention solves the above problem by providing an IC mounting method that can inexpensively and accurately mount an IC chip on a substrate and improve product reliability in subsequent processes.

課題を解決するための手段 上記課沁１を解決するため本発明のＩＣの装着方法は、
ＩＣチップの装着される回路基板の、ＩＣを装着するパ
ッド部分に、３点以上の等しい高さの突起を設け、この
矢起によって、基板とＩＣチップの千行朕を常に保ちな
がらＩＣを基板に装着するものである。Means for Solving the Problems In order to solve the above problem 1, the method for mounting an IC of the present invention is as follows:
Three or more protrusions of equal height are provided on the pad portion of the circuit board on which the IC chip is mounted, and these arrows allow the IC to be mounted on the board while always maintaining the alignment between the board and the IC chip. It is to be attached to.

作　　用 上記した方法によれば、ＩＣチップの装着時の傾きが少
ない。！！だＩＣチップと基板上の回路のＩＣｉ着パッ
ドとの間に塗布される接合剤の乾燥や硬化時においても
、ＩＣを装着するパッド上に設けられた突起によって、
常に基板との平行が保たれ、後工程の線材によるＩＣチ
ップの回路と基板の回路の接続・導通を安定して行なう
ことが可能である。Effect: According to the method described above, there is little inclination when the IC chip is mounted. ! ! Even when the bonding agent applied between the IC chip and the ICi mounting pad of the circuit on the board dries and hardens, the protrusions provided on the pad on which the IC is mounted will
The parallelism with the substrate is always maintained, and it is possible to stably connect and conduct the circuits of the IC chip and the circuits of the substrate using wire rods in the subsequent process.

実施例 以下本発明の一実施例であるＩＣｉ着方法について図面
を参照しながら説明する。第１図Ａ、Ｂに本実施例の斜
視図と断面図を示す。第１図において、基板１２上に設
けられたＩＣチップ１３．の装着パッド１４は、その表
面にＩＣチップ１３の平行度を維持するための等しい高
さの突起１５を備えている。この突起１５より厚く接合
剤１６を塗布し、その上にＩＣを保持手段７によって保
持し、装着をする。EXAMPLE Hereinafter, an ICi attaching method which is an example of the present invention will be described with reference to the drawings. FIGS. 1A and 1B show a perspective view and a sectional view of this embodiment. In FIG. 1, an IC chip 13 . The mounting pad 14 is provided with protrusions 15 of equal height on its surface to maintain the parallelism of the IC chip 13. A bonding agent 16 is applied thicker than the protrusion 15, and the IC is held thereon by the holding means 7 and mounted.

発明の効果 以上の様に、本発明はＩＣを装着しようとする基板のＩ
Ｃを装着するだめのパッド上に、等しい高さの３点以上
の突起を設けることにより、この上に装着されたＩＣは
、ＩＣチップと基板とを接合する接合剤の乾燥や硬化工
程を径ても、ＩＣチップの基板に対する平行度は確保さ
れ、信頼性のあるＩＣの装着が可能となる。Effects of the Invention As described above, the present invention provides an I
By providing three or more protrusions of equal height on the pad on which the IC is mounted, the IC mounted on this pad can be used to avoid the drying and curing process of the bonding agent used to bond the IC chip and the substrate. However, the parallelism of the IC chip to the substrate is ensured, and reliable IC mounting is possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図へ、Ｂは本発明の一実施例におけるＩＣの装着方
法の説明図、第２図Ａ、Ｂ及び第３図ハ。 Ｂは従来のＩＣの装着方法の説明図、第４図は従来のＩ
Ｃの装着方法の問題点の説明図である。 ２・・・・・・基板、 ３・・・・・・ＩＣチップ、 ６・・・・・・ 第 図 接合剤。1 and B are explanatory diagrams of an IC mounting method in an embodiment of the present invention, FIGS. 2A and B, and FIG. 3C. B is an explanatory diagram of the conventional IC mounting method, and Figure 4 is the conventional I
It is an explanatory view of the problem of the mounting method of C. 2...Substrate, 3...IC chip, 6...Bonding agent.

Claims (1)

【特許請求の範囲】[Claims] 　回路パターンの形成された基板と、この基板上の回路
の中にあってＩＣのベアチップを装着するためのパッド
と、このパッド上にあり高さの等しい３点以上の突起を
有する基板上に、ＩＣのベアチップと前記パッドとの接
合をはかるための接合剤を塗布し、ＩＣのベアチップを
保持する手段によりＩＣのベアチップを保持し、かつ前
記接合剤の塗布された、前記パッド上にＩＣのベアチッ
プを置く手段により、ＩＣのベアチップを前記パッド上
に置くＩＣの装着方法。A substrate on which a circuit pattern is formed, a pad for mounting an IC bare chip in the circuit on this substrate, and a substrate having three or more protrusions of equal height on this pad, A bonding agent is applied to bond the IC bare chip and the pad, the IC bare chip is held by means for holding the IC bare chip, and the IC bare chip is placed on the pad coated with the bonding agent. A method for mounting an IC in which a bare chip of an IC is placed on the pad by means of placing a bare IC on the pad.
JP170689A 1989-01-06 1989-01-06 Mounting method of ic Pending JPH02181444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP170689A JPH02181444A (en) 1989-01-06 1989-01-06 Mounting method of ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP170689A JPH02181444A (en) 1989-01-06 1989-01-06 Mounting method of ic

Publications (1)

Publication Number Publication Date
JPH02181444A true JPH02181444A (en) 1990-07-16

Family

ID=11508998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP170689A Pending JPH02181444A (en) 1989-01-06 1989-01-06 Mounting method of ic

Country Status (1)

Country Link
JP (1) JPH02181444A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04192596A (en) * 1990-11-27 1992-07-10 Hitachi Ltd Mounting structure of electronic component

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04192596A (en) * 1990-11-27 1992-07-10 Hitachi Ltd Mounting structure of electronic component

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