JPH11121520A - Ball grid array type semiconductor device - Google Patents

Ball grid array type semiconductor device

Info

Publication number
JPH11121520A
JPH11121520A JP9282211A JP28221197A JPH11121520A JP H11121520 A JPH11121520 A JP H11121520A JP 9282211 A JP9282211 A JP 9282211A JP 28221197 A JP28221197 A JP 28221197A JP H11121520 A JPH11121520 A JP H11121520A
Authority
JP
Japan
Prior art keywords
mounting
semiconductor device
solder
substrate
grid array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9282211A
Other languages
Japanese (ja)
Other versions
JP3070544B2 (en
Inventor
Harumi Mizunashi
晴美 水梨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9282211A priority Critical patent/JP3070544B2/en
Publication of JPH11121520A publication Critical patent/JPH11121520A/en
Application granted granted Critical
Publication of JP3070544B2 publication Critical patent/JP3070544B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Abstract

PROBLEM TO BE SOLVED: To enhance the mounting reliability of a fine pitched BGA. SOLUTION: This semiconductor device has a structure, which has an external terminal 7 on one face of an electrically insulating substrate 3 having wiring patterns 2, and in which a reverse face of the electrically insulating substrate 3 is adhered to a face having an electrode terminal 8 of a semiconductor element 1. The electrode terminal 8 of the semiconductor element is connected electrically to the wiring patterns 2 of the electrically insulating substrate 3. The external terminal 7 has a structure in which a solder ball is connected to a mounting pad, and an electrically insulating sheet 6 having a through-hole in a solder ball mounting part is adhered to the surroundings of the mounting pad.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置、特に
ボール・グリッド・アレイ(BGA)型半導体装置に関
する。
The present invention relates to a semiconductor device, and more particularly to a ball grid array (BGA) type semiconductor device.

【0002】[0002]

【従来の技術】近年、半導体装置の小型軽量化は著し
く、特に携帯電話に代表される携帯型電子機器に用いら
れる半導体装置として、特開平7−321157号公報
に開示されているような装置がある。この装置は、図7
のように配線パターン2を有する電気絶縁基板3の片面
に外部端子7を有し、反対面を半導体素子1の電極端子
8を有する面に張合わせ、半導体素子1の電極端子8と
電気絶縁基板3の配線パターン2とを電気的に接続した
構造を有している。4はソルダーレジストである。以下
この装置をファインピッチBGAという。このようなフ
ァインピッチBGAの外部端子は、電気絶縁基板上の電
極パッドに球状またはペレット状の金属ロー材を仮付け
したり、あるいは、金属ロー材を粉末状にし、フラック
スと混ぜペースト状にし、電極パッドにスクリーン印刷
し、その後金属ロー材の融点以上の温度でリフローする
ことで接着し、かつ形状を整えたものである。金属ロー
材には、共晶半田が多く用いられているが、球状の高融
点半田を共晶半田でコーティングしたものや球状の高融
点半田を共晶半田のペーストで接着するものもある。
2. Description of the Related Art In recent years, the size and weight of semiconductor devices have been remarkably reduced. In particular, as a semiconductor device used for portable electronic equipment typified by a portable telephone, a device disclosed in Japanese Patent Application Laid-Open No. 7-32157 has been proposed. is there. This device is shown in FIG.
The external terminal 7 is provided on one surface of the electrically insulating substrate 3 having the wiring pattern 2 and the opposite surface is bonded to the surface having the electrode terminal 8 of the semiconductor element 1 as shown in FIG. 3 is electrically connected to the wiring pattern 2. 4 is a solder resist. Hereinafter, this device is called a fine pitch BGA. The external terminal of such a fine pitch BGA is formed by temporarily attaching a metal brazing material in the form of a sphere or a pellet to an electrode pad on an electrically insulating substrate, or by powdering the metal brazing material, mixing it with a flux to form a paste, The electrode pad is screen-printed and then reflowed at a temperature equal to or higher than the melting point of the metal brazing material to bond and form the electrode pad. Eutectic solder is often used as the metal brazing material, but there is also a material in which spherical high melting point solder is coated with eutectic solder, and a case in which spherical high melting point solder is bonded with eutectic solder paste.

【0003】従来、外部端子に球状の共晶半田を用いた
半導体装置には、ファインピッチBGA以外には、プラ
スチック・ボール・グリッド・アレイ(以下、P・BG
Aという)といわれるものがある。P・BGAの場合、
外部端子は、ピッチが1mmまたは1.27mmと比較
的に広く、外部端子である球状の共晶半田も直径0.7
mm〜0.9mmと大きく、しかも共晶半田であるた
め、リフロー時に外部端子部分が完全に溶融し、半田の
表面張力に基づくセルフアライメントが働くため、基板
に実装する場合の位置合わせ精度はさほど必要なく、ま
た、実装後、はんだ接合部に加わるP・BGAと基板と
の熱膨張率の差から生じる熱ストレスは基板とP・BG
A基体とのギャップが大きいほど小さくなるが、P・B
GAの場合、このギャップが十分あり、基板とP・BG
A基体との熱膨張率の差から生じる熱ストレスを外部端
子であるはんだボールに十分に吸収でき、この結果、高
い信頼性が得られるという特徴があった。
Conventionally, semiconductor devices using spherical eutectic solder for external terminals include plastic ball grid arrays (hereinafter, P.BG) in addition to fine pitch BGA.
A). For P / BGA,
The external terminals have a relatively large pitch of 1 mm or 1.27 mm, and the spherical eutectic solder, which is an external terminal, has a diameter of 0.7 mm.
mm to 0.9 mm and the eutectic solder completely melts the external terminals during reflow, and performs self-alignment based on the surface tension of the solder. Not necessary, and after mounting, the thermal stress caused by the difference in the coefficient of thermal expansion between the P · BGA applied to the solder joint and the board is reduced by the P · BG
The smaller the gap with the A base, the smaller the gap.
In the case of GA, this gap is sufficient, and the substrate and P / BG
The thermal stress caused by the difference in the coefficient of thermal expansion from the base A can be sufficiently absorbed by the solder balls as the external terminals, and as a result, high reliability is obtained.

【0004】これに対し、ファインピッチBGAの外部
端子のピッチは、0.4mm〜0.8mm、外部端子の
大きさが0.1mm〜0.4mmであり、基板に実装す
る場合の位置精度に高いレベルに要求されていた。ま
た、実装後基板とファインピッチBGA基体とのギャッ
プが狭くなり、かつファインピッチBGAの場合外形サ
イズが半導体素子の外形サイズに近いため、全体の熱膨
張率が半導体素子の基材であるシリコンの影響を強く受
け、P・BGAと比べ小さくなり、基板との熱膨張率の
差が大きくなり、実装信頼性が低下するという問題があ
る。
On the other hand, the pitch of the external terminals of the fine pitch BGA is 0.4 mm to 0.8 mm, and the size of the external terminals is 0.1 mm to 0.4 mm. Demanded to a high level. In addition, since the gap between the board after mounting and the fine pitch BGA base becomes narrow, and the outer size of the fine pitch BGA is close to the outer size of the semiconductor element, the overall thermal expansion coefficient of the silicon There is a problem that it is strongly affected, becomes smaller than P.BGA, a difference in thermal expansion coefficient with the substrate becomes large, and mounting reliability is reduced.

【0005】このため、特開平8−236654号公報
に開示されているように実装前に、はんだボールの周辺
部を樹脂で覆う方法や、実装後基板とファインピッチB
GAの基体間に樹脂を充填する方法(以下アンダーフィ
ルという)を用いて実装の信頼性を確保していた。
For this reason, as disclosed in Japanese Patent Application Laid-Open No. Hei 8-236654, a method of covering the peripheral portion of a solder ball with a resin before mounting, or a method of mounting a substrate with a fine pitch B
A method of filling a resin between GA bases (hereinafter referred to as an underfill) has been used to ensure mounting reliability.

【0006】[0006]

【発明が解決しようとする課題】ところが、上記方法に
よるときに生ずる第1の問題点は、特開平8−2366
54号公報に開示されているように実装前に、はんだボ
ールの周辺部を樹脂で覆う方法では、ファインピッチB
GAのはんだボール周辺部を樹脂覆うことが極めて困難
であるということである。
However, the first problem that arises with the above method is that disclosed in Japanese Patent Laid-Open No. Hei 8-2366.
As disclosed in Japanese Patent Application Publication No. 54-54, the method of covering the peripheral portion of the solder ball with a resin before mounting requires fine pitch B
This means that it is extremely difficult to cover the periphery of the GA solder ball with resin.

【0007】その理由は、ファインピッチBGAの外部
端子ピッチは、0.4mm〜0.8mmであり、外部端
子であるはんだボールの大きさが0.1mm〜0.4m
mと小さいため、ポッティングや印刷では十分な精度が
得られず、本来樹脂が付着してはならない部分、例えば
はんだボールを搭載する電極パッド等にも樹脂が付着し
てしまうためである。
The reason is that the external terminal pitch of the fine pitch BGA is 0.4 mm to 0.8 mm, and the size of the solder ball as the external terminal is 0.1 mm to 0.4 m.
This is because, since the resin is small, sufficient accuracy cannot be obtained by potting or printing, and the resin adheres to portions to which the resin should not originally adhere, such as electrode pads on which solder balls are mounted.

【0008】第2の問題点は、アンダーフィルを施した
場合は、実装後半導体装置に不具合が見つかった場合、
リペアーが困難であるということである。
The second problem is that when underfilling is performed, if a defect is found in the semiconductor device after mounting,
It is difficult to repair.

【0009】その理由は、樹脂が実装基板とファインピ
ッチBGA基体に接着されているため、リペアーする場
合、まず樹脂を除去しなければならないが、実装基板に
ダメージを与えず除去する方法がないからである。
The reason is that, since the resin is bonded to the mounting board and the fine pitch BGA base, the resin must be removed first when repairing, but there is no method for removing the mounting board without damaging it. It is.

【0010】本発明の目的は、ファインピッチBGAの
実装後、基板とファインピッチBGA基体との熱膨張率
の差から生じる熱ストレスによる影響から外部端子であ
るはんだボールの破壊を防ぎ、高い信頼性が得られるよ
うにしたボール・グリッド・アレイ型半導体装置を提供
することにある。
SUMMARY OF THE INVENTION It is an object of the present invention to prevent a solder ball as an external terminal from being destroyed due to the effect of thermal stress caused by a difference in thermal expansion coefficient between a substrate and a fine pitch BGA base after mounting a fine pitch BGA. Is to provide a ball grid array type semiconductor device capable of obtaining the following.

【0011】[0011]

【課題を解決するための手段】上記目的を達成するた
め、本発明によるボール・グリッド・アレイ型半導体装
置においては、配線パターンを有する電気絶縁基板の一
面に外部端子を有し、電気絶縁板の反対面は半導体素子
の電極端子を有する面に張合わされ、前記半導体素子の
電極端子と前記電気絶縁基板の配線パターンとを電気的
に接続するボール・グリッド・アレイ型半導体装置であ
って、電気絶縁シートを有し、外部端子は、搭載パッド
にはんだボールを接続した構造をなし、電気絶縁シート
は、はんだボール搭載部に貫通孔を有し、搭載パッド周
縁に貼り付けられたものである。
In order to achieve the above object, in a ball grid array type semiconductor device according to the present invention, an external terminal is provided on one surface of an electric insulating substrate having a wiring pattern, and A ball grid array type semiconductor device, wherein the opposite surface is bonded to a surface having electrode terminals of the semiconductor element, and electrically connects the electrode terminals of the semiconductor element and the wiring pattern of the electrically insulating substrate. The external terminal has a structure in which a solder ball is connected to a mounting pad, and the electric insulating sheet has a through hole in a solder ball mounting portion and is attached to a periphery of the mounting pad.

【0012】また、電気絶縁シートの厚さは、50μm
以上である。
The thickness of the electric insulating sheet is 50 μm.
That is all.

【0013】また、ボール・グリッド・アレイ型半導体
装置は基板に実装され、外部端子のはんだボールは、電
気絶縁シートの貫通孔の形状と、実装基板にできる球状
のはんだとを合わせた形状となって実装高さを増大させ
るものである。
Further, the ball grid array type semiconductor device is mounted on a substrate, and the solder balls of the external terminals have a shape obtained by combining the shape of the through hole of the electric insulating sheet with the spherical solder formed on the mounting substrate. This increases the mounting height.

【0014】また、ボール・グリッド・アレイ型半導体
装置は基板に実装され、外部端子のはんだボールは、電
極パット部に加わるストレスを減少させるものである。
The ball grid array type semiconductor device is mounted on a substrate, and the solder balls of the external terminals reduce the stress applied to the electrode pads.

【0015】外部端子搭載面に貼り付けたはんだボール
搭載部に貫通孔を有した電気絶縁シートにより、ファイ
ンピッチBGAを基板に実装した場合、はんだ接合部の
形状は、単純な球状にはならず、電気絶縁シートの貫通
孔の径より横に広がらないため、貫通孔の形状と貫通孔
の下(実装基板側)にできる球状のはんだと合わせた形
状、たとえばだるまのような形状になり、結果的に高さ
方向に大きくなるため、基板とファインピッチBGA間
の距離が大きくなり、ファインピッチBGAの実装後、
接合部に生じる基板とファインピッチBGA基体との熱
膨張率の差から生じる熱ストレスを緩和できる。
When a fine pitch BGA is mounted on a substrate by an electric insulating sheet having a through hole in a solder ball mounting portion attached to an external terminal mounting surface, the shape of the solder joint does not become a simple sphere. However, since it does not spread horizontally beyond the diameter of the through hole of the electric insulating sheet, the shape of the through hole and the shape of the spherical solder formed below the through hole (on the mounting board side) are combined, for example, a ball-like shape, and as a result, In the height direction, the distance between the substrate and the fine pitch BGA increases, and after mounting the fine pitch BGA,
Thermal stress caused by the difference in the coefficient of thermal expansion between the substrate and the fine pitch BGA substrate generated at the joint can be reduced.

【0016】[0016]

【発明の実施の形態】次に本発明の実施の形態について
図1を参照して詳細に説明する。図1において、ファイ
ンピッチBGAは、配線パターンを有する電気絶縁基板
3の一面に外部端子7を有し、反対面が半導体素子1の
電極8を有する面に張合わされている。半導体素子1の
電極8と電気絶縁基板3の配線パターン2とは、電気的
に接続されている。本発明は、外部端子7は、搭載パッ
ドに、はんだボールを接続し、はんだボール搭載部に貫
通孔を有する電気絶縁シート6を接着剤5で搭載パッド
の周辺のソルダーレジスト4上に貼り付けたものであ
る。
Next, an embodiment of the present invention will be described in detail with reference to FIG. In FIG. 1, the fine pitch BGA has external terminals 7 on one surface of an electrically insulating substrate 3 having a wiring pattern, and the opposite surface is bonded to a surface having electrodes 8 of the semiconductor element 1. The electrode 8 of the semiconductor element 1 and the wiring pattern 2 of the electrically insulating substrate 3 are electrically connected. In the present invention, the external terminals 7 are formed by connecting solder balls to mounting pads, and attaching an electric insulating sheet 6 having through holes in the solder ball mounting portion to the solder resist 4 around the mounting pads with an adhesive 5. Things.

【0017】[0017]

【実施例】次に本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0018】図1は、本発明の実施例を示す概略断面図
である。
FIG. 1 is a schematic sectional view showing an embodiment of the present invention.

【0019】図1において、ポリイミド樹脂製の電気絶
縁基板3の一面には、図示を省略しているがポリイミド
系熱可塑性樹脂の接着剤が貼付けてある。電気絶縁基板
3は厚さが20〜30μm、接着剤の層の厚さは、5〜
10μmであり、その厚さは、接着すべき半導体素子1
とほぼ同じ厚さにしてある。
In FIG. 1, although not shown, an adhesive of a polyimide-based thermoplastic resin is adhered to one surface of an electric insulating substrate 3 made of a polyimide resin. The thickness of the electrically insulating substrate 3 is 20 to 30 μm, and the thickness of the adhesive layer is 5 to 30 μm.
10 μm, and the thickness thereof is
It has almost the same thickness as.

【0020】半導体素子1の電極8と、電気絶縁基板3
の配線パターン2とに熱と荷重と超音波とを加えて両者
を接続し、その後、300℃前後の熱と1Kg/cm2
の荷重を加えて半導体素子1と電気絶縁基板3とを接着
する。配線パータンは圧延銅箔をエッチングし、電解銅
めっきを施すことにより形成している。なお、配線パタ
ーン2の外部端子7側に外部端子7を搭載する部分(以
下、電極パッドという)を除いてソルダーレジスト4と
して厚さ10〜15μmのポリイミド樹脂を塗布してい
る。
The electrode 8 of the semiconductor element 1 and the electrically insulating substrate 3
And heat and a load and an ultrasonic wave are applied to the wiring pattern 2 to connect them, and then heat of about 300 ° C. and 1 kg / cm 2 are applied.
The semiconductor element 1 and the electrically insulating substrate 3 are adhered by applying a load of. The wiring pattern is formed by etching a rolled copper foil and applying electrolytic copper plating. The solder resist 4 is coated with a polyimide resin having a thickness of 10 to 15 μm except for a portion (hereinafter referred to as an electrode pad) on which the external terminal 7 is mounted on the external terminal 7 side of the wiring pattern 2.

【0021】ソルダーレジスト4の上には、電極パッド
部に電極パッド部より大きい開口部を有するポリイミド
樹脂製の絶縁シート6を熱硬化性ポリイミド樹脂性の接
着剤5を用いて接着している。絶縁シート6の厚さは5
0μm以上、特に95〜105μmであり、電極パッド
の大きさは直径175〜185μm、絶縁シート6の電
極パッド部の開口径は、直径290〜310μm、接着
剤5の厚さは、10〜20μmである。なお、絶縁シー
ト6を接着するとき、電極パッド部に接着剤5が流れ込
まないように接着剤5の量(厚さ)、電極パッドの大き
さに対する絶縁シート6の電極パッド部の開口径を決定
する。
On the solder resist 4, an insulating sheet 6 made of a polyimide resin having an opening in the electrode pad portion larger than the electrode pad portion is adhered by using a thermosetting polyimide resin adhesive 5. The thickness of the insulating sheet 6 is 5
0 μm or more, particularly 95 to 105 μm, the size of the electrode pad is 175 to 185 μm, the opening diameter of the electrode pad portion of the insulating sheet 6 is 290 to 310 μm, and the thickness of the adhesive 5 is 10 to 20 μm. is there. When the insulating sheet 6 is bonded, the amount (thickness) of the adhesive 5 and the opening diameter of the electrode pad portion of the insulating sheet 6 with respect to the size of the electrode pad are determined so that the adhesive 5 does not flow into the electrode pad portion. I do.

【0022】その後、外部端子7としてボール状のSn
とPbの共晶はんだを電極パッド部に載せてこれをリフ
ローすることにより接続している。
Thereafter, a ball-shaped Sn is used as the external terminal 7.
The eutectic solder of Pb and Pb is placed on the electrode pad portion and connected by reflow.

【0023】本実施例のサンプルと従来例のサンプルを
基板に実装し、温度サイクル試験を行った結果を表1に
示す。表1の結果から分るように本実施例を適用するこ
とで大幅に寿命が伸び、実装信頼性が向上することが分
る。
Table 1 shows the results of a temperature cycle test in which the sample of this embodiment and the sample of the conventional example were mounted on a substrate. As can be seen from the results shown in Table 1, it can be seen that the application of this embodiment greatly extends the life and improves the mounting reliability.

【0024】[0024]

【表1】 [Table 1]

【0025】なお、実装基板はFR−4といわれるガラ
ス布・エポキシ樹脂製で、厚さ0.8mmの両面基板で
ある。電極パッドサイズは、直径0.3mm、ピッチが
0.5mm、予備はんだとして実装基板側の電極パッド
に一定量(直径0.2mmの球相当)のはんだを供給し
ている。温度サイクルは−20℃〜125℃の条件で行
っている。なお図2に示すようにソルダーレジスト4と
絶縁シート6との間に隙間(フクレ等)が生じないよう
に、空気抜き用に電極パッドに対応する開口部以外にも
直径0.05〜0.1mmの空気抜き用貫通孔12を設
けることができる。
The mounting substrate is a double-sided substrate made of glass cloth / epoxy resin called FR-4 and having a thickness of 0.8 mm. The electrode pad size is 0.3 mm in diameter, the pitch is 0.5 mm, and a certain amount of solder (equivalent to a ball having a diameter of 0.2 mm) is supplied to the electrode pads on the mounting board side as preliminary solder. The temperature cycle is performed at a temperature of -20C to 125C. In addition, as shown in FIG. 2, in order to prevent a gap (such as blister) from being generated between the solder resist 4 and the insulating sheet 6, a diameter of 0.05 to 0.1 mm other than the opening corresponding to the electrode pad for air release is used. Air vent through hole 12 can be provided.

【0026】本発明によれば、ファインピッチBGAを
実装後、実装基板との実装高を高く出来る。
According to the present invention, after mounting the fine pitch BGA, the mounting height with the mounting substrate can be increased.

【0027】本実施例のファインピッチBGAを実装し
た場合の概略断面図を図3に示し、比較のため、従来の
ファインピッチBGAを実装した場合の概略断面図を図
4に示す。
FIG. 3 is a schematic cross-sectional view when the fine pitch BGA of this embodiment is mounted, and FIG. 4 is a schematic cross-sectional view when the conventional fine pitch BGA is mounted for comparison.

【0028】本発明によれば、図3に示すとおり、外部
端子7の搭載面に貼り付けたはんだボール搭載部に貫通
孔を有する電気絶縁シート6を用いてファインピッチB
GAを基板に実装した場合に、はんだボールの形状は、
単純な球状にはならず、電気絶縁シート6の貫通孔の径
より横に広がらないため、貫通孔の形状と貫通孔の下
(実装基板側)にできる球状のはんだと合わせてだるま
のような形状になり、結果的に高さ方向に大きくなるた
め、図4の従来例に比して実装基板9とファインピッチ
BGA間の距離が大きくなる。図3のh1が本実施例の
実装高、図4のh2が従来の実装高である。本実施例の
実装高h1が0.17mmに対し、従来例の実装高h2
が0.09mmである。
According to the present invention, as shown in FIG. 3, a fine pitch B is formed by using an electric insulating sheet 6 having a through hole in a solder ball mounting portion attached to a mounting surface of an external terminal 7.
When the GA is mounted on the board, the shape of the solder ball is
Since it does not become a simple sphere and does not spread laterally beyond the diameter of the through hole of the electric insulating sheet 6, the shape of the through hole and the spherical solder formed below the through hole (on the mounting substrate side) are like a ball. As a result, the distance between the mounting board 9 and the fine pitch BGA is increased as compared with the conventional example of FIG. H1 in FIG. 3 is the mounting height of the present embodiment, and h2 in FIG. 4 is the mounting height in the related art. While the mounting height h1 of the present embodiment is 0.17 mm, the mounting height h2 of the conventional example is
Is 0.09 mm.

【0029】また、本発明によれば、ファインピッチB
GAを実装後、はんだ接合部の熱ストレスを分散でき
る。
According to the present invention, the fine pitch B
After mounting the GA, the thermal stress at the solder joint can be dispersed.

【0030】本実施例のファインピッチBGAを実装し
た場合の概略部分断面図を図5に示し、比較のため、従
来のファインピッチBGAを実装した場合の概略部分断
面図を図6に示す。
FIG. 5 is a schematic partial cross-sectional view when the fine pitch BGA of this embodiment is mounted, and FIG. 6 is a schematic partial cross-sectional view when the conventional fine pitch BGA is mounted for comparison.

【0031】通常、ファインピッチBGAの電極パッド
サイズは、実装基板の電極サイズより小さく、実装後熱
ストレスで破損する場合はファインピッチBGA側の電
極パッド部aである。
Usually, the electrode pad size of the fine pitch BGA is smaller than the electrode size of the mounting board, and if it is damaged by thermal stress after mounting, it is the electrode pad section a on the fine pitch BGA side.

【0032】しかし、本実施例によるときには、外部端
子のはんだボールの途中を絶縁シート6が押えているた
め、この部分bでも熱ストレスが発生し、ファインピッ
チBGA側の電極パッド部aに加わる熱ストレスを減少
できるためである。従来例では、はんだ接合部の途中が
押えられないため、電極パッド部aには大きな熱ストレ
スが加えられる。
However, according to the present embodiment, since the insulating sheet 6 presses the middle of the solder ball of the external terminal, thermal stress also occurs in this portion b, and the heat applied to the electrode pad portion a on the fine pitch BGA side. This is because stress can be reduced. In the conventional example, a large thermal stress is applied to the electrode pad portion a because the middle of the solder joint is not pressed.

【0033】[0033]

【発明の効果】以上のように本発明によれば、ファイン
ピッチBGAを実装基板に実装後、接合部の信頼性が向
上し、ファインピッチBGAと実装基板の間にアンダー
フィルを施さなくとも十分な信頼性が得られる。
As described above, according to the present invention, after mounting the fine pitch BGA on the mounting board, the reliability of the joint is improved, and it is sufficient to provide no underfill between the fine pitch BGA and the mounting board. Reliability can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す概略断面図である。FIG. 1 is a schematic sectional view showing one embodiment of the present invention.

【図2】本発明の他の実施例を示す部分拡大図である。FIG. 2 is a partially enlarged view showing another embodiment of the present invention.

【図3】本発明の実施例の効果を説明するための概略断
面図である。
FIG. 3 is a schematic sectional view for explaining the effect of the embodiment of the present invention.

【図4】比較のために示した従来例の概略断面図であ
る。
FIG. 4 is a schematic sectional view of a conventional example shown for comparison.

【図5】本発明の実施例の効果を説明するための部分拡
大断面図である。
FIG. 5 is a partially enlarged sectional view for explaining the effect of the embodiment of the present invention.

【図6】比較のために示した従来例の部分拡大断面図で
ある。
FIG. 6 is a partially enlarged sectional view of a conventional example shown for comparison.

【図7】本発明の従来例を示す概略断面図である。FIG. 7 is a schematic sectional view showing a conventional example of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 配線パターン 3 電気絶縁基板 4 ソルダーレジスト 5 接着剤 6 絶縁シート 7 外部端子 8 電極 9 実装基板 10 配線パータン 11 ソルダーレジスト 12 空気抜き用貫通孔 h1,h2 実装高を示す記号 a,b 接合部の場所を示す記号 d1,d2,d3 接合部の直径を示す記号 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Wiring pattern 3 Electrical insulating substrate 4 Solder resist 5 Adhesive 6 Insulating sheet 7 External terminal 8 Electrode 9 Mounting substrate 10 Wiring pattern 11 Solder resist 12 Air vent through-hole h1, h2 Symbol indicating mounting height a, b Bonding Symbol indicating the location of the part d1, d2, d3 Symbol indicating the diameter of the joint

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 配線パターンを有する電気絶縁基板の一
面に外部端子を有し、電気絶縁板の反対面は半導体素子
の電極端子を有する面に張合わされ、前記半導体素子の
電極端子と前記電気絶縁基板の配線パターンとを電気的
に接続するボール・グリッド・アレイ型半導体装置であ
って、電気絶縁シートを有し、 外部端子は、搭載パッドにはんだボールを接続した構造
をなし、 電気絶縁シートは、はんだボール搭載部に貫通孔を有
し、搭載パッド周縁に貼り付けられたものであることを
特徴とするボール・グリッド・アレイ型半導体装置。
An electric insulating substrate having a wiring pattern has external terminals on one surface thereof, and an opposite surface of the electric insulating plate is bonded to a surface having electrode terminals of the semiconductor element, and is electrically connected to the electrode terminals of the semiconductor element. A ball grid array type semiconductor device electrically connecting a wiring pattern of a substrate, the device having an electric insulating sheet, external terminals having a structure in which solder balls are connected to mounting pads, A ball grid array type semiconductor device having a through hole in a solder ball mounting portion and attached to a periphery of a mounting pad.
【請求項2】 電気絶縁シートの厚さは、50μm以上
であることを特徴とする請求項1に記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the thickness of the electric insulating sheet is 50 μm or more.
【請求項3】 請求項1に記載のボール・グリッド・ア
レイ型半導体装置は基板に実装され、 外部端子のはんだボールは、電気絶縁シートの貫通孔の
形状と、実装基板にできる球状のはんだとを合わせた形
状となって実装高さを増大させるものであることを特徴
とするボール・グリッド・アレイ型半導体装置。
3. The ball grid array type semiconductor device according to claim 1, wherein the semiconductor device is mounted on a substrate, and the solder balls of the external terminals are formed of a through hole of an electric insulating sheet and a spherical solder formed on the mounting substrate. A ball grid array type semiconductor device characterized in that the height of the mounting is increased by adopting a shape combining the above.
【請求項4】 請求項1に記載のボール・グリッド・ア
レイ型半導体装置は基板に実装され、 外部端子のはんだボールは、電極パット部に加わるスト
レスを減少させるものであることを特徴とするボール・
グリッド・アレイ型半導体装置。
4. The ball grid array type semiconductor device according to claim 1, wherein the ball is mounted on a substrate, and the solder ball of the external terminal reduces a stress applied to an electrode pad portion.・
Grid array type semiconductor device.
JP9282211A 1997-10-15 1997-10-15 Ball grid array type semiconductor device Expired - Lifetime JP3070544B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9282211A JP3070544B2 (en) 1997-10-15 1997-10-15 Ball grid array type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9282211A JP3070544B2 (en) 1997-10-15 1997-10-15 Ball grid array type semiconductor device

Publications (2)

Publication Number Publication Date
JPH11121520A true JPH11121520A (en) 1999-04-30
JP3070544B2 JP3070544B2 (en) 2000-07-31

Family

ID=17649518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9282211A Expired - Lifetime JP3070544B2 (en) 1997-10-15 1997-10-15 Ball grid array type semiconductor device

Country Status (1)

Country Link
JP (1) JP3070544B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002239780A (en) * 2001-02-09 2002-08-28 Nippon Steel Corp Solder alloy, solder ball and electronic member having solder bump
JP2007027576A (en) * 2005-07-20 2007-02-01 Rohm Co Ltd Semiconductor device
JP2010040599A (en) * 2008-07-31 2010-02-18 Sanyo Electric Co Ltd Semiconductor module and semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002239780A (en) * 2001-02-09 2002-08-28 Nippon Steel Corp Solder alloy, solder ball and electronic member having solder bump
JP2007027576A (en) * 2005-07-20 2007-02-01 Rohm Co Ltd Semiconductor device
JP2010040599A (en) * 2008-07-31 2010-02-18 Sanyo Electric Co Ltd Semiconductor module and semiconductor device

Also Published As

Publication number Publication date
JP3070544B2 (en) 2000-07-31

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