JPH02105701A - Bias circuit for microwave integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the chip area of a microwave integrated circuit by forming an inductance pattern on a dielectric substance layer and constituting a bias circuit of a low-pass filter of the inductances and parasitic capacitances. CONSTITUTION:A dielectric substance layer 9 having a high dielectric constant is formed on a grounding metal 12 on a GaAs FET substrate 1 conducted with a grounding metal 13 on the rear of the substrate 1 through a through hole 10 and inductors 11 are formed on the upper surface of the layer 9 in a pattern. When the inductors 11 are formed in such way, parallel capacitances C are produced between the electrodes of the inductors and grounding metal 12 on the substrate 1. Therefore, the bias circuit thus formed has serial inductances and parallel capacitances and constitutes a low-pass filter. Therefore, the bias circuit of a GaAs monolithic microwave integrated circuit MMIC can be minia turized and the chip area of the MMIC can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to miniaturization of the bias circuit pattern of a tlGmAm monolithic microwave integrated circuit (hereinafter referred to as GaAm M!14IC).

[Conventional technology]

FIG. 3 is a chip pattern diagram of a conventional GmAa MMIC, in which a GaAsFET ft microwave amplification circuit is constructed. In the figure, (1)
T! A G5As field effect transistor (hereinafter referred to as GaAs FET) consisting of a GmA-substrate, a 121i gate terminal G, a drain terminal, and a source terminal S, +31 and (
4) Input matching circuit and output matching circuit consisting of a haopen stub, +51 [inductor, 181i capacitor, (
7) and (8) are a gate bias terminal and a drain bias terminal for applying a bias voltage to the gate terminal G and drain terminal S of the GaAs FET, a 191i capacitor (6) a dielectric layer with a high permittivity that constitutes the entire structure, ( lOl
This is a through hole for connecting the source electrode S to the ground plane on the back surface.

GaAa MMIC chip HGaAa shown in FIG.
Since the input matching circuit (3) and the output matching circuit (4) are attached to the gate terminal and drain terminal of the GaAs FET 121 made on the substrate (1), the GaAs FET 121 is connected to the signal input.
The signal is amplified at the input and output ends of the sPET 121 without reflection loss.

[Problem to be solved by the invention]

To be safe, the bias voltage at the gate terminal G and drain terminal of GaAa PET is applied through a bias circuit of a low-pass filter consisting of an independent inductor and capacitor. As a result, the shape of the bias circuit becomes larger, which inevitably increases the chip area of the G5As MMIG, which is a problem.

This invention was made to solve the above problems, and by downsizing the bias circuit of G5As MMIC, GaAs MM with a small chip area can be realized.
The purpose is to obtain ICf.

[Tanu's means of solving problems]

The bias circuit for a GaAs MMIC according to the present invention has an inductor pattern formed directly on top of a dielectric layer having a high dielectric constant to constitute a low-pass filter.

[Effect]

In the bias circuit for GaAm MMIC of the present invention, a low-pass filter is fabricated by fully utilizing the parasitic capacitance of an inductor formed on a dielectric layer.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a GaAa MMI using the bias circuit of this invention.
A chip pattern diagram of C is shown. In the figures, the same parts are indicated by the same reference numerals as in the conventional system.

In the figure, the bias circuit of the present invention is constructed with an inductor that contains a large parasitic capacitance, and the ground metal on the GaAA substrate is shown to make sure that the inductor contains a parasitic capacitance.

FIG. 2 is a cross-sectional view of the bias circuit (11) of the present invention.
A sectional view taken along the line ■-■ in FIG. 1 is shown.

In the bias circuit of the present invention shown in FIGS. 1 and 2, conduction occurs between the back surface ground metal α of the GaAv substrate (1) and the through hole α0). A dielectric layer (9) with a thin dielectric constant is formed, and an inductor (11) is patterned on the upper surface of this dielectric layer (9).

In this case, the electrode of the inductor (11) and the GaAa FE
Capacitance C in parallel between ground metal 0 force on T board
occurs. Therefore, the inductor (1) is placed on the dielectric layer (9).
The bias circuit of the present invention in which the electrode pattern 1) is formed has a series inductance and a parallel capacitance, and constitutes a low-pass filter.

Therefore, similar to the conventional bias circuit composed of independent inductors and capacitors, the bias circuit of the present invention functions as a bias circuit (passing the bias voltage, which is a DC voltage, and blocking the microwave signal power). .

As a reminder, in the bias circuit of this invention, the inductor is formed on a dielectric layer (9) with a high dielectric constant, and a low-pass filter is constructed using the parasitic capacitance of the inductor. Compared to some conventional bias circuits, the chip area of ω GaAs MMICs can be significantly reduced.

■ It becomes easier to draw the bias circuit.

There is an advantage.

In addition, in the above embodiment, T'S GaAa MMIC (D case) was explained, but MMt c using a semiconductor other than GaA.

Needless to say, similar effects can be obtained with SIM MMIC, for example.

〔Effect of the invention〕

As described above, according to this invention, an inductor pattern is formed on a dielectric layer, and a bias circuit is configured with a low-pass filter using this inductance and parasitic capacitance, so that the chip area of a microwave integrated circuit can be reduced. It has the effect of being able to

[Brief Description of the Drawings] FIG. 1 shows a GaAa M? according to an embodiment of the present invention. vi
IC chip pattern diagram, Figure 2 is a cross-sectional view of the bias circuit taken along the line ■-■ in Figure 1, Figure 3 is the conventional GmAs
It is a chip pattern diagram of MMIC. In the figure, Ill T'S GmAm substrate, 1211
'CGsAa FET. (3) is an input matching circuit, t41d output conditioning output path, t51
1! Inductor, 181H capacitor, (71 [gate bias terminal, +8) u drain bias terminal, (91
1! Dielectric layer, (101 is a through hole, (■) is a bias circuit, (I21 is a ground metal on the G self A- board, (1
3 is the back ground metal. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A bias circuit for a microwave integrated circuit, characterized in that an inductor pattern is formed on a dielectric layer on a semiconductor substrate, and a low-pass filter is configured by the inductance and parasitic capacitance.