JPH02105701A - Bias circuit for microwave integrated circuit - Google Patents

Bias circuit for microwave integrated circuit

Info

Publication number
JPH02105701A
JPH02105701A JP25972988A JP25972988A JPH02105701A JP H02105701 A JPH02105701 A JP H02105701A JP 25972988 A JP25972988 A JP 25972988A JP 25972988 A JP25972988 A JP 25972988A JP H02105701 A JPH02105701 A JP H02105701A
Authority
JP
Japan
Prior art keywords
bias circuit
circuit
bias
microwave integrated
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25972988A
Other languages
Japanese (ja)
Inventor
Tetsuo Mori
哲郎 森
Masahide Yamauchi
山内 眞英
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP25972988A priority Critical patent/JPH02105701A/en
Publication of JPH02105701A publication Critical patent/JPH02105701A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Microwave Amplifiers (AREA)

Abstract

PURPOSE:To reduce the chip area of a microwave integrated circuit by forming an inductance pattern on a dielectric substance layer and constituting a bias circuit of a low-pass filter of the inductances and parasitic capacitances. CONSTITUTION:A dielectric substance layer 9 having a high dielectric constant is formed on a grounding metal 12 on a GaAs FET substrate 1 conducted with a grounding metal 13 on the rear of the substrate 1 through a through hole 10 and inductors 11 are formed on the upper surface of the layer 9 in a pattern. When the inductors 11 are formed in such way, parallel capacitances C are produced between the electrodes of the inductors and grounding metal 12 on the substrate 1. Therefore, the bias circuit thus formed has serial inductances and parallel capacitances and constitutes a low-pass filter. Therefore, the bias circuit of a GaAs monolithic microwave integrated circuit MMIC can be minia turized and the chip area of the MMIC can be reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明tlGmAmモノリシックマイクロ波集積回路
(以下GaAm M!14ICと称す)のバイアス回路
パターンの小型化に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to miniaturization of the bias circuit pattern of a tlGmAm monolithic microwave integrated circuit (hereinafter referred to as GaAm M!14IC).

〔従来の技術〕[Conventional technology]

第3図は従来のGmAa MMICのチップパターン図
であり、GaAsFET ft用い念マイクロ波増幅回
路がこのチップに構成されている。図において、(1)
t!GmA−基板、121iゲート端子G、ドレイン端
子り、ソース端子SよりなるG5As電界効果トランジ
スタ(以下GaAs FETと称す) 、+31及び(
4)ハオープンスタブよりなる入力整合回路及び出力整
合回路、+51[インダクタ、181iキヤパシタ、(
7)及び(8)はGaAs FETのゲート端子G及び
ドレイン端子Sにバイアス電圧を印加するためのゲート
バイアス端子及びドレインバイアス端子、191iキヤ
パシタ(6)全構成する高誘電率の誘電体層、(lOl
にソース電極Sを裏面の接地面と導通するためのスルー
ホールである。
FIG. 3 is a chip pattern diagram of a conventional GmAa MMIC, in which a GaAsFET ft microwave amplification circuit is constructed. In the figure, (1)
T! A G5As field effect transistor (hereinafter referred to as GaAs FET) consisting of a GmA-substrate, a 121i gate terminal G, a drain terminal, and a source terminal S, +31 and (
4) Input matching circuit and output matching circuit consisting of a haopen stub, +51 [inductor, 181i capacitor, (
7) and (8) are a gate bias terminal and a drain bias terminal for applying a bias voltage to the gate terminal G and drain terminal S of the GaAs FET, a 191i capacitor (6) a dielectric layer with a high permittivity that constitutes the entire structure, ( lOl
This is a through hole for connecting the source electrode S to the ground plane on the back surface.

第3図に示されたGaAa MMICチップHGaAa
基板(1)上に作られたGaAs FET 121のゲ
ート端子及びドレイン端子に入力整合回路(3)及び出
力整合回路(4)が付いているので、信号入力にGaA
sPET 121の入出力端で反射損失がなく増幅され
る。
GaAa MMIC chip HGaAa shown in FIG.
Since the input matching circuit (3) and the output matching circuit (4) are attached to the gate terminal and drain terminal of the GaAs FET 121 made on the substrate (1), the GaAs FET 121 is connected to the signal input.
The signal is amplified at the input and output ends of the sPET 121 without reflection loss.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のGaAs MMICn以上のように構成されてい
念ので、GaAa PETのゲート端子G及びドレイン
端子りのバイアス電圧に各々独立のインダクタとキャパ
シタで構成された低域通過型フィルタのバイアス回路を
通して印加していたので、バイアス回路の形状が大きく
なり、必然的にG5As MMIGのチップ面積が大き
くなるという問題点かあつ念。
To be safe, the bias voltage at the gate terminal G and drain terminal of GaAa PET is applied through a bias circuit of a low-pass filter consisting of an independent inductor and capacitor. As a result, the shape of the bias circuit becomes larger, which inevitably increases the chip area of the G5As MMIG, which is a problem.

この発明は上記のような問題点を解消するためになされ
念もので、G5As MMICのバイアス回路を小型化
することによって、チップ面積の小さなGaAs MM
ICf得ることを目的とする。
This invention was made to solve the above problems, and by downsizing the bias circuit of G5As MMIC, GaAs MM with a small chip area can be realized.
The purpose is to obtain ICf.

〔課題を解決するたぬの手段〕[Tanu's means of solving problems]

この発明のGaAs MMIC用バイアス回路は誘電率
の高い誘電体層の上部に直接インダクタのパターンを形
成して低域通過型フィルタを構成したものである。
The bias circuit for a GaAs MMIC according to the present invention has an inductor pattern formed directly on top of a dielectric layer having a high dielectric constant to constitute a low-pass filter.

〔作用〕[Effect]

この発明のGaAm MMIC用バイアス回路は誘電体
層上に形成されているインダクタに寄生するキャパシタ
ンス全有効に用いて低域通過型フィルタが作られている
In the bias circuit for GaAm MMIC of the present invention, a low-pass filter is fabricated by fully utilizing the parasitic capacitance of an inductor formed on a dielectric layer.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図はこの発明のバイアス回路を用いたGaAa MMI
Cのチップパターン図を示す。図において、前記従来の
ものと同一符号に同一部分を示す。
An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a GaAa MMI using the bias circuit of this invention.
A chip pattern diagram of C is shown. In the figures, the same parts are indicated by the same reference numerals as in the conventional system.

図中、(Illi大きな寄生容ilヲ含んだインダクタ
で構成し念この発明のバイアス回路、(1凶にインダク
タに寄生容量を含ませる念めのGaAa基板上の接地金
属である。
In the figure, the bias circuit of the present invention is constructed with an inductor that contains a large parasitic capacitance, and the ground metal on the GaAA substrate is shown to make sure that the inductor contains a parasitic capacitance.

第2図はこの発明のバイアス回路(11)の断面図で、
第1図の■−■線における断面図を示す。
FIG. 2 is a cross-sectional view of the bias circuit (11) of the present invention.
A sectional view taken along the line ■-■ in FIG. 1 is shown.

第1図及び第2図で示すこの発明のバイアス回路におい
て[GaAv基板(1)の裏面接地金属αりとスルホー
ルα0)で導通しft GaA@FET基板上の接地金
属(+2)の上に高誘電率の薄い誘電体層(9)を形成
し、この誘電体層(9)上面にインダクタ(11)がパ
ターン化されている。
In the bias circuit of the present invention shown in FIGS. 1 and 2, conduction occurs between the back surface ground metal α of the GaAv substrate (1) and the through hole α0). A dielectric layer (9) with a thin dielectric constant is formed, and an inductor (11) is patterned on the upper surface of this dielectric layer (9).

この場合、インダクタ(11)の電極とGaAa FE
T基板上の接地金属0力の間に並列のキャパシタンスC
が生じる。従って、誘電体層(9)上にインダクタ(1
1)の電極パターンを形成し之この発明のバイアス回路
は、直列のインダクタンスと並列のキャパシタンスを有
することになり、低域通過型フィルタを構成している。
In this case, the electrode of the inductor (11) and the GaAa FE
Capacitance C in parallel between ground metal 0 force on T board
occurs. Therefore, the inductor (1) is placed on the dielectric layer (9).
The bias circuit of the present invention in which the electrode pattern 1) is formed has a series inductance and a parallel capacitance, and constitutes a low-pass filter.

よって、従来の各々独立インダクタとキャパシタで構成
し之バイアス回路と同様、この発明のバイアス回路にバ
イアス回路としての作用(直流電圧であるバイアス電圧
を通過させ、マイクロ波信号電力を阻止させる)を果す
Therefore, similar to the conventional bias circuit composed of independent inductors and capacitors, the bias circuit of the present invention functions as a bias circuit (passing the bias voltage, which is a DC voltage, and blocking the microwave signal power). .

念だし、この発明のバイアス回路はインダクタを高誘電
率の誘電体層(9)上に形成し、インダクタの寄生容量
を利用して低域通過型フィルタを構成しているので、個
別のキャパシタのある従来のバイアス回路と比較して、 ω GaAs MMICのチップ面積を大幅に小さくす
ることができる。
As a reminder, in the bias circuit of this invention, the inductor is formed on a dielectric layer (9) with a high dielectric constant, and a low-pass filter is constructed using the parasitic capacitance of the inductor. Compared to some conventional bias circuits, the chip area of ω GaAs MMICs can be significantly reduced.

■ バイアス回路の作図が容易になる。■ It becomes easier to draw the bias circuit.

という利点がある。There is an advantage.

なお、上記実施例でT’S GaAa MMIC(D場
合にりい2て説明したが、 GaA・以外の半導体を用
いたMMt c 。
In addition, in the above embodiment, T'S GaAa MMIC (D case) was explained, but MMt c using a semiconductor other than GaA.

例えばSI MMICでも同様の効果が得られることに
言うまでもない。
Needless to say, similar effects can be obtained with SIM MMIC, for example.

〔発明の効果〕〔Effect of the invention〕

以上のようKこの発明によれば、誘電体層上にインダク
タパターンを形成し、このインダクタンスと寄生のキャ
パシタンスによる低域通過フィルタでバイアス回路を構
成したので、マイクロ波集積回路のチップ面積を縮小す
ることができるという効果がある。
As described above, according to this invention, an inductor pattern is formed on a dielectric layer, and a bias circuit is configured with a low-pass filter using this inductance and parasitic capacitance, so that the chip area of a microwave integrated circuit can be reduced. It has the effect of being able to

【図面の簡単な説明】 第1図はこの発明の一実施例によるGaAa M?vi
ICのチップパターン図、第2図は第1図の■−■線に
おけるバイアス回路の断面図、第3図は従来のGmAs
 MMICのチ゛ンプパターン図である。 図において、Ill T’S GmAm基板、1211
’CGsAa FET 。 (3)は入力整合回路、t41d出力整出力路、t51
1!インダクタ、181Hキヤパシタ、(71[ゲート
バイアス端子、+8)uドレインバイアス端子、(91
1!誘電体層、(101はスルーホール、(■)にバイ
アス回路、(I21にG自A−基板上の接地金属、(1
3は裏面接地金属である。 なお、図中、同一符号に同一 またに相当部分を示す。
[Brief Description of the Drawings] FIG. 1 shows a GaAa M? according to an embodiment of the present invention. vi
IC chip pattern diagram, Figure 2 is a cross-sectional view of the bias circuit taken along the line ■-■ in Figure 1, Figure 3 is the conventional GmAs
It is a chip pattern diagram of MMIC. In the figure, Ill T'S GmAm substrate, 1211
'CGsAa FET. (3) is an input matching circuit, t41d output conditioning output path, t51
1! Inductor, 181H capacitor, (71 [gate bias terminal, +8) u drain bias terminal, (91
1! Dielectric layer, (101 is a through hole, (■) is a bias circuit, (I21 is a ground metal on the G self A- board, (1
3 is the back ground metal. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims]  半導体基板上の誘電体層にインダクタのパターンを形
成し、そのインダクタンスと寄生のキャパシタンスによ
り低域通過型フィルタを構成したことを特徴とするマイ
クロ波集積回路用バイアス回路。
A bias circuit for a microwave integrated circuit, characterized in that an inductor pattern is formed on a dielectric layer on a semiconductor substrate, and a low-pass filter is configured by the inductance and parasitic capacitance.
JP25972988A 1988-10-14 1988-10-14 Bias circuit for microwave integrated circuit Pending JPH02105701A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25972988A JPH02105701A (en) 1988-10-14 1988-10-14 Bias circuit for microwave integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25972988A JPH02105701A (en) 1988-10-14 1988-10-14 Bias circuit for microwave integrated circuit

Publications (1)

Publication Number Publication Date
JPH02105701A true JPH02105701A (en) 1990-04-18

Family

ID=17338132

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25972988A Pending JPH02105701A (en) 1988-10-14 1988-10-14 Bias circuit for microwave integrated circuit

Country Status (1)

Country Link
JP (1) JPH02105701A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999063656A1 (en) * 1998-06-04 1999-12-09 Analog Devices, Inc. Low noise amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999063656A1 (en) * 1998-06-04 1999-12-09 Analog Devices, Inc. Low noise amplifier

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