JPH02288409A - Resistance feedback type amplifier - Google Patents

Resistance feedback type amplifier

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Publication number
JPH02288409A
JPH02288409A JP1109722A JP10972289A JPH02288409A JP H02288409 A JPH02288409 A JP H02288409A JP 1109722 A JP1109722 A JP 1109722A JP 10972289 A JP10972289 A JP 10972289A JP H02288409 A JPH02288409 A JP H02288409A
Authority
JP
Japan
Prior art keywords
electrode
divided
feedback
electrodes
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1109722A
Other languages
Japanese (ja)
Other versions
JPH07118619B2 (en
Inventor
Osamu Ishihara
理 石原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1109722A priority Critical patent/JPH07118619B2/en
Publication of JPH02288409A publication Critical patent/JPH02288409A/en
Publication of JPH07118619B2 publication Critical patent/JPH07118619B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)
  • Microwave Amplifiers (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To make unnecessary the need of detour of a feedback circuit for evading a source electrode to miniaturize the amplifier by dividing a drain electrode placed between gate electrodes divided into two, and placing a feedback resistance between its divided drain electrodes. CONSTITUTION:A drain electrode placed between divided gate electrodes G1, G2 is divided into D1 and D2, and between these divided drain electrodes, a feedback resistance 4 is placed. Also, ohmic electrodes 5, 6 are formed across this resistance 4, one electrode 5 is connected to a gate electrode leading-out conductor 8 through an air bridge 7, and the other electrode 6 is connected to a DC obstructing MIM(Metal-Insulator-Metal) capacitor 10 through an air bridge 9. This MIM capacitor 10 is formed on a drain electrode leading-out conductor 3. In such a way, detour of a feedback circuit for evading a source electrode and its leading-out part is made unnecessary and this amplifier can be miniaturized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、主としてマイクロ波帯で使われる集積回路
であるMMIC(モノリシックマイクロ波集積回路)の
改良に関するものである。更に。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvement of MMIC (monolithic microwave integrated circuit), which is an integrated circuit mainly used in the microwave band. Furthermore.

詳しく言えば、抵抗帰還型増幅器において、抵抗で構成
される帰還回路の改良に関するものである。
Specifically, the present invention relates to an improvement of a feedback circuit composed of resistors in a resistive feedback amplifier.

(従来の技術) MMICはマイクロ波帯で使われるモノリシックICの
総称てあって1通常、GaAs基板上にGaAsFET
 (GaAs電界効果トランジスタ)やHEMT (旧
gh Electron #Iobility Tra
n−sistor)等の高周波トランジスタの能動素子
を抵抗やコンデンサ等の受動素子と共に集積化して作ら
れたものである。MMICには、低雑音増幅器、高出力
増幅器、スイッチ、移相器等様々な種類のものがあるか
、マイクロ波増幅器への応用か多い。
(Prior art) MMIC is a general term for monolithic ICs used in the microwave band.1 Usually, a GaAs FET is mounted on a GaAs substrate.
(GaAs field effect transistor) and HEMT (formerly GH Electron #Iability Tra
It is made by integrating active elements such as high-frequency transistors such as n-sisters with passive elements such as resistors and capacitors. There are various types of MMICs, such as low-noise amplifiers, high-output amplifiers, switches, and phase shifters, and there are many applications for microwave amplifiers.

第3図はMMICの1例として、広帯域増幅器の等価回
路を図示したものである。図中、TはGaAsFETま
たはHEMT等のトランジスタ、G、D、Sはトランジ
スタTのゲート電極。
FIG. 3 shows an equivalent circuit of a wideband amplifier as an example of an MMIC. In the figure, T is a transistor such as a GaAsFET or HEMT, and G, D, and S are the gate electrodes of the transistor T.

ドレイン電極、ソース電極を示す。C1〜C4はコンデ
ンサ、 L+〜L7はインダクタ、Rは抵抗を示す。
A drain electrode and a source electrode are shown. C1 to C4 are capacitors, L+ to L7 are inductors, and R is a resistance.

この回路の特徴は、第3図から分るように、トランジス
タTのドレイン電極D(出力端子)とゲート電極G(入
力端子)とを接続するC3、Ls、 Rの直列回路によ
って、帰還がかけられていることでである。この帰還を
かけることにより広帯域な増幅特性を実現することが出
来る。第4図は第3図に示す各回路定数の最適化を図り
シミュレーションにより求めた利得の周波数特性である
。この図から分るように、約2GIIzから18Gll
zに至る広帯域で平坦な利得か得られる。
As can be seen from Figure 3, the feature of this circuit is that feedback is applied by the series circuit of C3, Ls, and R that connects the drain electrode D (output terminal) and gate electrode G (input terminal) of the transistor T. This is due to the fact that By applying this feedback, wideband amplification characteristics can be realized. FIG. 4 shows the frequency characteristics of the gain obtained by simulation by optimizing each circuit constant shown in FIG. As you can see from this figure, from about 2GIIz to 18Gll
A flat gain can be obtained over a wide band up to z.

第5図は、第3図の等価回路のトランジスタ1部分と帰
還回路C3、L5、Rの部分をMM I Cのパターン
図として示したちのである。この図ではトランジスタT
のゲート電極Gは2本に分岐した電極部分68、G2を
有するものとして示されている。
FIG. 5 shows the transistor 1 portion and the feedback circuits C3, L5, and R portions of the equivalent circuit of FIG. 3 as a pattern diagram of MMIC. In this diagram, transistor T
The gate electrode G is shown as having two branched electrode portions 68, G2.

それぞれのゲート電極部分G1、G2は例えば、ゲー)
JjO,25ILm、単位ゲート幅50pm(トランジ
スタとしての全ゲート幅looJLm )である。この
場合、ドレイン電極りは1個でよいか、ソース電極は第
5図に示すように2個、すなわちsl、 s2が必要と
なる。それぞれのソース電極S8、S2は第3図に示す
ように、接地されていなければならない。
The respective gate electrode portions G1 and G2 are, for example, gate electrodes)
JjO, 25ILm, and a unit gate width of 50 pm (total gate width as a transistor looJLm). In this case, only one drain electrode is required, or two source electrodes, sl and s2, are required as shown in FIG. Each source electrode S8, S2 must be grounded as shown in FIG.

MMICではGllz以上の極めて高い周波数での動作
が要求されるので、接地については出来るだけ接地イン
ダクタンスか小さくなるように工夫がなされている。M
MICの接地電極は通常基板の裏面に形成されている。
Since MMICs are required to operate at an extremely high frequency of Gllz or higher, efforts are being made to minimize grounding inductance as much as possible. M
The ground electrode of the MIC is usually formed on the back surface of the substrate.

第6図はソース電極の接地法の1例を示したものてあり
、第5図の線B−B′に沿った断面を示している。この
図て、(1)はGaAs基板、(2)はソース電極S、
の引出し部、(20)は接地電極である。(30)は基
板(1)に開けられた穴であり、バイアホールと呼ばれ
る。この図から分るようにソース電極S0、S2は引出
し部(2)の下に設けられたバイアホール(30)を通
じて直接基板裏面の接地電極(20)に接続され、結果
として最小のソースインダクタンスを実現てきる。
FIG. 6 shows an example of a method of grounding the source electrode, and shows a cross section taken along line BB' in FIG. In this figure, (1) is a GaAs substrate, (2) is a source electrode S,
The lead-out portion (20) is a ground electrode. (30) is a hole made in the substrate (1) and is called a via hole. As can be seen from this figure, the source electrodes S0 and S2 are directly connected to the ground electrode (20) on the back side of the substrate through the via hole (30) provided under the lead-out part (2), resulting in the minimum source inductance. It will come true.

基板(1)の厚さはlOO〜200JLm程度か普通で
あり、バイアホール(30)の直径は基板(1)の厚さ
以上の寸法が必要である。そのため、引出し部(2)の
パターンサイズとしては、  2007zm角乃至30
0pm角程度か必要である。帰還回路部は第5図に示さ
れるように、コンデンサC3と抵抗凡の直列回路で構成
され、ソース電極(S2)及びその引出し部(2)を回
避するようにドレイン電極りからゲート電極Gに接続さ
れる。
The thickness of the substrate (1) is usually about 100 to 200 JLm, and the diameter of the via hole (30) needs to be larger than the thickness of the substrate (1). Therefore, the pattern size of the drawer part (2) is 2007mm square to 30mm square.
Approximately 0 pm square is required. As shown in FIG. 5, the feedback circuit section is composed of a series circuit of a capacitor C3 and a resistor, and is connected from the drain electrode to the gate electrode G so as to avoid the source electrode (S2) and its lead-out section (2). Connected.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述のようにして帰還回路部を設ける場合において問題
になることは、ソース電極を接地するためのバイアホー
ル部が比較的大きな面積を占めていることである。すな
わち、ソース電極及びその引出し部を回避する帰還回路
の迂回距離か長くなることである。第3図のインダクタ
L5は帰還回路の迂回に必要な線路の等何重なインダク
タンスを表わしているが、その迂回距離が長くなるとイ
ンダクタL5のインダクタンスが大きくなるので、MM
ICの性能を高くすることができなくなる。つまり、シ
ミュレーションで良好な性能か得られてもパターン図上
て実現不可能な場合か生ずる。また、帰還回路の迂1回
距離が長くなるとその帰還回路が占有する面積が大きく
なるという問題点が生ずる。
A problem in providing the feedback circuit section as described above is that the via hole section for grounding the source electrode occupies a relatively large area. That is, the detour distance of the feedback circuit that avoids the source electrode and its lead portion becomes longer. Inductor L5 in Fig. 3 represents the inductance of the same number of lines necessary for detouring the feedback circuit, but as the detour distance increases, the inductance of inductor L5 increases, so MM
It becomes impossible to improve the performance of the IC. In other words, even if good performance is obtained through simulation, it may not be possible to realize it based on the pattern diagram. Further, as the detour distance of the feedback circuit increases, a problem arises in that the area occupied by the feedback circuit increases.

この発明は上述の問題点を解決するためになされたもの
であって、帰還回路の迂回を不要とする抵抗帰還型増幅
器を提供することを目的とする。
The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a resistive feedback amplifier that does not require a detour of the feedback circuit.

鼻 (W#題を解決するための手段) この発明に係る抵抗帰還型増幅器は、少なくとも2つに
分割されたゲート電極間に配置されたドレイン電極を分
割してその分割したドレイン電極間に帰還抵抗を配置す
るようにしだものである。
(Means for Solving Problem W#) A resistive feedback amplifier according to the present invention divides a drain electrode arranged between at least two divided gate electrodes, and divides a drain electrode between the divided drain electrodes. It's like placing a resistor.

(作 用) この発明における抵抗帰還型増幅器は、分割されたゲー
ト電極間に配置されたドレイン電極を分割してその分割
したドレイン電極間に帰還抵抗を配置してその帰還抵抗
によりドレイン電極とゲート電極とを接続するので、ソ
ース電極を回避するための帰還回路の迂回を不要にする
(Function) The resistive feedback amplifier according to the present invention divides the drain electrode placed between the divided gate electrodes, places a feedback resistor between the divided drain electrodes, and uses the feedback resistor to connect the drain electrode to the gate electrode. Since it is connected to the electrode, there is no need to detour the feedback circuit to avoid the source electrode.

(実 施 例) 第1図はこの発明の一実施例を示すものである。この図
において、(3)はドレイン電極り、、 D2の引出し
導体を示す。この図から分るように、第5図に示す従来
のトランジスタとの構造上の相違はドレイン電極なり、
とD2に2分割していることである。この分割したドレ
イン電極の間に帰還抵抗(4)が配置されている。この
例ては、抵抗(4)は半導体層で形成されている。また
、この抵抗(4)の両端にはオーム性電極(5) 、 
(5)か形成され、一方の電極(5)はエアブリッジ(
7)を介してゲート電極引出し導体(8)に接続され、
また他方の電極(6)はエアブリッジ(9)を介して直
流阻止用MI M (Metal−Insulator
−Metal )コンデンサ(lO)に接続されている
。このMIMコンデンサ(lO)はドレイン電極引出し
導体(3)上に形成されている。第2図は第1図の線A
−A ”に沿った断面を示すものである。この図から分
かるように、M!Mコンデンサ(!0)は金属膜(3)
−誘電体膜(101)−金属膜(102)の3層構造の
モ行平板型コンデンサであり、この実施例ては、ドレイ
ン電極引出し導体(3)かMIMコンデンサ(10)の
下地電極を兼ねている。MIM:7ンデンサ(10)の
上地電極、すなわち金属膜(102)はエアブリッジ(
9)に接続されている。
(Embodiment) FIG. 1 shows an embodiment of this invention. In this figure, (3) indicates the drain electrode and the lead conductor of D2. As can be seen from this figure, the structural difference from the conventional transistor shown in Fig. 5 is the drain electrode.
and D2. A feedback resistor (4) is placed between the divided drain electrodes. In this example, the resistor (4) is formed of a semiconductor layer. In addition, ohmic electrodes (5) are connected to both ends of this resistor (4).
(5) is formed, and one electrode (5) is formed with an air bridge (
7) is connected to the gate electrode lead conductor (8),
The other electrode (6) is connected to a DC blocking MI M (Metal-Insulator) via an air bridge (9).
-Metal) connected to the capacitor (lO). This MIM capacitor (lO) is formed on the drain electrode lead conductor (3). Figure 2 is line A in Figure 1.
-A”. As can be seen from this figure, the M!M capacitor (!0) has a metal film (3).
This is a flat plate capacitor with a three-layer structure of - dielectric film (101) - metal film (102), and in this embodiment, it also serves as the base electrode of the drain electrode lead-out conductor (3) or the MIM capacitor (10). ing. The upper electrode of the MIM:7 capacitor (10), that is, the metal film (102) is connected to the air bridge (
9).

上述の実施例では、帰還抵抗(4)として半導体層を用
いたが、金属抵抗であってもよい、また、帰還抵抗(4
)とゲート電極引出し導体(8)及びMIMコンデンサ
(lO)との接続にはエアブリッジ(7) 、 (9)
を用いたが、通常の配線でもよい。また、MIMコンデ
ンサ(10)はドレイン電極引出し導体(3)トに形成
されているか、基板(1)に形成してもよい。更に、M
IMコンデンサ(lO)はゲート電極引出し導体(8)
上あるいはゲート電極側の基板(1)上に配置してもよ
いことは言うまでもない。更にまた、トランジスタは2
本に分岐したゲート電極部分G、、G2を有するものを
例に取っているか、この発明は多数のゲート准極を有す
るトランジスタに対しても容易に実施可能である。むし
ろ、多数のゲート電極を有するトランジスタの方かこの
発明の効果はより顕著なものとなる。すなわち、高出力
トランジスタは通常、数10本のゲート電極を有し、ト
ランジスタ寸法は大きくなるのて、第5図に示すような
従来の方法ては帰還回路のインダクタンスが大きくなり
その帰還回路を構成することは不可滝になるか、この発
明では容易に可能である。
In the above embodiment, a semiconductor layer was used as the feedback resistor (4), but a metal resistor may also be used.
) and the gate electrode lead conductor (8) and MIM capacitor (lO) are connected by air bridges (7) and (9).
was used, but normal wiring may also be used. Further, the MIM capacitor (10) may be formed on the drain electrode lead-out conductor (3) or may be formed on the substrate (1). Furthermore, M
The IM capacitor (lO) is the gate electrode lead conductor (8)
Needless to say, it may be placed on the substrate (1) on the gate electrode side. Furthermore, the transistor is 2
Although the present invention is taken as an example of a transistor having bifurcated gate electrode portions G, . Rather, the effects of the present invention are more pronounced in transistors having a large number of gate electrodes. That is, a high-output transistor usually has several tens of gate electrodes, and as the transistor size increases, the inductance of the feedback circuit increases in the conventional method shown in Figure 5, making it difficult to configure the feedback circuit. Although it would be impossible to do so, it is easily possible with this invention.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、帰還回路をコンパク
トに形成することかできるので、パターンレイアウトが
極めて容易になり、増幅器の高性能化及び小型化が可使
となる。
As described above, according to the present invention, the feedback circuit can be formed compactly, so the pattern layout becomes extremely easy, and the amplifier can be made high-performance and compact.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示す図、第2図は第1図
の一部断面を示す図、第3図はモノリシックマイクロ波
集積回路の1例を示す図、第4図は第3図の回路の利得
の周波数特性を示す図、第5図は第3図の主要部のパタ
ーンを示す図、第6図は第5図の一部断面を示す図であ
る。 図中、(3)はドレイン電極引出し導体、(4)は帰還
抵抗、(8)はゲート電極引出し導体、 (10)は直
流阻止用コンデンサ、(61)、(G2)はゲート電極
、(DI)、(D2)はドレイン電極、である。 なお、各図中同一符号は同−又は相当部分を示す。 第1 図 8コ)r−1tキシロ18ニレm O:MIM  コン干−ン寸 ol、oz:t’しくンt41M 第21!1 代  理  人   大  岩  増  雄01:斡を
4膿 102:金All 第3 図 第4 図 固;を敷(Gl−1z ) 第5 図
FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a partial cross-sectional view of FIG. 1, FIG. 3 is a diagram showing an example of a monolithic microwave integrated circuit, and FIG. 3, FIG. 5 is a diagram showing the pattern of the main part of FIG. 3, and FIG. 6 is a diagram showing a partial cross section of FIG. 5. In the figure, (3) is the drain electrode lead conductor, (4) is the feedback resistor, (8) is the gate electrode lead conductor, (10) is the DC blocking capacitor, (61) and (G2) are the gate electrode, (DI ), (D2) is a drain electrode. Note that the same reference numerals in each figure indicate the same or corresponding parts. 1st Figure 8) r-1t xylo 18 elm O:MIM con dry size ol, oz:t'shikun t41M 21! All Fig. 3 Fig. 4 Lay down (Gl-1z) Fig. 5

Claims (1)

【特許請求の範囲】[Claims] (1)電界効果トランジスタのドレイン電極からゲート
電極に抵抗で帰還をかける形式の抵抗帰還型増幅器であ
って、少なくとも2つに分割されたゲート電極間に配置
されたドレイン電極が分割されていて、その分割された
ドレイン電極間に帰還抵抗が配置されている抵抗帰還型
増幅器。
(1) A resistive feedback amplifier in which feedback is applied from the drain electrode to the gate electrode of a field effect transistor by a resistor, in which the drain electrode arranged between at least two divided gate electrodes is divided, A resistive feedback amplifier in which a feedback resistor is placed between the divided drain electrodes.
JP1109722A 1989-04-27 1989-04-27 Resistance feedback amplifier Expired - Lifetime JPH07118619B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1109722A JPH07118619B2 (en) 1989-04-27 1989-04-27 Resistance feedback amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1109722A JPH07118619B2 (en) 1989-04-27 1989-04-27 Resistance feedback amplifier

Publications (2)

Publication Number Publication Date
JPH02288409A true JPH02288409A (en) 1990-11-28
JPH07118619B2 JPH07118619B2 (en) 1995-12-18

Family

ID=14517567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1109722A Expired - Lifetime JPH07118619B2 (en) 1989-04-27 1989-04-27 Resistance feedback amplifier

Country Status (1)

Country Link
JP (1) JPH07118619B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008066059A1 (en) 2006-11-30 2008-06-05 Kabushiki Kaisha Toshiba Semiconductor device and semiconductor device manufacturing method
EP2053660A1 (en) 2007-10-26 2009-04-29 Kabushiki Kaisha Toshiba Semiconductor device
EP2056351A2 (en) 2007-10-31 2009-05-06 Kabushiki Kaisha Toshiba Semiconductor device
EP2083442A1 (en) 2008-01-24 2009-07-29 Kabushiki Kaisha Toshiba Semiconductor device and fabrication method of the semiconductor device
JP2009239816A (en) * 2008-03-28 2009-10-15 Icom Inc Amplifier
US8278685B2 (en) 2007-04-02 2012-10-02 Kabushiki Kaisha Toshiba Semiconductor device used with high frequency band

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6263477A (en) * 1985-09-14 1987-03-20 Sharp Corp Field effect transistor
JPS6377165A (en) * 1986-09-19 1988-04-07 Mitsubishi Electric Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6263477A (en) * 1985-09-14 1987-03-20 Sharp Corp Field effect transistor
JPS6377165A (en) * 1986-09-19 1988-04-07 Mitsubishi Electric Corp Semiconductor device

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008066059A1 (en) 2006-11-30 2008-06-05 Kabushiki Kaisha Toshiba Semiconductor device and semiconductor device manufacturing method
US7749901B2 (en) 2006-11-30 2010-07-06 Kabushiki Kaisha Toshiba Method for forming a tapered via of a semiconductor device
US8278685B2 (en) 2007-04-02 2012-10-02 Kabushiki Kaisha Toshiba Semiconductor device used with high frequency band
EP2053660A1 (en) 2007-10-26 2009-04-29 Kabushiki Kaisha Toshiba Semiconductor device
US7851832B2 (en) 2007-10-26 2010-12-14 Kabushiki Kaisha Toshiba Semiconductor device
EP2447998A1 (en) 2007-10-26 2012-05-02 Kabushiki Kaisha Toshiba Semiconductor device
EP2056351A2 (en) 2007-10-31 2009-05-06 Kabushiki Kaisha Toshiba Semiconductor device
US8546852B2 (en) 2007-10-31 2013-10-01 Kabushiki Kaisha Toshiba Semiconductor device
EP2083442A1 (en) 2008-01-24 2009-07-29 Kabushiki Kaisha Toshiba Semiconductor device and fabrication method of the semiconductor device
US8026595B2 (en) 2008-01-24 2011-09-27 Kabushiki Kaisha Toshiba Semiconductor device having hermitically sealed active area and electrodes
US8476118B2 (en) 2008-01-24 2013-07-02 Kabushiki Kaisha Toshiba Semiconductor device and fabrication mehtod of the semiconductor device
JP2009239816A (en) * 2008-03-28 2009-10-15 Icom Inc Amplifier

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