JP2000068762A - Field effect transistor and its active circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the active circuits of an amplifier, an oscillator, etc., having the satisfactory input/output impedance matching by previously embedding the phase returning capacitors in a gate or drain lead wire, a bus, a bar, etc., and using these capacitors as active elements. SOLUTION: In regard to the plane layout structure of an FET(field effect transistor) part of an FET, the phase returning capacitors 11 and 11' are embedded in the lead wires 9 and 10 of one or both of a gate and a drain. Meanwhile, an input RF signal port 6, an output RF signal port 7 and the gate and drain DC bias ports 8 and 8' are prepared at the FET part. When the capacitors 11 and 11' are formed on an integrated circuit, an MIM(metal-insulator-metal) structure or an interdigital structure is applied to secure the small distribution constant property and the integrated constant characteristic. As a result, a trimming job is facilitated and a total size can be reduced for a matching circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microwave / millimeter-wave field effect transistor capable of easily achieving input / output impedance matching and an active circuit using the same.

[0002]

2. Description of the Related Art Field effect transistors (FETs)
In some cases, a transistor such as a ffect transistor is applied to form a high-output amplifier that operates in a millimeter wave, in particular, a W band. Since high output is intended, the FET has a multi-cell structure in most cases.

[0003] As a conventional example of a multi-cell structure FET, a description will be given of a portion of an input / output force lead line when input / output force matching is performed. Here, the part of the input (output) force lead line generally refers to the part of the gate lead line or gate bus bar for input, and the part of the drain lead line or drain bus bar for output. is there.

FIG. 9 is a plan view schematically showing a layout near a phase return capacitor in a conventional field effect transistor, and FIG. 10 is an input / output based on a conventional FET structure.
It is a figure of force impedance matching.

A point B in FIG. 9 represents a starting point of the input / output force matching when the input / output force matching circuit is connected. The input (output) impedance of an output stage FET having a large gate width Wg (not shown) may be an upper hemisphere (that is, an inductive impedance) above a 50Ω equal conductance circle 5 on the Smith chart. In this case, as shown in FIG. 10, the point B, which is the starting point of the matching by the matching circuit, comes to the portion marked with a mark in the admittance Smith chart. This tendency becomes stronger as the frequency becomes higher and as the gate width Wg becomes larger.

In an FET having such an inductive input (output) impedance, even if an attempt is made to match the input (output) impedance, the phase in the Smith chart is counterclockwise in a combination of a transmission line and a stub which is usually used. Since it cannot be returned to the surroundings in principle, good matching cannot be obtained.

Therefore, a capacitor (not shown) is connected to the outside of the FET shown in FIG. 9 and the phase is returned in advance to the point C in the conductance circle 5 such as 50Ω in FIG. A method is used in which matching can be achieved by means (that is, impedance conversion using a transmission line and a stub or a quarter wavelength line). Point C represents the input (output) impedance returned by the phase return capacitor, and points C to D represent the phase rotation (advance) by the transmission line.

In FIG. 10, the phase is advanced from the point C by a transmission line, the input (output) force impedance is brought to the point D of the equal conductance circle 5 of 50Ω, and then, it has a capacitive property at the operating frequency. The case where the input (output) impedance is matched to 50Ω by compensating the impedance by the open stub (that is, brought to the center point O in FIG. 10) is shown. That is, the impedance from the point D to the center point O represents the impedance compensation by the open stub.

[0009]

However, if a capacitor is provided outside the FET, the distance from the FET to the capacitor is large, so that it is necessary to return the phase including the phase shift of the wiring. This means that, in FIG. 10, the starting point of the matching is from the point B to the point B '(the starting point of the matching when the phase return capacitor is arranged outside the FET) in FIG. Therefore, as a capacitor for returning the phase to the point C, a very small capacitance value (eg, 0.1 pF or less)
Is required. It is generally difficult to accurately realize a capacitor with a small capacitance value.

In addition, although a capacitor having a high lumped constant with an MIM (metal-insulator-metal) structure actually has physical dimensions, it has not only a function of returning the phase but also a function of advancing the phase. (For example, at 76 GHz, even if the length is 15 μm, the phase rotation there is not negligible.) Further, since this distributed constant property becomes more conspicuous at higher frequencies, it is particularly high in the W band. At the operating frequency, high-precision designability could not be expected in a practical design for determining the physical shape of the capacitor.

The solution of the above problems has been a major problem in designing a millimeter-wave high-power amplifier.

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, an object of the present invention is to provide an FET which has relatively high feasibility and design accuracy without disposing a capacitor outside the FET. It is an object of the present invention to provide a basic technique for obtaining good input / output impedance matching of FETs when a millimeter-wave active circuit for W-band operation or the like is to be constructed by using the above.

[0013]

According to the present invention, in order to solve the above-mentioned problems of the prior art, in a planar layout structure of a multi-cell structure of FETs, a capacitor for returning a phase is previously formed in a lead line, a bus bar, or the like. Take a capacitor built-in structure.

The present invention also relates to a structure incorporating a capacitor, which is applied to an input (gate) side of an FET, applied to an output (drain) side, and applied to an input (gate) side. It is also applied to Further, it is an active circuit such as an amplifier or an oscillator using an FET having such a capacitor built-in structure as an active element.

By forming a capacitor for phase return in the planar layout structure of the FET, the capacitance value of this capacitor can be kept within a range of relatively high feasibility and design accuracy.

[0016]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view conceptually showing a layout of a lead line portion in a capacitor built-in field effect transistor FET of the present invention, and FIG. 2 is a view of input (output) force impedance matching based on the FET structure of the present invention. is there.

A feature of the structure of this embodiment is that, as shown in FIG. 1, a capacitor 3 is formed on a lead line 2 of a gate or a drain as a structure for achieving good input / output impedance matching of an FET (not shown). It is a point that is embedded. FE
In the structure of T, a central part such as a recess structure or a gate electrode structure may be a conventional structure. That is,
Conventionally, the phase return capacitor is disposed outside the planar layout of the FET.
This is a point formed in the portion of the gate lead line and the drain lead line inside the planar layout of T. In this case, the starting point of the input (output) force matching is point A in FIG.

The capacitance value to be made may be the phase return from the point B in FIG. 10 to the point A (matching start point) in FIG. 2.
This is because the value may be about F, so that the value does not need to be too small. Further, the transmission line from the point B to the point B 'in FIG. 9 is basically unnecessary, which leads to a reduction in the layout of the entire matching circuit. In addition, the unnecessary phase lead of the physical dimensions of the capacitor becomes a part of the distributed constant property originally possessed by the lead wire and the bus bar,
It can be reduced to almost negligible.

In FIG. 2, the phase is advanced from the point A by the transmission line, the input (output) force impedance is brought to the point D of the equal conductance circle 5 of 50Ω, and the open stub having the capacitive property is used. The input (output) impedance should be matched to 50Ω by compensating the impedance and brought to the center point O shown in the figure. That is, the impedance from the point D to the center point O represents the impedance compensation by the open stub.

If the phase is previously returned to a larger value by this capacitor, the input / output force of the FET can be matched with the transmission line and the open stub.

If a cross-sectional structure or a process flow in which the FET and various passive elements (such as wiring, capacitors, resistors, and inductors) are monolithically formed on the same substrate is adopted, integration in manufacturing the FET of the present embodiment is possible. The cross-sectional structure and process flow of the circuit may be the same as the conventional method. To realize the FET structure of this embodiment based on the conventional structure,
In the planar layout structure, a capacitor may be formed in a portion of a gate lead line or a drain lead line.

FIG. 3 is an equivalent circuit diagram of the FET when the FET structure of the present invention is applied to the input (gate) side, and FIG. 4 is an equivalent circuit diagram of the FET when the FET structure of the present invention is applied to the output (drain) side. FIG. 5 is an equivalent circuit diagram of an FET when the FET structure of the present invention is applied to both the input and output (gate / drain) sides.

In the present invention, FIG. 3 shows a structure in which a capacitor is formed, which is applied to the input (gate) side of an FET. Further, when the gate width is 600 μm, in most cases, both the input impedance and the output impedance of the FET enter the inductive region marked with a star in FIGS. FIG. 4 shows an example applied to only the output (drain) side. It is not usually used much, but may be required depending on the matching circuit employed. FIG. 5 shows a case where the present invention is applied to the input (gate) side and the output (drain) side.

Now, in the case where the structure of the capacitor for phase return is specifically formed on an integrated circuit,
A (metal-insulator-metal) structure or an interdigital structure is conceivable. However, in order to be able to cope with high frequencies such as millimeter waves, it is preferable to use a material having a distribution constant characteristic and a lumped constant characteristic as much as possible. , MIM structure is preferred.

In the layout in which the MIM structure is employed as a phase return capacitor, the FET and the external matching circuit are roughly divided into two types depending on whether they are connected by an upper electrode layer or a lower electrode layer of the MIM capacitor. The street is conceivable.

FIG. 6 shows that the FET and the external matching circuit are connected to the MIM.
FIG. 4 is a layout diagram in a case where connection is made with an upper electrode layer of a capacitor. Since the transmission line extending from the FET to the outside is formed only by a normal wiring layer (such as gold), the characteristic impedance of the transmission line of the matching circuit is well designed, and the open stub is located very close to the FET. There is a merit that can be connected to. In order to improve the breakdown voltage of the MIM capacitor, the capacitor upper electrode layer 16 and its external wiring layer 1
Although the air bridge structure 17 is applied to the connection portion with the air bridge 2, the air bridge portion usually requires only one portion. However, a relatively large number of openings 15 for electrical contact between the lower electrode layer 14 of the capacitor and the wiring layer 13 are required.

FIG. 7 is a layout diagram when the FET and the external matching circuit are connected by the lower electrode layer of the MIM capacitor. There is an advantage that the number of openings for electrical contact between the lower electrode layer 14 of the capacitor and the wiring layer 13 is relatively small. However, the FET and the external wiring layer 1
First, since the lower electrode layer 14 of the capacitor is first connected, the external wiring portion needs a window 15 for electrical contact between the lower electrode layer 14 and the wiring portion 12, and the external matching circuit Care must be taken in designing the characteristic impedance of the transmission line. In addition, open
It is difficult to arrange the stub very close to the FET. Also, MI
When the air bridge structure 17 is applied to the connection between the capacitor upper electrode layer 16 and the external wiring layer 12 in order to improve the breakdown voltage of the M capacitor, three air bridge portions are required as shown in FIG. If anything, it is considered that the wiring configuration of FIG. 6 is easier to apply as an integrated circuit.

On the other hand, FIG. 8 is a sectional structural view of the capacitor and the wiring portion shown in FIG. 6 or FIG. 7 in the case where the capacitor built FET of the present invention is actually formed on a GaAs substrate.

A capacitor and wiring layers 12 and 13 are formed on a GaAs crystal material 19 epitaxially grown on a semi-insulating GaAs substrate 18 wafer. Titanium / aluminum / titanium (Ti / Al / Ti) was used for the lower electrode layer 14 of the capacitor. Silicon nitride (SiNx) 2 for dielectric
3 was used. For the wiring layers 12 and 13 and the capacitor upper electrode layer 16, titanium / platinum / gold (Au / Pt / Ti)
A metal conductor layer made of gold (Au) was used for the upper layer 12 and the capacitor upper electrode layer 16. Titanium, platinum, gold (Au / Pt / Ti)
Where the layer 13 is removed, an air bridge structure 17 is formed. The recesses, gate electrodes, and the like, which are the central portions of the FET, are formed monolithically with the above-described capacitor and wiring structure processes.

Based on the above wiring configuration, a capacitor for phase return is formed in the planar layout structure of the FET,
The setting of the capacitance value of this capacitor was specifically performed. In a basic design, the capacitance value may be the phase return from point B to point C in FIG.

Further, an FET having a gate width of 600 μm is actually used.
Was used to design a high-output amplifier operating at 76 GHz. As a result, a capacitor for returning the phase was required on both the input side and the output side.
It was calculated that the pF level was appropriate, and it was found to be within a range of relatively high feasibility and design accuracy. On the other hand, when this amplifier is designed with a conventional structure, the capacitance value of the capacitor for phase return needs to be a very small value of 0.1 pF or less. It is generally difficult to accurately realize the capacitance value of the capacitor with the aim of such a small capacitance value.

An active circuit such as an amplifier or an oscillator using an FET having such a capacitor-built-in structure (the structure shown in FIG. 6 or FIG. 7) as an active element is conceivable. Not only does the design accuracy of the matching greatly improve, but it also leads to a reduction in the chip layout area.

Next, an embodiment in which the capacitor built-in field effect transistor (FET) of the present invention is actually applied to a microwave / millimeter wave integrated circuit will be described.

In the detailed design, the capacitance of the capacitor for returning the phase is previously set to a small value of 0.2 pF and the phase is returned to the larger value, so that the input and output of the FET can be controlled by the transmission line and the open stub. ) Designed to achieve force matching. Since the dielectric of the applied MIM capacitor was silicon nitride (SiNx) and its thickness was 1000 Å, in order to realize a capacitance value of 0.2 pF, the size of the upper electrode layer of the MIM capacitor was 9 μm × 32 μm. there were. These dimensions were just right for making capacitors in lead wires and bus bars.

When trimming the matching circuit when the amplifier is configured as a 76 GHz high power amplifier MMIC, the position of the open stub (that is, the length of the transmission line for phase rotation) and the length are basically corrected. Since there was no need to change the capacitance value of the capacitor,
Trimming was very easy. Furthermore, since the transmission line from point B to point B 'in FIG. 9 can be eliminated at all, the layout of the entire matching circuit can be reduced in size. In addition, the unnecessary phase lead of the physical dimensions of the capacitor became a part of the distribution constant property originally possessed by the lead wire and the bus bar, and could be almost negligibly reduced.

Now, a description will be given of a case where a high-output amplifier is designed using an FET as an active element in order to operate in the millimeter wave W-band at 76 GHz.

When the gate width of the FET is up to 200 μm, the input (output) force impedance is normally shown in FIGS.
Since it is not in the marked inductive area, it is not necessary to build a capacitor in the lead wire or bus bar, but the gate width is 3
When it becomes 00 μm, the input impedance first becomes
Therefore, it is necessary to build a capacitor in the gate lead line and the gate bus bar because the capacitor enters the inductive region marked with a star.

[0039]

As described above, according to the present invention, when an FET is used as an active element to construct a millimeter-wave active circuit such as a W-band operation, the input / output impedance matching of the FET is improved. Provide the basic technology to take. Further, when an amplifier is configured as an integrated circuit such as an MMIC, trimming of a matching circuit includes:
Basically, it is only necessary to modify the position and length of the open stub, and it is not necessary to change the capacitance value of the capacitor, so that trimming becomes very easy.

Therefore, the present invention greatly contributes to the development of microwave / millimeter wave monolithic ICs, and promotes advances in microwave / millimeter wave communication devices and sensing devices.

[Brief description of the drawings]

FIG. 1 is a plan view conceptually showing a layout of a lead line portion in a capacitor built-in field effect transistor FET of the present invention.

FIG. 2 is a diagram of input / output impedance matching based on the FET structure of the present invention.

FIG. 3 is an equivalent circuit diagram of an FET when the FET structure of the present invention is applied to the input (gate) side.

FIG. 4 is an equivalent circuit diagram of an FET when the FET structure of the present invention is applied to the output (drain) side.

FIG. 5 is an equivalent circuit diagram of an FET when the FET structure of the present invention is applied to both input and output (gate / drain) sides.

FIG. 6 is a plan view showing a specific layout of an FET lead line according to the present invention.

FIG. 7 is a plan view showing a specific layout of an FET lead line according to the present invention.

FIG. 8 is a sectional structural view of an MIM capacitor and a wiring portion based on an actual manufacturing process.

FIG. 9 is a plan view showing a layout near a phase return capacitor in a conventional field effect transistor.

FIG. 10 is a diagram of input / output impedance matching based on a conventional FET structure.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 RF signal line 2 Leader line 3 Capacitor part 4 DC bias line 5 Equiconductance circle of 50Ω 6 Input (gate) side RF signal port 7 Output (drain) side RF signal port 8 Gate DC bias port 8 'Drain DC bias port 9 Gate lead line 10 Drain lead line 11 Gate side phase return capacitor 11 'Drain side phase return capacitor 12 Upper conductor layer of wiring using gold (Au) 13 Titanium / Platinum / Au (Au / Pt / Ti) 14 Lower electrode layer of capacitor using Ti / Al / Ti 15 Window for electrical connection between capacitor lower electrode layer and lower conductor layer 16 Capacitor upper electrode pattern portion 17 Air bridge Structure (only 12 without 13) 17 'Hollow part by air bridge structure 18 Semi-insulating GaAs substrate layer 19 AlGaAs layer 20 InGaAs Layer 21 n-AlGaAs layer 22 Silicon oxide (SiO2) layer 23 Silicon nitride (SiNx) layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03F 3/68 F term (Reference) 5F048 AA01 AB10 AC10 BA01 BF02 BF07 BF11 BF15 BF16 5J067 AA01 CA75 CA92 FA16 HA09 HA24 HA29 KS11 MA09 QA02 QA03 QS04 TA02 5J069 AA01 CA75 CA92 FA16 HA09 HA24 HA29 MA09 QA02 QA03 TA02

Claims (6)

[Claims] In a planar layout structure of a field effect transistor, a gate lead line or a gate bus line is provided.
A monolithic field effect transistor having a structure in which a capacitor is built in a bar. 2. A monolithic field effect transistor having a planar layout structure of a field effect transistor, wherein a capacitor is formed in a drain lead line or a drain bus bar. 3. A planar layout structure of a field effect transistor, comprising: a gate lead line or a gate bus line.
A monolithic field-effect transistor having a structure in which a capacitor is formed in a bar and a structure in which a capacitor is also formed in a drain lead line or a drain bus bar. 4. In a planar layout structure of a field effect transistor, a gate lead line or a gate bus line is provided.
A monolithic active circuit, wherein a field effect transistor having a structure in which a capacitor is formed in a bar is used as an active element. 5. A monolithic active circuit comprising a planar layout structure of a field effect transistor, wherein a field effect transistor having a structure in which a capacitor is formed in a drain lead line or a drain bus bar is used as an active element. 6. A planar layout structure of a field effect transistor, comprising: a gate lead line or a gate bus line.
A field effect transistor is used as an active element, characterized in that it has a structure in which a capacitor is built in the bar, and has a structure in which a capacitor is also built in the lead wire or the drain bus bar. Monolithic active circuit.