JP3455413B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a transistor and a high frequency signal line connected to the transistor.

[0002]

2. Description of the Related Art In recent years, in the field of information communication, several GH
High-frequency regions of z or higher are being developed for consumer use one after another, and small, inexpensive high-performance high-frequency devices are required.
Particularly, for example, in a high-frequency device that transmits and receives radio waves of several tens GHz or more, since the wavelength is as short as several millimeters, problems such as resonance of the envelope and oscillation of the circuit can be prevented, and the high-frequency circuit can be easily designed. The miniaturization of parts has become important.

In order to reduce the size of the high-frequency circuit section, it is necessary to form as many necessary circuits as possible on one semiconductor substrate, that is, MMIC (Monolithic Microwave Integrated).
Circuit) is effective. In other words, the conventional single active element, a single functional circuit block that performs a predetermined circuit function, and a plurality of functional circuit blocks are integrated and formed in a single semiconductor substrate.

FIG. 13 shows a circuit configuration of a one-stage amplifier with a bias function as an example of an amplifier formed on a semiconductor substrate. To the source S, which is the ground electrode of the transistor 1, a capacitor 9 having a capacitance Cs is connected, and a resistor 10 having a DC bias function is connected. In FIG. 13, G is a gate, D is a drain, 1a is a high-frequency signal wiring functioning as a short stub, Vd is a drain voltage source, RFin is a gate input signal, and RFout is an output signal.

FIG. 14 shows a layout diagram near the transistor 1. In the high frequency line near the transistor 1, a high frequency signal wiring 5 and a high frequency ground 6 are provided.
A coplanar line consisting of is used. The high frequency ground 6 is connected to an adjacent high frequency ground 12 via a bridge 7 and a contact (interlayer connection portion) 8. The high frequency ground 12 is composed of a coplanar line, and constitutes the ground side electrode of the MIM capacitor 9. The source-side electrode 11 of the MIM capacitor 9 is connected to the source S of the transistor 1 via the contact 8.
Further, the resistor 10 has one end connected to the source side electrode 11 via a contact and the other end connected to the high frequency ground 12 via a contact, and thus is added in parallel to the MIM capacitor 9. In the conventional technique, the high frequency grounds 6 and 12 (ground side electrodes) function as both a high frequency ground and a direct current ground.

Since the source S of the transistor 1 is divided into two as shown in the enlarged plan view of FIG. 15, there are two MIM capacitors 9 and resistors 10 connected to the source S as shown in the layout diagram of FIG. Will be divided.

Next, a method of using each wiring layer on the semiconductor substrate will be described with reference to FIGS. 14 and 16. In each layer in the vicinity of the transistor 1, the first metal layer 14 is used as the source-side electrode 11 of the MIM capacitor 9, and the second metal layer 15 is used as the coplanar line signal line 5, high-frequency ground 6, ground-side electrode 12, and third layer. Can be used for the bridge 7 for connecting the high frequency grounds on both sides of the coplanar line.

[0008]

In such a high frequency circuit, the capacitor 9 and the resistor 10 which determines the DC potential of the source S as a part of the bias circuit require a large area. Further, in order to bring out the latent performance of the transistor, the impedance viewed from the source S of the resistor 10 divided into two must be the same impedance although it is difficult due to layout restrictions and manufacturing errors.

From such a demand, it is desired that the resistor 10 for adjusting the DC potential is not divided but connected to two sources S via wirings on different layers to be commonly used. However, in order to achieve this connection, a new wiring that crosses the high-frequency signal line 5 that is input to the gate G of the transistor 1 is required. In order to provide a new wiring layer on the high-density circuit layout, the bridge 7 for connecting the high frequency ground 6 and the high frequency ground (ground side electrode) 12 on both sides of the coplanar line already provided Method of providing wiring using the third metal layer 16 while making a detour so as not to hit, or the third metal layer 1
A method of newly providing a fourth metal layer on 6 is conceivable, but when the former method is adopted, the chip area increases,
Further, when the latter method is adopted, there is an adverse effect that the number of metal layers increases.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a semiconductor device which can achieve miniaturization and reduction of the number of wiring layers, and which can exhibit the potential of a transistor. To do.

[0011]

In order to solve the above-mentioned problems, the first aspect of the present invention is to provide a high-frequency signal line and a high-frequency ground formed on the same layer, a transistor in which a ground electrode is divided, and a ground of the transistor. A semiconductor device having a capacitor and a resistor connected to an electrode, wherein the DC potential of a high frequency ground is equal to the DC potential of a ground electrode.

A second aspect of the present invention is a semiconductor device including a high frequency signal line and a high frequency ground formed on the same layer, a transistor having a ground electrode divided, and a capacitor and a resistor connected to the ground electrode of the transistor. A high frequency ground adjacent to the transistor is directly connected to a ground electrode.

According to the first and second aspects of the present invention, the degree of freedom in circuit layout design is increased, and the chip area is reduced.
It is possible to reduce the number of wiring layers and to provide a semiconductor device in which the potential performance of a transistor can be sufficiently exhibited. Further, the first and second aspects of the present invention are characterized in that a bridge for connecting a plurality of high frequency grounds sandwiching the high frequency signal line is provided in an upper layer or a lower layer of the high frequency signal line and the high frequency ground.

Further, in the first and second aspects of the present invention, the high-frequency signal line and the high-frequency ground are provided with an electrode layer of the capacitor whose DC potential becomes a ground potential in an upper layer or a lower layer.

Furthermore, in the first and second aspects of the present invention, the transistor is a T-type transistor, and the high-frequency signal line and the high-frequency ground form a coplanar line,
The ground electrode has a source potential.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a layout diagram of a semiconductor device according to a first embodiment of the present invention. Further, the multilayer wiring layer will be described with reference to FIG.

In this embodiment, a semiconductor substrate having multilayer wiring is used as the MMIC, and the high frequency signal line 5 near the T-type transistor 1 having the source S, the drain D and the gate G, the MIM (metal-insulator). -metal)
Of the two electrodes of the capacitors 9a and 9b, the high-frequency ground and the high-frequency ground 11 to be the source-side electrode 11
a is the ground of the coplanar line. That is, the high frequency ground 11 in the present embodiment is connected to the source S of the transistor 1 and has a direct current source potential unlike the high frequency ground 12 of FIG. . The high frequency ground 11 serves as a high frequency ground in the operating frequency band of the transistor 1. Further, the electrode 11 is connected to the adjacent high frequency ground via the bridge 7 and the contact 8. The other electrode 12 of the capacitors 9a and 9b is a high frequency ground 1 which is also a ground in terms of direct current.
It is an electrode on the side of 1a and is connected to a high frequency ground 11a via a contact 8a. High frequency ground 11
a has a ground potential both in terms of direct current and high frequency. The resistor 10 has a high frequency ground 11 at one end.
And the other end is connected to the high frequency ground 11a through the contact 8b.

In the circuit configuration of this embodiment, as shown in FIG. 2, there is one resistor Rs. Further, in FIG. 2, since the two divided capacitors Cs have a parallel configuration, a single capacitor is shown in the circuit.

Each layer in the vicinity of the transistor 1 when the circuit is formed into an MMIC is used as follows. That is, the metal pattern formed of the second metal layer 15 is used for the signal line 5 for the coplanar line and the T-type transistor 1 of the electrodes of the capacitor 9.
Of the first metal layer 14 is used as the source side electrode connected to the source S, the high frequency ground 11 having a source potential in terms of direct current, and the high frequency ground 11a of the ground in terms of direct current. The metal pattern formed of the third metal layer 16 is used for the ground side electrode 12 facing the side electrode, and the source side electrode 11
It is used for the bridge 7 to connect the two.

By doing so, the DC potential of the high frequency ground 11 (source-side electrode) adjacent to the transistor 1 becomes equal to the source potential via the bridge 7 connected by the contact (interlayer connection portion) 8. Become. The layer of the resistor 11 can be composed of the first metal layer 14 and the second metal layer 15 of FIG. 15 or the layer disposed at a predetermined position between the second metal layer 15 and the third metal layer 16.

According to the present embodiment as described above, there is no occurrence of uneven impedance due to division of resistors, the capacitors 9a and 9b can have a large area, and the degree of freedom in layout design can be increased. Problems such as an increase in chip area and an increase in the number of metal layers can be prevented. Further, it is possible to prevent the inductance component of the high frequency ground to which the ground electrode of the transistor is connected from increasing.
Therefore, the potential performance of the transistor 1 can be sufficiently exhibited without deteriorating.

The internal structure of the circuit device has been described above. Next, the outer peripheral portion of the MMIC connected to the peripheral circuit will be described. The peripheral circuit is usually provided with a high frequency signal line, a bias line having a predetermined DC potential, and a high frequency ground / DC ground. So MM
It is desirable that a high-frequency signal line, a bias line, and a high-frequency ground / DC ground are provided in the peripheral portion of the IC in addition to the peripheral circuits. MMIC according to the present invention
In the case of, the high frequency ground 11 near the transistor 1
The (source-side electrode of the capacitor 9) has a source potential in terms of direct current. Therefore, the layout on the semiconductor substrate 13 needs to convert the DC potential of the high frequency ground 11 from the source potential to the ground potential between the electrode of the transistor 1 and the connection electrode with the peripheral portion. This conversion can be realized by using an MIM capacitor having sufficiently low impedance at the operating frequency for the high frequency ground of the coplanar line. For example, by setting the DC potential of one electrode of a low-impedance capacitor to the source potential and the DC potential of the other electrode to the ground potential, it behaves as a continuous high-frequency ground at the operating frequency, and in terms of direct current, before and after the capacitor. The source potential can be converted to the ground potential.

Next, the layout of the connection electrodes of the semiconductor device according to the first embodiment connected to the peripheral portion will be described. FIG. 3 shows a layout in the vicinity of an electrode for connecting a bonding wire as an example of this connection electrode. In the bonding wire connecting electrode 18 of FIG. 3 configured by the second metal layer 15 of FIG. 16, there is a possibility that the metal layers of the multi-layer will be short-circuited by the impact of the step of hitting the bonding wire.
Therefore, the MIM that converts the DC potential of the high frequency ground
Capacitor (first metal layer 14 or third metal layer 16
It is preferable that a position where a region sandwiched by the high frequency ground 11 a facing each other is provided is a region adjacent to the electrode 18.

FIG. 4 shows a layout in the vicinity of the bump connection electrode 19 as another example of the connection electrode. In the case of a semiconductor substrate having the bump connecting electrodes 19, the MIM capacitor (first metal layer 1
It is preferable to provide a region sandwiched by the high frequency ground 11a facing the fourth or third metal layer 16.

The material used for the semiconductor substrate is a Si substrate,
A semiconductor substrate such as a GaAs substrate or another substrate can be used, and the semiconductor substrate is provided with active elements, passive elements, wirings, electrodes and the like. As the active element, a bipolar transistor, a field effect transistor, etc. are formed,
The ground electrode of the present invention can be variously selected according to the circuit configuration. Further, as passive elements, resistors, capacitors, inductors, directional couplers, filters, impedance converters, antennas, etc. are formed. The wiring material is A
It is possible to use u, Al, Cu, other metals, or a conductive resin.

Next, the manufacturing method of the wiring connecting to the transistor 1, the signal wiring 5, the high frequency ground 11 and the like in the first embodiment will be described with reference to FIGS. 5 (a), 5 (b),
6 (a), 6 (b), 7 (a), and 7 (b)
Will be explained.

FIG. 5A is a HEM according to this embodiment.
A laminated structure substrate for forming T is shown, and a semi-insulating Ga is shown.
On the main surface of the semiconductor substrate 21 such as As, the buffer layer 22,
The channel layer 23, the spacer layer 24, the electron supply layer 25, the Schottky contact layer 26, and the ohmic contact layer 27 are sequentially crystal-grown by the MBE method or the like. The channel layer 23 is an undoped layer, and electrons are supplied from the electron supply layer 25 to form a two-dimensional electron gas. For electrical isolation between adjacent elements, after crystal growth, a portion other than the element formation region (not shown)
Are removed by etching to form an insulating material by embedding.

After element isolation is thus performed, SiO ₂ is deposited on the ohmic contact layer 27 by a CVD method or the like, and as shown in FIG. 5B, a pattern 28 is formed by a photolithography process and etching. After forming the pattern, A is formed in the contact hole surrounded by the pattern 28.
An ohmic electrode 29 made of a metal such as 1 is formed by a sputtering method or the like.

Then, a photoresist pattern having an opening in the intended gate region is formed. Then, using this photoresist pattern, the ohmic contact layer 27 in the gate region is etched to expose the Schottky contact layer 26. Then, after the gate electrode material is vapor-deposited, lift-off processing is performed to form a gate electrode 30 having a T-shaped cross section as shown in FIG.

Next, a photoresist (not shown) is coated on this element region, and this photoresist is patterned into a shape that surrounds a region that will be a transmission line or a lead-out wiring of each terminal. Then, a metal material is vapor-deposited on the element region where the photoresist pattern is formed, and the first metal layer 31 (14 in FIG. 16) as shown in FIG. 6B is formed by the lift-off method. Then, a SiN film 32 to be a passivation film is deposited on the entire surface by the CVD method as shown in FIG. 6B.

Further, as shown in FIG. 7A, on the surface of the SiN film 32, a first metal layer is formed on a partial region including the ohmic electrode 29 and the gate lead electrode (not shown). A contact hole 33 connecting to the second metal layer is opened. And contact hole 3
A resin 34 such as BCB is applied to the element region where the opening 3 is formed, and then cured.

Next, a photoresist 35 is applied on the element region, and as shown in FIG. 7A, the ohmic electrode 29 is formed.
The opening 3 is formed in the photoresist 35 in the partial region 36 including the top and the gate extraction electrode (not shown).
6 is formed to form a via hole pattern connecting the first metal layer 31 and the second metal layer.

Then, as shown in FIG. 7B, RIE is performed.
The resin 34 in the partial region 36 exposed by the via hole pattern is etched by a method. After the metal wiring 37 as shown in FIG. 7B is formed in the via hole opened by this etching, the photoresist 35 is formed.
Is peeled off and coated again to form a photoresist pattern (not shown). Then, by a lift-off method using this photoresist pattern, as shown in FIG.
The second metal layer 38 as shown in FIG.
5) is formed.

Furthermore, it is possible to manufacture a semiconductor device having an arbitrary multilayer wiring structure. That is, by sequentially forming the BCB, the via hole connecting the second metal layer 38 and the third metal layer (16 in FIG. 16), the third metal layer, etc. on the second metal layer 38 following the above steps. The step of forming the multi-layer includes the BCB on the first metal layer, the via hole connecting the first metal layer 31 and the second metal layer 38, and the second hole.
This is similar to the step of forming the metal layer 38.

After that, if necessary, electrodes are formed, and the wafer is diced into individual semiconductor devices.
Next, an application example of the first embodiment will be described with reference to the layout diagram of FIG. In this application example, a GaAs substrate is used as a substrate for forming a semiconductor element such as a transistor, and an alumina substrate is used for a region other than the region where the semiconductor element is formed, that is, a so-called HMIC (Hybrid Microw
ave IC). A bonding wire 41 is used to electrically connect the GaAs substrate and the alumina substrate. The layer structure of the wiring on the alumina substrate is the same as when the semiconductor substrate 13 is regarded as the alumina substrate in FIG. In the case of a small-volume production product, the cost can be reduced by adopting the configuration of this embodiment.

(Second Embodiment) FIG. 9 shows a second embodiment of the present invention.
FIG. 6 is a layout diagram of the semiconductor device according to the embodiment of the present invention, specifically, a layout diagram including two transistors and their vicinity. FIG. 10 is a circuit diagram of the semiconductor device of this embodiment. In the present embodiment, an MMIC in which two stages of transistors 1 are provided on a semiconductor substrate is used. When a plurality of transistors 1 are provided in the semiconductor substrate, it may be necessary to give different source potentials to the respective transistors. In the present embodiment, as shown in FIG. 9, capacitors 9c and 9d having different source potentials of adjacent transistors 1 on their electrodes are used.
It was possible to apply different source potentials by providing the above in the high frequency ground section. The source potential of each stage is set to the capacitor 9
By separating by e, the effect of suppressing the oscillation of the high-frequency ground pattern having the source potential in the direct current in the semiconductor substrate can be exerted.

(Third Embodiment) FIG. 11 is a layout diagram of a semiconductor device according to a third embodiment of the present invention. FIG. 12 is a circuit diagram of the semiconductor device according to the embodiment. The wiring of the semiconductor device of the fourth embodiment is similar to the layer structure shown in the sectional view of FIG. In the present embodiment, the transistor 1 is of the gate G ground type. Thus, the ground electrode of the transistor is the source S
Not only grounding, but drain D grounding, gate G grounding, etc. can be appropriately selected according to the application of the circuit. Particularly, when the gate G is grounded, good characteristics in a high frequency band can be expected.

The present invention is not limited to the above embodiments. For example, although a T-type transistor is used as the transistor shape in the above-described embodiments, the present invention can be applied to π-type and comb-type transistors. Further, although the coplanar line is used for the wiring in the above-mentioned embodiment, the present invention can be applied to a microstrip line, a triplate line, and other lines. In addition, various modifications can be made without departing from the scope of the present invention.

[0039]

According to the semiconductor device of the present invention, the degree of freedom in circuit layout design is increased, and the chip area and the number of metal layers can be reduced.

[Brief description of drawings]

FIG. 1 is a layout diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of the semiconductor device according to the first embodiment.

FIG. 3 is a layout diagram in the vicinity of a bonding wire connection electrode according to the first embodiment.

FIG. 4 is a layout diagram near a bump connection electrode in the semiconductor device according to the first embodiment.

5A to 5D are cross-sectional views in order of the processes, for explaining the manufacturing method of the transistor according to the first embodiment.

FIG. 6 is a process sequential cross-sectional view for explaining the method for manufacturing the transistor according to the first embodiment, following FIG. 5;

7A to 7C are cross-sectional views in order of the processes, for explaining the method for manufacturing the transistor according to the first embodiment, following FIG.

FIG. 8 is a layout diagram for explaining an application example of the first embodiment.

FIG. 9 is a layout diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a circuit diagram of a semiconductor device according to a second embodiment.

FIG. 11 is a layout diagram of a semiconductor device according to a third embodiment of the present invention.

FIG. 12 is a circuit diagram of a semiconductor device according to a third embodiment.

FIG. 13 is a circuit diagram of a semiconductor device for explaining a conventional technique of the present invention.

FIG. 14 is a layout diagram of a semiconductor device according to a conventional technique of the present invention.

FIG. 15 is a plan view of a T-type transistor.

FIG. 16 is a cross-sectional view showing a multilayer wiring structure.

[Explanation of symbols]

1 ... T-type transistor G ... Gate S ... source D ... Drain 5 ... Coplanar signal line 7 ... Bridge 8 ... Contact 9 ... Capacitor 10 ... resistance 11 ... Source side electrode 11a ... High-frequency ground that is also ground in terms of direct current 12 ... Ground electrode 13, 21 ... Semiconductor substrate 14 ... First metal layer 15 ... Second metal layer 16 ... Third metal layer 18 ... Electrodes for connecting bonding wires 19 ... Bump connection electrode 22 ... Buffer layer 23 ... Channel layer 24 ... Spacer layer 25 ... Electron supply layer 26 ... Schottky contact layer 27 ... Ohmic contact layer 29 ... Ohmic electrode 30 ... Gate electrode 31 ... First metal layer 37, 38 ... Metal wiring 41 ... Bonding wire

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-8-330519 (JP, A) JP-A-4-157736 (JP, A) JP-A-4-225608 (JP, A) JP-A-7- 240645 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 27/095 H01L 21/822 H01L 21/8232 H01L 27/04 H01L 21/06

Claims (5)

(57) [Claims] 1. A transistor having a ground electrode; a capacitor provided with a counter electrode and connected in parallel to the ground electrode of the transistor; a resistor connected in parallel to the ground electrode of the transistor; a high frequency in an operating frequency band. First high with ground potential
A frequency ground; a DC ground provided separately from the first high frequency ground.
It has a round potential and high frequency grout in the operating frequency band.
A second high frequency ground having a ground potential; a first high frequency ground and a second high frequency ground
Consists of a high-frequency ground consisting of and a high-frequency wave signal line
Opposing constituting the capacitor; and a high-frequency line which is; and the first high-frequency ground, and the ground electrode of said transistor, one electrode of the counter electrode constituting the capacitor are formed from a common metal layer The other electrode of the electrodes is
It is connected to the second high-frequency ground; the common metal layer is a semiconductor device, characterized in that connected to the second high-frequency <br/> ground layer through the resistor. 2. The first high frequency ground has a region divided by the high frequency signal line, and the first high frequency ground divided by sandwiching the high frequency signal line is electrically connected by a bridge. The semiconductor device according to claim 1, wherein: 3. The ground electrode is divided and formed by a bridge.
2. The semiconductor device according to claim 1, wherein the resistance is electrically connected to each other, and the resistor is provided commonly to the ground electrodes formed in a divided manner. 4. The other electrode of the capacitor having a DC potential at the ground potential is provided in an upper layer or a lower layer of the first high frequency ground.
The semiconductor device described. 5. The semiconductor device according to claim 1, wherein the transistor is a T-type transistor, the high-frequency signal line and the high-frequency ground form a coplanar line, and the ground electrode is a source. .