JPH0661058A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH0661058A
JPH0661058A JP21400492A JP21400492A JPH0661058A JP H0661058 A JPH0661058 A JP H0661058A JP 21400492 A JP21400492 A JP 21400492A JP 21400492 A JP21400492 A JP 21400492A JP H0661058 A JPH0661058 A JP H0661058A
Authority
JP
Japan
Prior art keywords
inductor
conductive wiring
integrated circuit
circuit device
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21400492A
Other languages
Japanese (ja)
Inventor
Yoshihiro Yamamoto
佳弘 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP21400492A priority Critical patent/JPH0661058A/en
Publication of JPH0661058A publication Critical patent/JPH0661058A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To miniaturize a semiconductor integrated circuit device, by forming an inductor of a transmission circuit element formed in a semiconductor integrated circuit device or the like, in the structure wherein high inductance can be obtained in a minute area. CONSTITUTION:Two or more layers of ring type conductive wiring films 3a, 3b, 3c having notches are laminated on the surface of a semiconductor substrate 2, via interlayer insulating films 4a, 4b, 4c. The adjacent conductive wiring films are connected in series at the notched parts by using connection wirings 5a, 5b so as to have the same rotation direction. Thereby an inductor 1 is formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はインダクタおよびそのイ
ンダクタを使用した半導体集積回路装置に関する。さら
に詳しくは、インダクタの構造を立体的に形成し、面積
の縮小化を図ったインダクタおよび半導体集積回路装置
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inductor and a semiconductor integrated circuit device using the inductor. More specifically, the present invention relates to an inductor and a semiconductor integrated circuit device in which the structure of the inductor is three-dimensionally formed to reduce the area.

【0002】[0002]

【従来の技術】高周波用の半導体集積回路装置として従
来より、半導体基板に高周波用の電界効果トランジスタ
(以下、FETという)が形成されると共に、基板上に
インダクタやキャパシタが形成されたモノリシックマイ
クロ波集積回路装置(以下、MMICという)が利用さ
れている。
2. Description of the Related Art Conventionally, as a high frequency semiconductor integrated circuit device, a high frequency field effect transistor (hereinafter referred to as FET) is formed on a semiconductor substrate, and a monolithic microwave having an inductor and a capacitor formed on the substrate. An integrated circuit device (hereinafter referred to as MMIC) is used.

【0003】このMMICで、基板表面に形成される伝
送回路素子のうち、インダクタは図5に示されるような
構成になっている。図5においてガリウムヒ素(GaA
s)などからなる半導体基板22上にTi/Auからなる
導電配線膜23を渦巻状に形成することにより、インダク
タ21が作製されている。
In this MMIC, of the transmission circuit elements formed on the surface of the substrate, the inductor has a structure as shown in FIG. In FIG. 5, gallium arsenide (GaA
The inductor 21 is manufactured by forming the conductive wiring film 23 made of Ti / Au in a spiral shape on the semiconductor substrate 22 made of s) or the like.

【0004】[0004]

【発明が解決しようとする課題】叙上のインダクタ21は
インダクタンスを大きくするためには、渦巻状の巻き数
を多くしなければならない。しかし、巻き数を多くする
と、外周にいく程導電配線膜が長くなり、半導体基板22
表面の広い面積を占有することになる。このためMMI
Cの小型化が困難となり、それに伴い低コスト化も困難
になる。
In order to increase the inductance of the above inductor 21, the number of spiral turns must be increased. However, when the number of turns is increased, the conductive wiring film becomes longer toward the outer periphery, and the semiconductor substrate 22
It occupies a large surface area. Therefore, MMI
It becomes difficult to reduce the size of C, and accordingly it becomes difficult to reduce the cost.

【0005】本発明では、かかる問題を解消し、しかも
微小な面積で高インダクタンスがえられるインダクタの
構造を提供し、小型化した半導体集積回路装置を提供す
ることを目的とする。
It is an object of the present invention to solve the above problems and to provide a structure of an inductor capable of obtaining a high inductance in a small area, and to provide a miniaturized semiconductor integrated circuit device.

【0006】[0006]

【課題を解決するための手段】本発明のインダクタは、
基板上に、一部に切欠部を有するリング状の導電配線膜
が層間絶縁膜を介して2層以上積層され、隣接し合う前
記導電配線膜が同一回転方向となるように前記切欠部で
接続配線により直列に接続されてなることを特徴とする
ものである。
The inductor of the present invention comprises:
On the substrate, two or more layers of ring-shaped conductive wiring films partially having a cutout are laminated with an interlayer insulating film interposed therebetween, and the conductive wiring films adjacent to each other are connected at the cutout so that they are in the same rotation direction. It is characterized by being connected in series by wiring.

【0007】本発明の半導体集積回路装置は、半導体基
板に形成された能動素子と、該基板表面に形成されたイ
ンダクタを含む伝送回路素子とからなる半導体集積回路
装置であって、前記基板表面に形成される少なくとも一
のインダクタが請求項1記載のインダクタであることを
特徴とするものである。
A semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device comprising an active element formed on a semiconductor substrate and a transmission circuit element including an inductor formed on the surface of the substrate. At least one inductor formed is the inductor according to claim 1.

【0008】[0008]

【作用】本発明によれば、インダクタは基板表面上にリ
ング状の導電配線膜が層間絶縁膜を介して積層され各層
の導電配線膜を直列接続して形成しているため、1つの
リング状の導電配線膜の面積でインダクタを形成でき、
小さな面積でインダクタを形成できる。しかもコイルを
形成する導電配線膜およびそのあいだの層間絶縁膜は薄
く形成でき、所望のインダクタスンに応じて何層でも形
成でき、小さな面積で大きなインダクタンスを有するイ
ンダクタを形成できる。
According to the present invention, the inductor is formed by stacking the ring-shaped conductive wiring films on the surface of the substrate through the interlayer insulating film and connecting the conductive wiring films of the respective layers in series. An inductor can be formed with the area of the conductive wiring film of
An inductor can be formed with a small area. Moreover, the conductive wiring film forming the coil and the interlayer insulating film between them can be formed thin, and any number of layers can be formed according to a desired inductor, and an inductor having a large inductance in a small area can be formed.

【0009】[0009]

【実施例】つぎに図面を参照しながら本発明について説
明する。図1は、本発明の一実施例である伝送回路素子
のインダクタ部分を示す断面説明図、図2は図1のイン
ダクタ部分の立体配置を模式的に示した斜視説明図、図
3は図1のインダクタを含む高周波増幅回路の主要部分
を示す平面配置図、図4は図3の等価回路図である。
The present invention will be described below with reference to the drawings. 1 is a cross-sectional explanatory view showing an inductor portion of a transmission circuit element which is an embodiment of the present invention, FIG. 2 is a perspective explanatory view schematically showing a three-dimensional arrangement of the inductor portion of FIG. 1, and FIG. 4 is a plan layout view showing a main part of a high-frequency amplifier circuit including the inductor of FIG. 4, and FIG. 4 is an equivalent circuit diagram of FIG.

【0010】本発明の半導体集積回路装置の構成要素で
あるインダクタ1の構造を図1〜2に基づき説明する。
たとえばガリウムヒ素(GaAs)などからなる半導体
基板2上にTi/Auからなる第1の導電配線膜3a
が、蒸着またはスパッタリング法とフォトリソグラフィ
工程などにより一部分切欠した矩形のループ状に、0.5
〜2μmの厚さの帯状膜により形成されている。その表
面にはCVD法やスパッタ法などにより、SiO2 膜ま
たはSiN膜などからなる第1の層間絶縁膜4aが0.5
〜1μmの厚さで形成されている。この第1の層間絶縁
膜4aの表面には、第1層と同様に第2の導電配線膜3
bおよび第2の層間絶縁膜4bが形成されている。前記
第1および第2の導電配線膜3a、3bはそれぞれの一
方の端部をTi/Pt/Auからなる第1の接続配線5
aによって電気的に接続されている。第1の接続配線5
aは、第2の導電配線膜3bを形成する前に第1の層間
絶縁膜4aの一部をエッチングしてコンタクト孔を形成
し、表面に導電配線膜と同じ金属材料を蒸着またはスパ
ッタリングなどをすることにより形成される。さらに同
様にして第2の層間絶縁膜の上には、第3の導電配線膜
3cおよび第3の層間絶縁膜4cが形成されている。こ
の際、第2の導電配線膜の他端部およびその直上にある
第3の導電配線膜3cの一方の端部は前述の第1の接続
配線5aと同様に形成される第2の接続配線5bによっ
て電気的に接続されている。さらに第3の層間絶縁膜4
cの一部にコンタクト孔が形成され、その表面に電極配
線6が形成されており、他の素子と電気的に接続できる
ようになっている。この各導電配線膜の接続は隣接し合
う導電配線膜が同一回転方向となるように前述の各切欠
部で接続配線により直列に接続され、コイルを形成して
いる。
The structure of the inductor 1 which is a constituent element of the semiconductor integrated circuit device of the present invention will be described with reference to FIGS.
For example, the first conductive wiring film 3a made of Ti / Au is formed on the semiconductor substrate 2 made of gallium arsenide (GaAs).
However, it has a rectangular loop shape that is partially cut by the evaporation or sputtering method and the photolithography process.
It is formed of a band-shaped film having a thickness of ˜2 μm. The first interlayer insulating film 4a made of a SiO 2 film or a SiN film is formed on the surface by a CVD method or a sputtering method.
It is formed with a thickness of ˜1 μm. On the surface of the first interlayer insulating film 4a, the second conductive wiring film 3 is formed similarly to the first layer.
b and the second interlayer insulating film 4b are formed. One end of each of the first and second conductive wiring films 3a and 3b is a first connection wiring 5 made of Ti / Pt / Au.
It is electrically connected by a. First connection wiring 5
a is formed by etching a part of the first interlayer insulating film 4a to form a contact hole before forming the second conductive wiring film 3b, and depositing the same metal material as the conductive wiring film on the surface by sputtering or sputtering. It is formed by Further, similarly, a third conductive wiring film 3c and a third interlayer insulating film 4c are formed on the second interlayer insulating film. At this time, the other end of the second conductive wiring film and one end of the third conductive wiring film 3c immediately above the second conductive wiring film are formed in the same manner as the above-mentioned first connecting wiring 5a. It is electrically connected by 5b. Further, the third interlayer insulating film 4
A contact hole is formed in a part of c, and the electrode wiring 6 is formed on the surface thereof so that it can be electrically connected to another element. The conductive wiring films are connected in series by connecting wirings at the above-mentioned notches so that the adjacent conductive wiring films have the same rotation direction to form a coil.

【0011】叙上のように構成されるインダクタ1は、
図2に示されるように、第1から第3の導電配線膜の端
部同士が直列に接続され、半導体基板2の表面に対して
垂直方向に延びる導電配線膜の積層体として形成されて
いる。このため、インダクタ1による半導体基板2上の
占有面積が小さくてもコイルの巻き数を増やすことがで
きる。さらにインダクタの仕様を変更するばあい、積層
する導電配線膜の数を変えるだけで比較的簡単に所望の
インダクタンスをうることができ、積層する膜の数は2
層以上で自由に設定できる。
The inductor 1 constructed as above is
As shown in FIG. 2, the end portions of the first to third conductive wiring films are connected in series and are formed as a laminated body of conductive wiring films extending in the direction perpendicular to the surface of the semiconductor substrate 2. . Therefore, the number of turns of the coil can be increased even if the area occupied by the inductor 1 on the semiconductor substrate 2 is small. Furthermore, when changing the specifications of the inductor, it is possible to obtain the desired inductance relatively simply by changing the number of conductive wiring films to be stacked.
It can be set freely in more than one layer.

【0012】つぎに叙上のように構成されるインダクタ
を有するMMICについて、図3〜4に基づき説明す
る。MMICは半導体基板にFETやダイオードなどの
能動素子が形成され、基板表面にインダクタやキャパシ
タなどの伝送回路素子が形成される。
Next, an MMIC having the above-described inductor will be described with reference to FIGS. In the MMIC, active elements such as FETs and diodes are formed on a semiconductor substrate, and transmission circuit elements such as inductors and capacitors are formed on the surface of the substrate.

【0013】図3〜4に示されるように、低雑音マイク
ロ波増幅器などに用いられるMMICのマイクロ波用F
ET周辺の主要部は、増幅用FET7のゲート電極8が
第1の端子9にインダクタ10を介して電気的に接続さ
れ、ドレイン電極11が第2の端子12にインダクタ13を介
して電気的に接続され、ソース電極14がグランド側端子
15にインダクタ16を介して電気的に接続されて構成され
ている。第1の端子および第2の端子9、12のそれぞれ
入力側および出力側には図4に等価回路図で示すよう
に、直流カットのためのコンデンサ17、18が接続される
と共に、さらにインダクタ19、20を介してそれぞれ第1
のバイアス端子21および第2のバイアス端子22が形成さ
れDCバイアスを供給できるようになっている。
As shown in FIGS. 3 and 4, an MMIC microwave F used in a low noise microwave amplifier or the like.
In the main part around ET, the gate electrode 8 of the amplification FET 7 is electrically connected to the first terminal 9 through the inductor 10, and the drain electrode 11 is electrically connected to the second terminal 12 through the inductor 13. Connected, the source electrode 14 is the ground side terminal
It is configured to be electrically connected to 15 through an inductor 16. As shown in the equivalent circuit diagram of FIG. 4, capacitors 17 and 18 for cutting direct current are connected to the input side and the output side of the first and second terminals 9 and 12, respectively, and an inductor 19 is further provided. , 20 through 1st respectively
Bias terminal 21 and second bias terminal 22 are formed so that a DC bias can be supplied.

【0014】この増幅回路は、インダクタ10、13、16が
従来のものに比べ微小な面積で配置されているため、回
路全体が小型化されている。
In this amplifier circuit, the inductors 10, 13 and 16 are arranged in a smaller area than the conventional one, so that the entire circuit is miniaturized.

【0015】なお本実施例では、矩形のループ状の導電
配線膜を積層した例で示したが、本発明はこの形状に限
定されず、円形のループ状の導電配線膜を積層したもの
でもよく、どんな形状のコイルでもホトリソグラフィ工
程により形成できる。
In this embodiment, an example in which rectangular loop-shaped conductive wiring films are laminated is shown, but the present invention is not limited to this shape, and circular loop-shaped conductive wiring films may be laminated. Any shape coil can be formed by photolithography process.

【0016】[0016]

【発明の効果】本発明によれば、コイル部分を基板の表
面に対して垂直方向に導電配線膜を積層してインダクタ
を形成しているため、巻き数を増やしても、面積的には
変わらず、微小な面積で高インダクタンスがえられる。
According to the present invention, since the inductor is formed by laminating the conductive wiring film in the coil portion in the direction perpendicular to the surface of the substrate, the area is changed even if the number of turns is increased. In addition, high inductance can be obtained in a small area.

【0017】また、半導体基板にFETなど高周波素子
が形成されると共に、基板表面に形成されるインダクタ
が本発明のインダクタで形成されることにより、チップ
面積の小さいモノリシックマイクロ波集積回路装置を形
成できる。さらには素子面積が小さくなる結果、素子間
を接続する配線も短かくなり、マイクロ波帯域で起り易
い配線での相互干渉やノイズの発生も抑制でき、高特性
のモノリシックマイクロ波集積回路装置をうることがで
きる。
Further, a high frequency element such as an FET is formed on a semiconductor substrate, and an inductor formed on the surface of the substrate is formed by the inductor of the present invention, whereby a monolithic microwave integrated circuit device having a small chip area can be formed. . Furthermore, as a result of the smaller element area, the wiring connecting the elements becomes shorter, mutual interference and noise generation in the wiring that tends to occur in the microwave band can be suppressed, and a monolithic microwave integrated circuit device with high characteristics can be obtained. be able to.

【0018】また装置の小型化に伴ない、最近の電子機
器の小型化に対応できると共に、コストダウンにも寄与
するという効果がある。
Further, with the miniaturization of the device, it is possible to cope with the recent miniaturization of electronic equipment and to contribute to cost reduction.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例であるインダクタ部分を示す
断面説明図である。
FIG. 1 is a cross-sectional explanatory view showing an inductor portion which is an embodiment of the present invention.

【図2】図1のインダクタのコイル部分を模式的に示し
た斜視図である。
FIG. 2 is a perspective view schematically showing a coil portion of the inductor shown in FIG.

【図3】高周波増幅回路の主要部分を示す平面配置図で
ある。
FIG. 3 is a plan layout view showing a main part of a high frequency amplifier circuit.

【図4】図3の等価回路図である。FIG. 4 is an equivalent circuit diagram of FIG.

【図5】従来のインダクタを示す平面説明図である。FIG. 5 is an explanatory plan view showing a conventional inductor.

【符号の説明】[Explanation of symbols]

1 インダクタ 2 半導体基板 3a 第1の導電配線膜 3b 第2の導電配線膜 3c 第3の導電配線膜 4a 第1の層間絶縁膜 4b 第2の層間絶縁膜 4c 第3の層間絶縁膜 5a 第1の接続配線 5b 第2の接続配線 1 Inductor 2 Semiconductor substrate 3a First conductive wiring film 3b Second conductive wiring film 3c Third conductive wiring film 4a First interlayer insulating film 4b Second interlayer insulating film 4c Third interlayer insulating film 5a First Connection wiring 5b Second connection wiring

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板上に、一部に切欠部を有するリング
状の導電配線膜が層間絶縁膜を介して2層以上積層さ
れ、隣接し合う前記導電配線膜が同一回転方向となるよ
うに前記切欠部で接続配線により直列に接続されてなる
インダクタ。
1. A ring-shaped conductive wiring film having a notch in a part thereof is laminated on a substrate by two or more layers via an interlayer insulating film, and the conductive wiring films adjacent to each other have the same rotation direction. An inductor which is connected in series by connection wiring at the cutout portion.
【請求項2】 半導体基板に形成された能動素子と、該
基板表面に形成されたインダクタを含む伝送回路素子と
からなる半導体集積回路装置であって、前記基板表面に
形成される少なくとも一のインダクタが請求項1記載の
インダクタであることを特徴とする半導体集積回路装
置。
2. A semiconductor integrated circuit device comprising an active element formed on a semiconductor substrate and a transmission circuit element including an inductor formed on the surface of the substrate, wherein at least one inductor formed on the surface of the substrate. Is the inductor according to claim 1, wherein the semiconductor integrated circuit device is a semiconductor integrated circuit device.
JP21400492A 1992-08-11 1992-08-11 Semiconductor integrated circuit device Pending JPH0661058A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21400492A JPH0661058A (en) 1992-08-11 1992-08-11 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21400492A JPH0661058A (en) 1992-08-11 1992-08-11 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0661058A true JPH0661058A (en) 1994-03-04

Family

ID=16648673

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21400492A Pending JPH0661058A (en) 1992-08-11 1992-08-11 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0661058A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001046971A1 (en) * 1999-12-20 2001-06-28 Advanced Micro Devices, Inc. Multi-layer inductor and transformer formed on an integrated circuit substrate
EP1189293A2 (en) * 2000-08-21 2002-03-20 Infineon Technologies AG Monolithic integrable inductor
KR100390448B1 (en) * 1995-12-05 2003-09-19 주식회사 하이닉스반도체 Inductor omitted
WO2008016089A1 (en) 2006-08-01 2008-02-07 Nec Corporation Inductor element, inductor element manufacturing method, and semiconductor device with inductor element mounted thereon
EP1503415A3 (en) * 2003-07-26 2011-04-27 Samsung Electronics Co., Ltd. On-chip Inductors having interconnect and inductor portions providing combined magnetic fields
US8310316B2 (en) 2007-09-28 2012-11-13 Nec Corporation Oscillator circuit
US9076502B2 (en) 2013-07-30 2015-07-07 Kabushiki Kaisha Toshiba Non-volatile memory device
WO2020170411A1 (en) * 2019-02-22 2020-08-27 三菱電機株式会社 Semiconductor device and power conversion device
US11189416B2 (en) 2017-06-05 2021-11-30 Murata Manufacturing Co., Ltd. Coil component and method of changing frequency characteristic thereof

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100390448B1 (en) * 1995-12-05 2003-09-19 주식회사 하이닉스반도체 Inductor omitted
WO2001046971A1 (en) * 1999-12-20 2001-06-28 Advanced Micro Devices, Inc. Multi-layer inductor and transformer formed on an integrated circuit substrate
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