JP2011171622A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is excellent in power efficiency, can exhibit designed performance and can be miniaturized, and a manufacturing method thereof. <P>SOLUTION: A stub connected to a drain electrode is formed on a semiconductor substrate with a semiconductor device such as a field-effect transistor in such a way that an insulating layer is interleaved on an electrode extended from the source electrode. In other words, an element forming region 22 is provided with a substrate 20 on which a stub region 26 and an active device region 24 are defined, a semiconductor device having a first main electrode 42 and a second main electrode 44 formed on a substrate of the active device region, an first insulating film 50 formed on the substrate of the stub region and a side of the semiconductor device, a ground electrode 60 formed on the first insulating film and electrically connected to the second main electrode, a second insulating film 52 formed on the ground electrode, and a stub electrode 62 formed on the second insulating layer, and electrically connected to the first main electrode. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, in particular, a semiconductor device in which a high-frequency processing stub is formed on the same substrate as a semiconductor element, and a manufacturing method thereof.

  In wireless communication, the frequency has been increased due to the demand for higher speed and larger capacity of information communication or effective use of radio frequency. In addition, reduction of power consumption in a wireless communication system is also desired. Therefore, there is a demand for higher frequency and lower power consumption of semiconductor devices used in receivers and transmitters of wireless communication systems.

  In a semiconductor device used in a radio communication system in a high frequency region such as a microwave and a millimeter wave, a compound semiconductor such as gallium arsenide (GaAs), indium phosphide (InP), or gallium nitride (GaN) is used as a semiconductor material. This is because a compound semiconductor exhibits excellent high-frequency characteristics compared to a silicon semiconductor, such as high electron mobility.

  Among compound semiconductors, particularly GaN has a higher dielectric breakdown voltage than other compound semiconductors such as GaAs and InP. For this reason, for example, since a high voltage can be applied to the GaN transistor, the power efficiency is increased, and a reduction in power consumption can be expected.

  In order to improve the power efficiency of a semiconductor element used in a high frequency region, there is a technique of providing a dielectric substrate on which a transmission line having a stub is formed on the output side of the semiconductor element. In this technique, harmonics can be reflected to the semiconductor element, and the class F operation of the circuit becomes possible (see, for example, Patent Documents 1, 2, and 3).

  Also, a technique for forming a so-called open stub, a microstrip line, or a coplanar transmission line on a semiconductor substrate on which a field effect transistor is formed has been reported (see, for example, Patent Documents 4 and 5).

JP 2001-111362 A JP 2003-234626 A JP 2008-113402 A JP 2006-173595 A JP-A-11-150126

  However, in the techniques disclosed in Patent Documents 1, 2, and 3, the transmission line having the stub is formed on a dielectric substrate different from the semiconductor substrate on which the semiconductor element is formed. For this reason, the occupation area of the circuit provided with the semiconductor element formed on the semiconductor substrate and the transmission line is increased.

  Furthermore, there is a problem that it is difficult to obtain the performance as designed due to parasitic elements such as bonding wires connecting the semiconductor element and the transmission line.

  In the techniques disclosed in Patent Documents 4 and 5, although not easily affected by parasitic elements, a ground electrode (GND) for the transmission line is provided on the back side of the insulating substrate. For this reason, for example, in the microstrip line, the design may be difficult because the line width cannot be reduced.

  The present invention has been made in view of the above-described problems, and an object of the present invention is a semiconductor device having excellent power efficiency, which can obtain performance as designed and can be miniaturized. A semiconductor device and a manufacturing method thereof are provided.

  In order to achieve the above-described object, a semiconductor device of the present invention includes a ground electrode in which a stub electrode connected to a drain electrode is extended from a source electrode on a semiconductor substrate on which a semiconductor element such as a field effect transistor is formed. An insulating film is interposed therebetween.

  That is, the semiconductor device of the present invention includes a substrate, a semiconductor element, a first insulating film, a ground electrode, a second insulating film, and a stub electrode.

  A stub area and an active element area are set in the element formation area of the substrate. The semiconductor element includes a semiconductor growth portion formed on a substrate in an active element region, a first main electrode, and a second main electrode. The first insulating film is formed from the upper surface of the substrate in the stub region to the side surface of the semiconductor growth portion. The ground electrode is formed on the first insulating film and is electrically connected to the second main electrode of the semiconductor element. The second insulating film is formed on the ground electrode. The stub electrode is formed on the second insulating film and is electrically connected to the first main electrode of the semiconductor element.

  The method for manufacturing a semiconductor device according to the present invention comprises the following steps.

  First, a substrate in which a stub area and an active element area are set in an element forming area is prepared. Next, a semiconductor growth layer is formed on the substrate. Next, the semiconductor growth layer in the stub region is removed, and a semiconductor growth portion is formed in the active element region. Next, a first main electrode and a second main electrode are formed on the semiconductor growth portion, thereby forming a semiconductor element including the semiconductor growth portion, the first main electrode, and the second main electrode. Next, a first insulating film is formed from the upper surface of the substrate in the stub region to the side surface of the semiconductor growth portion. Next, a ground electrode electrically connected to the second main electrode of the semiconductor element is formed on the first insulating film. Next, a second insulating film is formed on the ground electrode. Next, a stub electrode that is electrically connected to the first main electrode of the semiconductor element is formed on the second insulating film.

  According to the semiconductor device of the present invention, the occupation area can be reduced by forming the stub electrode on the same substrate as the semiconductor element. Further, since the stub electrode is directly connected to the first main electrode of the semiconductor element, the influence of the parasitic element can be suppressed.

  According to the semiconductor device of the present invention, the ground electrode drawn from the second main electrode and the stub electrode connected to the first main electrode are formed on the substrate with the ground electrode and the insulating film interposed therebetween. is doing. For this reason, when the stub is configured by a microstrip line, the line width can be reduced as compared with the configuration in which the back electrode of the substrate is used as GND. Further, the ground electrode of the microstrip line can be grounded without forming a via hole.

1 is a schematic diagram of a semiconductor device according to a first embodiment. It is the schematic for demonstrating the design of the transmission line formed as a microstrip line. It is the schematic of the semiconductor device of 2nd Embodiment. It is process drawing (1) for demonstrating the manufacturing method of a semiconductor device. It is process drawing (2) for demonstrating the manufacturing method of a semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the shape, size, and arrangement relationship of each component are merely schematically shown to the extent that the present invention can be understood. In the following, a preferred configuration example of the present invention will be described. However, the material and numerical conditions of each component are merely preferred examples. Therefore, the present invention is not limited to the following embodiments, and many changes or modifications that can achieve the effects of the present invention can be made without departing from the scope of the configuration of the present invention.

(Semiconductor Device of First Embodiment)
With reference to FIGS. 1A and 1B, the semiconductor device of the first embodiment will be described. 1A and 1B are schematic views for explaining the semiconductor device of the first embodiment. FIG. 1A is a top view. Moreover, FIG. 1 (B) has shown the cut surface of the cross section along the AA 'line of FIG. 1 (A). Note that in FIG. 1B, a line indicating the connection relationship between the electrodes is provided, but this is not included in the cut surface of the cross section.

  Here, a configuration example will be described in which the semiconductor device 10 includes a transistor using gallium nitride (GaN) as a channel material.

  In this embodiment, an active element region 24 and a stub region 26 are set in the element formation region 22 of the substrate 20. The element formation region 22 is defined by an element isolation region (not shown) provided around the element formation region 22.

  As the substrate 20, an insulating substrate, for example, an insulating Si substrate is used. A semiconductor growth portion 30 is provided on the active element region 24 of the substrate 20. The semiconductor growth section 30 is configured by sequentially stacking a buffer layer 32 made of AlN, a channel layer 34 made of GaN, and a carrier supply layer 36 made of AlGaN.

  On the carrier supply layer 36, a gate electrode 40 is formed as a control electrode. On the carrier supply layer 36, a drain electrode 42 as a first main electrode and a source electrode 44 as a second main electrode are provided. The gate electrode 40 is manufactured as a Schottky electrode, and the drain electrode 42 and the source electrode 44 are manufactured as ohmic electrodes.

  The semiconductor growth portion 30, the gate electrode 40, the drain electrode 42, and the source electrode 44 formed on the substrate 20 in the active element region 24 constitute a GaN transistor as a semiconductor element.

  A first insulating film 50 is formed from the upper surface of the substrate of the stub region 26 adjacent to the active element region 24 to the side surface of the semiconductor growth portion 30. For example, the first insulating film 50 is formed as a silicon nitride film (SiN film). A ground electrode 60 is formed on the first insulating film 50. The ground electrode 60 is electrically connected to the source electrode 44.

  A second insulating film 52 is formed on the ground electrode 60. A stub electrode 62 is formed on the second insulating film 52. The stub electrode 62 is provided with the ground electrode 60 and the second insulating film 52 interposed therebetween, and constitutes a so-called microstrip line.

  The stub electrode 62 is electrically connected to the drain electrode 42 and is formed as an open stub. The connection position of the stub electrode 62 with the drain electrode 42 is preferably closer to the drain electrode 42 in order to suppress the influence of parasitic elements.

  The length of the stub electrode 62 is determined by the order of harmonics to be processed. As an operation of the transistor, a case where power is input from the gate side and power is amplified from the drain side and output is described. In this case, when the input power is increased, the linearity of the power amplification factor (gain) is deteriorated, and the harmonic component of the fundamental frequency f is output as power. Here, when the length of the stub electrode 62 is set to 1/8 of the wavelength λ determined by the fundamental frequency f, the second harmonic (second harmonic) can be reflected.

  The design of the transmission line will be described with reference to FIG. FIG. 2 is a schematic diagram for explaining the design of a transmission line formed as a microstrip line.

  In the microstrip line, it is known that the following relationship holds among the dielectric constant εr of the insulating substrate 100, the width W of the transmission line 102, and the thickness h of the insulating substrate 100.

Where λ ₀ is the wavelength determined by the fundamental frequency f in free space, V _p is the phase velocity, c is the speed of light in vacuum, and ε _ff is the effective Dielectric constant. In addition, in said formula (1)-(5), although it is carried in to the constant, the thickness t of the transmission line 102 exists further as a parameter.

For example, assuming that the fundamental frequency f is 5 GHz, the dielectric constant ε _r of the insulating substrate 100 is 10, the width W of the transmission line 102 is 80 μm, and the thickness t of the transmission line 102 is 1 μm, the thickness h of the insulating substrate 100 is At 100 μm, the 1 / 8λ length is 2.9 mm. Further, from the above formulas (2) to (5), when the thickness h of the insulating substrate 100, that is, the distance between the transmission line 102 and the ground electrode 104 is reduced, the width W of the transmission line 102 of the microstrip line is reduced. However, the same electrical characteristics can be obtained.

  According to the semiconductor device of this embodiment, the occupation area can be reduced by forming the high-frequency processing stub on the same substrate as the semiconductor element. Further, since the stub electrode is directly connected to the drain electrode which is the main electrode of the semiconductor element, the influence of the parasitic element can be suppressed.

  Further, according to the semiconductor device 10 of this embodiment, the ground electrode 60 drawn from the source electrode 44 on the substrate 20 and the ground electrode 60 and the second insulating film 52 are sandwiched between the drain electrode 42 and the ground electrode 60. The stub electrode 62 is provided. Thus, when the stub is constituted by a microstrip line, the electrical characteristics of the microstrip line are determined not by the thickness up to the back electrode 70 of the substrate 20 but by the thickness of the second insulating film 52. The line width can be reduced.

  Further, the ground electrode 60 of the microstrip line can be grounded without forming a via hole. Further, when the stub is formed by a microstrip line, the simulation is easier than when the stub is formed by a coplanar line, and the area can be reduced as compared with the coplanar line.

(Semiconductor Device of Second Embodiment)
With reference to FIGS. 3A and 3B, the semiconductor device of the second embodiment will be described. 3A and 3B are schematic views for explaining the semiconductor device of the second embodiment. FIG. 3A is a top view. FIG. 3B shows a cross-section cut along the line AA ′ in FIG. Note that in FIG. 3B, a line indicating the connection relationship between the electrodes is provided, but this is not included in the cross section.

  The semiconductor device 11 of the second embodiment is different from the first embodiment in that the stub provided in the stub region 26 is formed of a coplanar line, and other configurations are the same as those of the first embodiment. is there. Therefore, the overlapping description may be omitted here.

  The stub is configured as a so-called coplanar line. The coplanar line includes a pair of ground lines at positions sandwiching the transmission line. In this embodiment, the stub electrode 62 as a transmission line is electrically connected to the drain electrode 42 and formed as an open stub. The ground line 64 is electrically connected to the source electrode 44. FIG. 3A shows a configuration example in which a pair of ground lines provided at positions sandwiching the stub electrode 62 are connected to each other to form an integral structure.

  According to the configuration of this embodiment, as in the first embodiment, the occupation area can be reduced by forming the stub on the same substrate as the semiconductor element. Further, since the stub is directly connected to the drain which is the main electrode of the semiconductor element, the influence of the parasitic element can be suppressed.

(Method for manufacturing semiconductor device)
With reference to FIGS. 4A to 4C and FIGS. 5A to 5C, a method for manufacturing a semiconductor device will be described. 4 (A) to 4 (C) and FIGS. 5 (A) to 5 (C) are process diagrams for explaining a method of manufacturing a semiconductor device, and show cut end surfaces of main parts obtained in the respective processes. ing.

  First, the substrate 20 in which the active element region 24 and the stub region 26 are set in the element forming region 22 is prepared. For example, an insulating Si substrate is used as the substrate 20.

  Next, a semiconductor growth layer 30 a is formed on the substrate 20 in the active element region 24. In this step, first, an AlN layer 32a, a GaN layer 34a, and an AlGaN layer 36a are sequentially grown on the entire surface of the first main surface 20a of the substrate 20 by metal organic vapor phase epitaxy (MOVPE) to obtain a semiconductor growth layer. 30a is formed.

  Further, an insulator film 38a is formed on the AlGaN layer 36a. In this step, a SiN film as the insulator film 38a is formed by a chemical vapor deposition (CVD) method (FIG. 4A).

  Next, the semiconductor growth layer 30a and the insulator film 38a in the stub region 26 are removed by inductively coupled reactive ion etching (ICP-RIE) to expose the substrate 20 in the stub region 26, and the substrate in the active element region 24. The semiconductor growth portion 30 and the insulating film 38b are left on the substrate 20 (FIG. 4B). Further, element isolation of the element formation region 22 is performed. This element isolation can be performed by any suitable method. Here, it is assumed that ion isolation is performed in the element isolation region to insulate the semiconductor growth layer in the element isolation region.

  Next, a control electrode, a first main electrode, and a second main electrode are formed on the semiconductor growth portion 30 in the active element region 24. In the case of the GaN transistor formed here, the gate electrode 40 as the control electrode is formed as a so-called Schottky electrode. The drain electrode 42 as the first main electrode and the source electrode 44 as the second main electrode are formed as ohmic electrodes. The semiconductor growth portion 30, the gate electrode 40, the drain electrode 42, and the source electrode 44 constitute a GaN transistor as a semiconductor element.

  About the process of forming each electrode of this GaN transistor, what is necessary is just to carry out by an arbitrary suitable well-known method, Therefore It abbreviate | omits description here.

  After the semiconductor element is formed by the above steps, the first insulating film 50 is formed on the substrate 20. In this step, the SiN film 50a that covers the exposed upper surface of the substrate 20 and the semiconductor element is formed by CVD (FIG. 4C). Next, the SiN film 50a is etched by ICP-RIE to form the first insulating film 50 that exposes the source electrode 44.

  Next, a ground electrode 60 that is electrically connected to the source electrode 44 is formed on the first insulating film 50. The formation of the ground electrode 60 can be performed by using a technique similar to that of normal wiring formation (FIG. 5A).

  Next, the second insulating film 52 is formed on the ground electrode 60. The formation of the second insulating film 52 can be performed in the same manner as the formation of the first insulating film 50 (FIG. 5B).

  A stub electrode 62 electrically connected to the drain electrode 42 is formed on the second insulating film 52. The stub electrode 62 and the ground electrode 50 provided with the second insulating film 52 interposed therebetween constitute a so-called microstrip line (FIG. 5C).

  Here, an example in which the high-frequency processing stub is configured by a microstrip line has been described. In the case of a coplanar line, when the stub electrode 62 as a transmission line connected to the drain electrode 42 is formed, the ground line connected to the source electrode 44 may be formed together.

  In each of the above-described embodiments, the high electron mobility transistor (HEMT) using gallium nitride (GaN) as a channel material has been described. However, the present invention is not limited to this, and other materials may be used. Further, an active element such as a so-called field effect transistor (FET) may be formed as a semiconductor element included in the semiconductor device.

  Moreover, although the process with respect to the 2nd harmonic was demonstrated here, you may provide a stub also with respect to the 3rd or higher harmonic. However, for higher harmonics, the degree of improvement in power efficiency is small, so processing up to the third harmonic is usually sufficient.

  Further, here, the configuration example including only the HEMT and the stub has been described, but a monolithic microwave integrated circuit (MMIC) including an impedance matching circuit and a bias circuit may be used. Further, although the stub is provided on the drain electrode on the output side, the stub may be provided on the gate electrode on the input side.

10, 11 Semiconductor device
DESCRIPTION OF SYMBOLS 20 Substrate 22 Element formation area 24 Active element area 26 Stub area 30 Semiconductor growth part 32 Buffer layer 34 Channel layer 36 Carrier supply layer 40 Gate electrode 42 Drain electrode 44 Source electrode 50 First insulating film 52 Second insulating film 60 Ground electrode 62 Stub electrode 64 Ground line 70 Back electrode

Claims (5)

A substrate in which an active element region and a stub region are set in an element formation region;
A semiconductor element composed of a semiconductor growth portion formed on the substrate in the active element region, and a first main electrode and a second main electrode formed on the semiconductor growth portion;
A first insulating film formed from an upper surface of the substrate in the stub region to a side surface of the semiconductor growth portion;
A ground electrode formed on the first insulating film and electrically connected to the second main electrode;
A second insulating film formed on the ground electrode;
A semiconductor device comprising: a stub electrode formed on the second insulating film and electrically connected to the first main electrode.   2. The semiconductor device according to claim 1, further comprising a ground line electrically connected to the second main electrode at a position on the second insulating film with the stub electrode interposed therebetween. The two active element regions are set at positions sandwiching the stub region,
The stub electrode is connected to both of the first main electrodes formed in each of the two active element regions;
The semiconductor device according to claim 1, wherein the ground electrode is connected to both of the second main electrodes formed in each of the two active element regions. Preparing a substrate in which an active element region and a stub region are set in an element formation region;
Forming a semiconductor growth layer on the substrate;
Removing the semiconductor growth layer in the stub region and forming a semiconductor growth portion in the active element region;
Forming a first main electrode and a second main electrode on the semiconductor growth portion to form a semiconductor element composed of the semiconductor growth portion and the first main electrode and the second main electrode;
Forming a first insulating film from the upper surface of the substrate in the stub region to the side surface of the semiconductor growth portion;
Forming a ground electrode electrically connected to the second main electrode on the first insulating film;
Forming a second insulating film on the ground electrode;
Forming a stub electrode electrically connected to the first main electrode on the second insulating film. A method of manufacturing a semiconductor device, comprising: 5. The semiconductor according to claim 4, further comprising a step of forming a ground line electrically connected to the second main electrode at a position on the second insulating film with the stub electrode interposed therebetween. Device manufacturing method.

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