JPS6348855A - Monolithick microwave integrated circuit - Google Patents

Monolithick microwave integrated circuit

Info

Publication number
JPS6348855A
JPS6348855A JP19421886A JP19421886A JPS6348855A JP S6348855 A JPS6348855 A JP S6348855A JP 19421886 A JP19421886 A JP 19421886A JP 19421886 A JP19421886 A JP 19421886A JP S6348855 A JPS6348855 A JP S6348855A
Authority
JP
Japan
Prior art keywords
inductor
bias circuit
circuit section
insulating film
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19421886A
Other languages
Japanese (ja)
Inventor
Yasuro Mitsui
三井 康郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP19421886A priority Critical patent/JPS6348855A/en
Publication of JPS6348855A publication Critical patent/JPS6348855A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body

Abstract

PURPOSE:To reduce the area of a bias circuit device and to implement high integration density and reduction in chip price as a result, by forming an inductor on an insulating film formed on a substrate electrode, and constituting the bias circuit part. CONSTITUTION:An inductor 5 is formed on an insulating film 11, which is continuously deposited and formed on a substrate electrode 10. A capacitor is formed between the inductor 5 and the substrate electrode 10. Therefore, the area of a bias circuit part can be reduced. As a result, an IC chip can be integrated, and the price of the chip can be made low.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、U HF帯辺上の超高周波帯で動作するモ
ノリシック化マイクロ波集積回路(以下MMICと略ず
)に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a monolithic microwave integrated circuit (hereinafter abbreviated as MMIC) that operates in an ultra-high frequency band on the UHF band.

〔従来の技術〕[Conventional technology]

第3図は一般に用いられるMMICの等価回路図である
。この図において、1はMM I C中に形成される能
動回路部である砒化ガリウム電界効果トランジスタ(以
下FETと略す)、2は前記FETIのドレイン端子、
3は前記ドレイン端子2に直流バイアスを印加するため
のバイアス回路部で、マイクロ波阻止用のインダクタ5
とキャパシタ6とでなり、インダクタ5のインダクタン
ス値とキャパシタ6のキャパシタンス値とを各々所望の
値に設計することにより、バイアス電源端子7へのマイ
クロ波信号の漏洩を防止する。なお、4は前記バイアス
回路部3と前記FETIとの間に設けたマイクロ波回路
部である。
FIG. 3 is an equivalent circuit diagram of a commonly used MMIC. In this figure, 1 is a gallium arsenide field effect transistor (hereinafter abbreviated as FET) which is an active circuit part formed in the MMIC, 2 is a drain terminal of the FETI,
3 is a bias circuit section for applying a DC bias to the drain terminal 2, and includes an inductor 5 for blocking microwaves.
and a capacitor 6, and by designing the inductance value of the inductor 5 and the capacitance value of the capacitor 6 to desired values, leakage of the microwave signal to the bias power supply terminal 7 is prevented. Note that 4 is a microwave circuit section provided between the bias circuit section 3 and the FETI.

また、第4図は第3図のバイアス回路部3をMMIC上
に実現した場合の構造を示す表面バクーンの平面図であ
る。この図において、第3図と同一符号は同一部分を示
し、8は金属ブリッジ、9は上地電極、10は下地電極
、11は絶縁膜である。
Further, FIG. 4 is a plan view of a surface backplane showing the structure when the bias circuit section 3 of FIG. 3 is realized on an MMIC. In this figure, the same reference numerals as in FIG. 3 indicate the same parts, 8 is a metal bridge, 9 is an upper electrode, 10 is an underlayer electrode, and 11 is an insulating film.

すなわち、この構成では、半絶縁性砒化ガリウム基板上
に形成したループ状のインダクタ5と平行平板型のキャ
パシタ6とを電屏メッキ法などにより作製した金属ブリ
ッジ8により電気的に接続している。ここでキャパシタ
6は、K 地To t%となる上地電極9とバイアス電
源端子7に接続される下地電極10および上地電極9と
下地電極1゜に挟まれた絶縁膜11よりなるM I M
 (M etal −I n5ulator M et
al)[造となっている。
That is, in this configuration, a loop-shaped inductor 5 formed on a semi-insulating gallium arsenide substrate and a parallel plate type capacitor 6 are electrically connected by a metal bridge 8 manufactured by an electroplating method or the like. Here, the capacitor 6 is composed of an upper electrode 9 having a K ground To t%, a base electrode 10 connected to the bias power supply terminal 7, and an insulating film 11 sandwiched between the upper electrode 9 and the base electrode 1°. M
(M etal -I n5ulator M etal
al) [It is constructed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のような従来のMMICでは、寸法の大きなマイク
ロ波阻止用のインダクタ5とキャパシタ6とを各々個別
に構成しているために、MMICデツプに占めるバイア
ス回路部3の占有面積が著しく大きくなり、これがチッ
プ面積縮小の阻害要因ともなり、このため、ICの低価
格化が困難になるなどの問題点があった。
In the conventional MMIC as described above, since the microwave blocking inductor 5 and capacitor 6, which are large in size, are each configured separately, the area occupied by the bias circuit section 3 in the MMIC depth becomes significantly large. This becomes an impediment to reducing the chip area, and therefore poses problems such as making it difficult to reduce the price of the IC.

この発明ハ、かかる問題点を解決するためになされたも
ので、バイアス回路部の面積を縮小でき、その結果とし
て、MMICの高集積化2チツプ価格の低減を達成でき
るM M I Cje得ることを目的とする。
The present invention has been made to solve this problem, and aims to provide an MMIC which can reduce the area of the bias circuit section and, as a result, achieve a highly integrated 2-chip price reduction for the MMIC. purpose.

〔問題点を解決するための手段〕 この発明に係るMMICは、下地電極上に形成した絶縁
股上にインダクタを形成してバイアス回路部を構成した
ものである。
[Means for Solving the Problems] The MMIC according to the present invention has a bias circuit section formed by forming an inductor on an insulating layer formed on a base electrode.

〔作用〕[Effect]

この発明においては、インダクタと下地電極間にキャパ
シタが形成される。
In this invention, a capacitor is formed between the inductor and the base electrode.

〔実施例〕〔Example〕

第1図はこの発明のMMICのバイアス回路部の一実施
例を示す斜視図である。この図において、第4図と同一
符号は同一部分を示し、12ば前記マイクロ波回路゛部
4に接続される端子、13ばバイアス電源端子7に接続
される端子である。
FIG. 1 is a perspective view showing an embodiment of a bias circuit section of an MMIC according to the present invention. In this figure, the same reference numerals as in FIG.

すなわち、この発明ではインダクタ5が下地電極1o上
に連続して被着形成された絶縁膜11上に形成されてい
るため、インダクタ5と下地電極10との間に容量が形
成される。このため、バイアス回路部の面積の縮小が可
能となる。
That is, in the present invention, since the inductor 5 is formed on the insulating film 11 that is continuously deposited on the base electrode 1o, a capacitance is formed between the inductor 5 and the base electrode 10. Therefore, it is possible to reduce the area of the bias circuit section.

この場合、インダクタ5を形成するループ状の金属パー
タンと下地電極10との間の単位インダクタ長さあたり
の結合容量CI とインダクタンス値り、を用いて、バ
イアス回路部は第2図の等価回路図に示すように近似的
に表されろ。
In this case, the bias circuit section is constructed using the coupling capacitance CI per unit inductor length and the inductance value between the loop-shaped metal pattern forming the inductor 5 and the base electrode 10, as shown in the equivalent circuit diagram of FIG. Express it approximately as shown in .

一般に結合容量C,は絶縁膜11の材料および膜厚によ
って、また、インダクタンス値L1は、インダクタ5を
形成するループ状の金属の線幅W。
In general, the coupling capacitance C, depends on the material and film thickness of the insulating film 11, and the inductance value L1 depends on the line width W of the loop-shaped metal forming the inductor 5.

線間隔り、ターン数nによって各々決定することが可能
で、結合容量CXおよびインダクタンス値L1を所望値
に設定することにより、端子12より電源回路側をみた
動作周波数帯域における電力反射係数をほとんど1に設
計することができる。
Each can be determined by the line spacing and the number of turns n, and by setting the coupling capacitance CX and the inductance value L1 to desired values, the power reflection coefficient in the operating frequency band viewed from the terminal 12 to the power supply circuit side can be reduced to almost 1. can be designed.

すなわち、バイアス回路をマイクロ波阻止回路として使
用することができる。
That is, the bias circuit can be used as a microwave blocking circuit.

なお、上記実施例では、FETのドレイン電圧印加用の
バイアス回路部について説明したが、ゲート電圧印加用
、あるいはダイオードなどの他のMMICの能動回路用
のバイアス回路部として用いても同様の効果を秦するこ
とはいうまでもない。
In the above embodiment, the bias circuit section for applying the drain voltage of the FET was explained, but the same effect can be obtained even if it is used as the bias circuit section for applying the gate voltage or for the active circuit of other MMICs such as a diode. It goes without saying that it would become Qin.

また、上記実施例では、インダクタとしてループ状のイ
ンダクタを用いる場合について示したが、メアンダ型の
インダクタや棒状のインダクタを適用してもよいことは
いうまでもない。
Further, in the above embodiment, a loop-shaped inductor is used as the inductor, but it goes without saying that a meander-shaped inductor or a rod-shaped inductor may be used.

〔発明の効果〕〔Effect of the invention〕

この発明は以上説明したとおり、下地電極上に形成した
絶縁膜上にインダクタを形成してバイアス回路部を構成
したので、ICチップを集積化でき、その結果、チップ
価格を安価にできろという効果がある。
As explained above, this invention has the effect of forming a bias circuit section by forming an inductor on an insulating film formed on a base electrode, so that IC chips can be integrated, and as a result, the chip price can be reduced. There is.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明のMMICのバイアス回路部の一実施
例を示す斜視図、第2図はこの発明によるバイアス回路
部の等価回路図、第3図は従来のMMICの等価回路図
、第4図は従来のバイアス回路部の構成を示す平面図で
ある。 図において、5はインダクタ、8は金属ブリッジ、10
は下地電極、11は絶縁膜、12.13は端子である。 なお、各図中の同一符号は同一または相当部分を示す。 代理人 大 岩 増 1a(外2名) 第1図 第2図 第3図 第4図
1 is a perspective view showing an embodiment of the bias circuit section of an MMIC according to the present invention, FIG. 2 is an equivalent circuit diagram of the bias circuit section according to the present invention, FIG. 3 is an equivalent circuit diagram of a conventional MMIC, and FIG. The figure is a plan view showing the configuration of a conventional bias circuit section. In the figure, 5 is an inductor, 8 is a metal bridge, 10
11 is a base electrode, 11 is an insulating film, and 12.13 is a terminal. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masu Oiwa 1a (2 others) Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] インダクタとキャパシタとからなるバイアス回路部を備
えたモノリシック化マイクロ波集積回路において、下地
電極上に形成した絶縁膜上に前記インダクタを形成して
前記バイアス回路部を構成したことを特徴とするモノリ
シック化マイクロ波集積回路。
A monolithic microwave integrated circuit comprising a bias circuit section consisting of an inductor and a capacitor, characterized in that the bias circuit section is configured by forming the inductor on an insulating film formed on a base electrode. Microwave integrated circuit.
JP19421886A 1986-08-19 1986-08-19 Monolithick microwave integrated circuit Pending JPS6348855A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19421886A JPS6348855A (en) 1986-08-19 1986-08-19 Monolithick microwave integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19421886A JPS6348855A (en) 1986-08-19 1986-08-19 Monolithick microwave integrated circuit

Publications (1)

Publication Number Publication Date
JPS6348855A true JPS6348855A (en) 1988-03-01

Family

ID=16320917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19421886A Pending JPS6348855A (en) 1986-08-19 1986-08-19 Monolithick microwave integrated circuit

Country Status (1)

Country Link
JP (1) JPS6348855A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01223758A (en) * 1988-03-02 1989-09-06 Mitsubishi Electric Corp Monolithic microwave integrated circuit
US4959705A (en) * 1988-10-17 1990-09-25 Ford Microelectronics, Inc. Three metal personalization of application specific monolithic microwave integrated circuit
US5233310A (en) * 1991-09-24 1993-08-03 Mitsubishi Denki Kabushiki Kaisha Microwave integrated circuit
US5557138A (en) * 1993-11-01 1996-09-17 Ikeda; Takeshi LC element and semiconductor device
WO2010064412A1 (en) * 2008-12-04 2010-06-10 日本電気株式会社 Bias circuit and method for making bias circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01223758A (en) * 1988-03-02 1989-09-06 Mitsubishi Electric Corp Monolithic microwave integrated circuit
US4959705A (en) * 1988-10-17 1990-09-25 Ford Microelectronics, Inc. Three metal personalization of application specific monolithic microwave integrated circuit
US5233310A (en) * 1991-09-24 1993-08-03 Mitsubishi Denki Kabushiki Kaisha Microwave integrated circuit
US5557138A (en) * 1993-11-01 1996-09-17 Ikeda; Takeshi LC element and semiconductor device
WO2010064412A1 (en) * 2008-12-04 2010-06-10 日本電気株式会社 Bias circuit and method for making bias circuit
US8975725B2 (en) 2008-12-04 2015-03-10 Nec Corporation Bias circuit and method of manufacturing the same

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