JPS5846571Y2 - High frequency circuit equipment - Google Patents
High frequency circuit equipmentInfo
- Publication number
- JPS5846571Y2 JPS5846571Y2 JP16772379U JP16772379U JPS5846571Y2 JP S5846571 Y2 JPS5846571 Y2 JP S5846571Y2 JP 16772379 U JP16772379 U JP 16772379U JP 16772379 U JP16772379 U JP 16772379U JP S5846571 Y2 JPS5846571 Y2 JP S5846571Y2
- Authority
- JP
- Japan
- Prior art keywords
- dielectric substrate
- transmission line
- high frequency
- frequency circuit
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Waveguides (AREA)
- Microwave Amplifiers (AREA)
Description
【考案の詳細な説明】
本考案は高周波回路装置、特に金属基体上に載置された
半導体装置と、該半導体装置をはさむ位置に配置された
誘電体基板および該誘電体基板上に形成された伝送線路
電極を有する1対のストリップ線路とを具備した高周波
回路装置に関する。[Detailed Description of the Invention] The present invention relates to a high-frequency circuit device, particularly a semiconductor device mounted on a metal substrate, a dielectric substrate placed between the semiconductor devices, and a device formed on the dielectric substrate. The present invention relates to a high frequency circuit device including a pair of strip lines having transmission line electrodes.
近隼、ガリウム砒素電界効果トランジスタ(GaAsF
ET)などのマイクロ波半導体素子の特性の飛躍的な向
上を背景としてマイクロ波帯(IGHz〜20GHz)
の広帯域低雑音増幅器、高出力直線増幅器などが実用化
されるようになった。Kin Hayabusa, gallium arsenide field effect transistor (GaAsF
Due to the dramatic improvement in the characteristics of microwave semiconductor devices such as ET), the microwave band (IGHz to 20GHz)
Wideband low-noise amplifiers and high-output linear amplifiers have come into practical use.
これらの増幅器はマイクロストリップ線路とFETやト
ランジスタダイオードなどの能動素子とり、C,Rの受
動素子で構成されたいわゆるマイクロ波集積回路を用い
ている。These amplifiers use a so-called microwave integrated circuit composed of a microstrip line, active elements such as FETs and transistor diodes, and C and R passive elements.
例えば従来のマイクロストリップ線路とFETの接続部
の構造は第1図に示される。For example, the structure of a conventional connection between a microstrip line and an FET is shown in FIG.
このようなマイクロ波増幅器では入出力間の帰還容量が
大きいと発振したり、利得が低下したりする。In such a microwave amplifier, if the feedback capacitance between the input and output is large, oscillation may occur or the gain may decrease.
特に広帯域増幅器や直線増幅器で周波数が高くなると(
例えばKuバンド12〜20 GHz)この影響が大き
い。Especially when the frequency increases with wideband amplifiers and linear amplifiers (
For example, Ku band 12 to 20 GHz) This influence is large.
つまり、図において表面に金メッキを施こした銅から成
る金属基体1上に半導体装置、例えばFETチップ2と
、誘電体基板3,3′およびその上に形成された伝送線
路電極4,4′を有する1対のストノツプ線路が設けら
れている高周波回路装置においては、電極4,4′の対
向部において入出力間の帰還容量が生じる。That is, in the figure, a semiconductor device, for example, an FET chip 2, a dielectric substrate 3, 3', and transmission line electrodes 4, 4' formed thereon are mounted on a metal substrate 1 made of copper whose surface is plated with gold. In a high frequency circuit device provided with a pair of stop line lines, a feedback capacitance occurs between input and output at the opposing portions of electrodes 4 and 4'.
そこで、この帰還容量を低減するために第2図に示す構
造が採用されている。Therefore, in order to reduce this feedback capacitance, the structure shown in FIG. 2 is adopted.
この構造は、金属基体1に突起部21を設けたものであ
り、ある程度帰還容量を低減させることができる。This structure is one in which a protrusion 21 is provided on the metal base 1, and the feedback capacitance can be reduced to some extent.
本考案はこの帰還容量をより小さくすることによって、
さらに高信波の信号を扱う高周波回路装置を提供するこ
とを目的とする。By making this feedback capacitance smaller, the present invention
A further object of the present invention is to provide a high frequency circuit device that handles high frequency signals.
このような本考案の特徴は、金属基体」二に載置された
半導体装置と、該半導体装置をはさむ位置に配置された
誘電体基板および該誘電体基板上に形成された伝送線路
電極を有する1対のストリップ線路とを具備した高周波
回路装置において、該1対のストリップ線路が対向する
部分において、該伝送線路電極の幅を該半導体装置の方
向に漸次小さくせしめると共に、該誘電体基板の厚さも
該伝送線路電極の幅と該誘電体基板の厚さとが一定の比
率となるように漸次小さくせしめたことにある。The present invention is characterized by having a semiconductor device mounted on a metal substrate, a dielectric substrate disposed to sandwich the semiconductor device, and a transmission line electrode formed on the dielectric substrate. In a high frequency circuit device comprising a pair of strip lines, the width of the transmission line electrode is gradually reduced in the direction of the semiconductor device in the portion where the pair of strip lines face each other, and the thickness of the dielectric substrate is gradually reduced. This is because the width of the transmission line electrode and the thickness of the dielectric substrate are gradually reduced so that they become a constant ratio.
以下、図面に用いて本考案の一実施例を説明する。An embodiment of the present invention will be described below with reference to the drawings.
第3図は本考案の一実施例を示す斜視図である。FIG. 3 is a perspective view showing an embodiment of the present invention.
図に示されるように、1対のストリップ線路が対向する
部分において、伝送線路電極4,4′の幅がFETチッ
プ2の方向に漸次小さくなっている。As shown in the figure, the width of the transmission line electrodes 4, 4' gradually decreases in the direction of the FET chip 2 at the portion where the pair of strip lines face each other.
また、これと共に誘電体基板の厚さも伝送線路電極の幅
と誘電体基板の厚さの比が一定となるように漸次小さく
しである。In addition, the thickness of the dielectric substrate is also gradually reduced so that the ratio of the width of the transmission line electrode to the thickness of the dielectric substrate becomes constant.
このようにして伝送線路電極4,4′の対向する面積を
小さくすることにより帰還容量を小さくすることか゛で
きる。In this way, by reducing the opposing areas of the transmission line electrodes 4, 4', the feedback capacitance can be reduced.
また、電極の幅を小さくした部分の誘電体基板の厚さを
小さくすることにより、ストリップ線路の特性インピー
ダンスを一定に保つことができる。Further, by reducing the thickness of the dielectric substrate in the portion where the electrode width is reduced, the characteristic impedance of the strip line can be kept constant.
具体的には図において、Wo=0.6mm、W1=0.
1mm、 t o=0.6 mm、、 t 、=Q、l
mm、従って電極の幅と誘電体基板の厚さの比はlと
した。Specifically, in the figure, Wo=0.6mm, W1=0.
1 mm, t = 0.6 mm, t , = Q, l
mm, and therefore the ratio of the width of the electrode to the thickness of the dielectric substrate was 1.
また電極間隔d=0.5mm、誘電体基板3,3′とし
て比誘電率ε、=9.6のアルミナ(Al□03)基板
を用いたところ、帰還容量は0.001PFとなった。Further, when the electrode spacing d=0.5 mm and alumina (Al□03) substrates with a dielectric constant ε=9.6 were used as the dielectric substrates 3 and 3', the feedback capacitance was 0.001PF.
同様の寸法、材料を用いた場合、帰還容量は本考案の様
に電極幅にテーパをつけない第1図の構造では0.01
PF、第2図の構造では0.006PFであり、本考案
の構造により、帰還容量が充分低減させ得ることが明ら
かとなった。When similar dimensions and materials are used, the feedback capacitance is 0.01 in the structure shown in Figure 1 in which the electrode width is not tapered as in the present invention.
The PF was 0.006PF in the structure shown in FIG. 2, and it became clear that the structure of the present invention could sufficiently reduce the feedback capacitance.
ただしいずれの場合も、ストリップ線路の特性インピー
ダンスは50J7である。However, in either case, the characteristic impedance of the strip line is 50J7.
第4図は、本考案の他の実施例を示す斜視図である。FIG. 4 is a perspective view showing another embodiment of the present invention.
第3図の実施例では、誘電体基板の上面にテーパをつけ
たが、本実施例では誘電基板の下面にテーパをつけた。In the embodiment shown in FIG. 3, the upper surface of the dielectric substrate was tapered, but in this embodiment, the lower surface of the dielectric substrate was tapered.
これにより、第3図の実施例よりも電極パターンの形成
を容易にすることができる。Thereby, the formation of the electrode pattern can be made easier than in the embodiment shown in FIG.
以上説明したように本考案によれば、帰還容量を小さく
することか゛できるので、高周波回路装置において不要
な発振や、利得の低下を防止することができる。As explained above, according to the present invention, it is possible to reduce the feedback capacitance, thereby preventing unnecessary oscillation and decrease in gain in a high frequency circuit device.
第1図及び第2図は従来の高周波回路装置を示す斜・視
図、第3図は本考案による高周波回路装置の一実施例を
示す斜視図、第4図は本考案の他の実施例を示す斜視図
である。
図において、1は金属基体、2はFETチップ(半導体
装置)、3,3′は誘電体基板、4,4′は伝送線路電
極を示す。1 and 2 are perspective and perspective views showing a conventional high frequency circuit device, FIG. 3 is a perspective view showing an embodiment of the high frequency circuit device according to the present invention, and FIG. 4 is a perspective view showing another embodiment of the present invention. FIG. In the figure, 1 is a metal base, 2 is an FET chip (semiconductor device), 3 and 3' are dielectric substrates, and 4 and 4' are transmission line electrodes.
Claims (1)
はさむ位置に配置された誘電体基体および該誘電体基板
上に形成された伝送線路電極を有する1対のストリップ
線路とを具備した高周波回路装置において、該1対のス
トリップ線路が対向する部分において、該伝送線路電極
の幅を該半導体装置の方向に漸次小さくせしめると共に
、該誘電体基板の厚さも該伝送線路電極の幅と該誘電体
基板の厚さとが一定の比率となるように漸次小さくせし
めたことを特徴とする高周波回路装置。A high frequency device comprising a semiconductor device mounted on a metal substrate, a dielectric substrate disposed to sandwich the semiconductor device, and a pair of strip lines having transmission line electrodes formed on the dielectric substrate. In the circuit device, in a portion where the pair of strip lines face each other, the width of the transmission line electrode is gradually decreased in the direction of the semiconductor device, and the thickness of the dielectric substrate is also equal to the width of the transmission line electrode and the dielectric substrate. 1. A high-frequency circuit device characterized in that the thickness of the body substrate is gradually reduced to a certain ratio.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16772379U JPS5846571Y2 (en) | 1979-12-04 | 1979-12-04 | High frequency circuit equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16772379U JPS5846571Y2 (en) | 1979-12-04 | 1979-12-04 | High frequency circuit equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5685415U JPS5685415U (en) | 1981-07-09 |
JPS5846571Y2 true JPS5846571Y2 (en) | 1983-10-24 |
Family
ID=29678571
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16772379U Expired JPS5846571Y2 (en) | 1979-12-04 | 1979-12-04 | High frequency circuit equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5846571Y2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7171618B2 (en) | 2018-10-05 | 2022-11-15 | 株式会社東芝 | Grounding structure for high-frequency circuit boards |
-
1979
- 1979-12-04 JP JP16772379U patent/JPS5846571Y2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5685415U (en) | 1981-07-09 |
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