JPS6053089A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6053089A JPS6053089A JP16141483A JP16141483A JPS6053089A JP S6053089 A JPS6053089 A JP S6053089A JP 16141483 A JP16141483 A JP 16141483A JP 16141483 A JP16141483 A JP 16141483A JP S6053089 A JPS6053089 A JP S6053089A
- Authority
- JP
- Japan
- Prior art keywords
- microstrip line
- metallized layer
- line
- matching circuit
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 6
- 239000004020 conductor Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000005540 biological transmission Effects 0.000 claims abstract description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 9
- 238000001465 metallisation Methods 0.000 claims description 6
- 230000005672 electromagnetic field Effects 0.000 abstract description 2
- 238000007747 plating Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は半導体装置に関し、特に半絶縁性ヒ化ガリウム
基板上に形成された小型化の進んだマイクロ波モノリシ
ック集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a semiconductor device, and more particularly to a miniaturized microwave monolithic integrated circuit formed on a semi-insulating gallium arsenide substrate.
ヒ化ガリウム基板上に、例えば従来のへｆｆ１ｓ ＦＥ
Ｔ構造を有する能動素子と、受動素子とを形成したマイ
クロ波モノリシック集積回路（以下ＮＭＩＣと記す）は
、ヒ化ガリウムの高電子移動度に起因する良好な高周波
特性を有し、又、低コスト化の見地から特に数ＧＨｚ以
上の超高周波領域において期待されている。For example, conventional ff1s FE on a gallium arsenide substrate
Microwave monolithic integrated circuits (hereinafter referred to as NMICs) in which active elements and passive elements having a T structure are formed have good high-frequency characteristics due to the high electron mobility of gallium arsenide, and are low-cost. From the viewpoint of technology, it is particularly expected in the ultra-high frequency region of several GHz or more.
従来、上記ＭＭＩＣにおいては、外部回路との接続のた
め、整合回路が必要であり、該整合回路は半絶縁性ヒ化
ガリウム基板上に形成されたマイクロストリップライン
で構成されている。上記マイクロストリップラインは、
半絶縁性ヒ化ガリウム基板（以下単に基板と記す）裏面
に蒸着等の方法で形成された金属化層を接地導体として
いる。所要特性インピーダンスを与えるマイクロストリ
ップラインの幅は基板厚さにはぼ比例する。例えば、特
性インピーダンスが５００の場合、ヒ化ガリウム基板の
比誘電率は約１２．５であるからマイクロストリップラ
イン幅はほぼ基板厚さに等しくなる。Conventionally, the MMIC described above requires a matching circuit for connection with an external circuit, and the matching circuit is composed of a microstrip line formed on a semi-insulating gallium arsenide substrate. The above microstrip line is
A metallized layer formed on the back surface of a semi-insulating gallium arsenide substrate (hereinafter simply referred to as the substrate) by a method such as vapor deposition is used as a ground conductor. The width of the microstrip line that provides the required characteristic impedance is approximately proportional to the substrate thickness. For example, when the characteristic impedance is 500, the dielectric constant of the gallium arsenide substrate is about 12.5, so the microstrip line width is approximately equal to the substrate thickness.
従って、基板厚さが固定されると、ストリップライン幅
は、特性インピーダンスの値に応じて一意に定まり、小
型化し得がい。Therefore, when the substrate thickness is fixed, the stripline width is uniquely determined according to the value of characteristic impedance, which facilitates miniaturization.
更に、上記ＡＩＭＩＣ内整合回路において、マイクロス
トリップライン間の不必要な干渉を妨ぐためマイクロス
トリップライン同士の間隔は、可能な限９広くとる必要
があり−１０ｄＢ以下の結合度に抑えるには最低ライン
幅の３倍程度は必要である。Furthermore, in the matching circuit in the AIMIC mentioned above, in order to prevent unnecessary interference between microstrip lines, it is necessary to make the spacing between the microstrip lines as wide as possible. Approximately three times the line width is required.
上記２つの理由により、従来のＭＭＩＣ内整合回路の面
積は大きくチップサイズの低減による低コスト化実現へ
の大きな妨げとなっていた。従って、チップサイズの低
減による低コスト化の実現、或いは、例えば、マイクロ
液受信器′ｆ：構成する低雑音増幅器と、局部発振器と
、周波数変換器とを同一チップに収納するような、高集
積化を実現するためには、上記整合回路の小型化は不可
欠である。For the above two reasons, the area of the conventional matching circuit in the MMIC is large, which is a major hindrance to realizing cost reduction by reducing the chip size. Therefore, it is possible to realize cost reduction by reducing the chip size, or to achieve high integration, for example, by accommodating the low-noise amplifier, local oscillator, and frequency converter constituting the micro-liquid receiver'f on the same chip. In order to achieve this, it is essential to downsize the matching circuit.
しかしながら、従来構造によれば、上述の２つの理由に
より、整合回路の小型化は不可能であることは明らかで
ある。However, it is clear that according to the conventional structure, it is impossible to miniaturize the matching circuit due to the above two reasons.
〔発明の目的〕
本発明の目的は、従来の問題点を解決し、製造工程を変
更することなく、上記整合回路の小型化を容易に実現し
、安価な超高周波用の半導体装置を提供することにある
。[Object of the Invention] An object of the present invention is to solve the conventional problems, easily realize miniaturization of the above-mentioned matching circuit without changing the manufacturing process, and provide an inexpensive ultra-high frequency semiconductor device. There is a particular thing.
本発明の半導体装置は、半絶縁性ヒ化ガリウム基板の一
生表面上に形成され、かつ、接地導体と同電位を有する
第一の金属化層と、該金属化層の一生表面上に形成され
た誘電体層と、上記誘電体層の一生表面上に選択的に形
成された第二の金属化層から成る伝送線路を含んで構成
される整合回路を有することにより構成される。The semiconductor device of the present invention includes a first metallized layer formed on the surface of a semi-insulating gallium arsenide substrate and having the same potential as a ground conductor, and a first metallized layer formed on the surface of the metallized layer. A matching circuit comprising a transmission line comprising a dielectric layer and a second metallization layer selectively formed on the surface of the dielectric layer.
以下、本発明の実施例について、図面を参照して説明す
る。Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明を適用したマイクロ波モノリ／ツク集積
回路の一実施例のチップの平面図、第２図は第１図に示
す一実施例のＡ−Ａ’断ｉｎｊ図である。FIG. 1 is a plan view of a chip of an embodiment of a microwave monolithic integrated circuit to which the present invention is applied, and FIG. 2 is a sectional view taken along line AA' of the embodiment shown in FIG.
ｇ１図及び第２図において、半絶縁性ヒ化ガリウム基板
１６上には選択イオン注入等の方法にてＭＥＳＩ”ＥＴ
の活性層が形成されている。該ＦＥＴのゲート電極ｌ及
び入プ〕整合回路接地導体４及び出力整合回路接地導体
５とは、全面蒸着及び選択エツチング等の方法で第一の
金属化層から同時に形成されている又、ドレイン電極３
は高インピーダンスライン１（１’経て、ドレインノく
イアス用ポンディングパッド１２と接続され、該ドレイ
ン電極からのマイクロ波出力はマイクロストリ・ノブラ
イン７にて構成される出力整合回路を経て、出力ボンデ
ィングバ・ラド１４より外部回路へ供給される。更に、
ゲート電極１はスルーホールコンタクト構成される入力
整合回路を介して入力ボンディングパッド１３と接続さ
れる。又、ゲーしくイアスボンディングバツド１１は高
インピーダンスライン９によりゲート電極１と接耕され
ている。更に、ソース電極２は接地用ポンプイングツく
ラドをも兼ねており、スルーホールコンタクトｉＢ ８
により整合回路接地２ｒ１．体４及び５と接続されてい
る。In FIG. g1 and FIG.
An active layer is formed. The gate electrode 1, the input matching circuit ground conductor 4, and the output matching circuit ground conductor 5 of the FET are simultaneously formed from the first metallization layer by a method such as full-surface vapor deposition and selective etching. 3
is connected to the bonding pad 12 for the drain electrode through the high impedance line 1 (1'), and the microwave output from the drain electrode is connected to the output bonding pad 12 through the output matching circuit composed of the microstrip knob line 7. - Supplied from the RAD 14 to the external circuit.Furthermore,
Gate electrode 1 is connected to input bonding pad 13 via an input matching circuit configured with through-hole contacts. Furthermore, the earth bonding pad 11 is connected to the gate electrode 1 by a high impedance line 9. Furthermore, the source electrode 2 also serves as a ground pumping pad and has a through-hole contact iB8.
Matching circuit grounding 2r1. It is connected to bodies 4 and 5.
なお、入力端を主にして説明すると、第一金属化層より
なる整合回路接地導体４形成後に全面スパッタ及び選択
エツチング等の方法で誘電体層Ｊ５が形成され、更に、
選択メッキ等により形成された第二の金，ｍ化層よりな
るＦ Ｅ Ｔソース電極を兼ねる接地パッド２と、高イ
ンピーダンスライン９及ヒマイクロストリツプライン６
とが同時に形成されている。すなわち、マイクロストリ
ップラインは第一の金属化層の整合回路接地導体４と、
その上に形成された誘電体層１５と、更に誘電体層１５
上に選択的に形成された第２の金属化層６により構成さ
れている。以上のように、整合回路接地導体４及び５は
ゲート電極と同一工程で形成されるため、本実施例の工
程は従来のＭＭＩＣ製造工程と全く同様である。更に、
銹電体Ｍ１５の膜厚は任意に運屋することができ、しか
も基板１６の厚さよりも格段に薄くし得る。従って、本
構造に依れば、所要特性インピーダンスを得るために必
要なマイクロストリップライン幅は従来構造に比較し格
段に縮小し得る。しかも、マイクロストリップラインか
ら周囲空間に拡がる電磁界の広がりも、接地導体との距
離にほぼ比例するため、本実流側の構で３によれば、ラ
イン同士の不必要な結合を防ぐだめのライン間隔も、従
来構造に比較して大幅に減少できる。In addition, mainly explaining the input end, after forming the matching circuit ground conductor 4 made of the first metallized layer, a dielectric layer J5 is formed by a method such as whole surface sputtering and selective etching, and further,
A grounding pad 2 which also serves as a FET source electrode made of a second gold, metal layer formed by selective plating or the like, a high impedance line 9 and a microstrip line 6.
are formed at the same time. That is, the microstrip line has a matching circuit ground conductor 4 of the first metallization layer;
Dielectric layer 15 formed thereon, and further dielectric layer 15
It is constituted by a second metallization layer 6 selectively formed on top. As described above, since the matching circuit ground conductors 4 and 5 are formed in the same process as the gate electrode, the process of this embodiment is completely similar to the conventional MMIC manufacturing process. Furthermore,
The film thickness of the electric conductor M15 can be adjusted arbitrarily, and can be made much thinner than the thickness of the substrate 16. Therefore, according to this structure, the microstrip line width required to obtain the required characteristic impedance can be significantly reduced compared to the conventional structure. Moreover, the spread of the electromagnetic field that spreads from the microstrip line into the surrounding space is also approximately proportional to the distance from the ground conductor. Line spacing can also be significantly reduced compared to conventional structures.
以上説明したように、本発明によれ１＝： 、整合回路
の小型化が容易に丈現され、力）つ工程を増加せしめる
こともない。従って、マイクロ仮モノリンツク集積回路
の小型化による低コスト化及び高集積化を容易に達り兄
することができる。又、本発明は、入出力に整合回路を
必要とするモノリシックマイクロ波周波数変換器及びモ
ノリシックマイクロ波発振器を始め、他の半涜′体装ｂ
１にも有効である。As explained above, according to the present invention, the matching circuit can be easily miniaturized without increasing the number of steps. Therefore, it is possible to easily achieve lower costs and higher integration by miniaturizing the micro temporary monolink integrated circuit. The present invention also applies to monolithic microwave frequency converters and monolithic microwave oscillators that require matching circuits for input and output, as well as other semi-obscure systems.
It is also effective for 1.
第１図は本発明の一実施例によるマイクロ波モノリンツ
ク集’ＡＷ回路の平面図、第２図は？ｊｒ、■図に示す
一実Ｊｆａ例の断面図である。
■・・・・・・ゲート電極、２・・・・・・接地用パッ
ドを兼ねたソース電極、３・・・・・・ドレイン電極、
４・・・・・・入力整合回路接地導体、５・・・・・・
出力整合回路接地導体、６・・・・・・入力整合回路マ
イクロマトリツブライン、７・・・・・・出力整合回路
マイクロストリップライン、８・・・・・・スルーホー
ルコンタクト、９・・・・・・ケートバイアス用甚イン
ピーダンスライン、ｌＯ・・・・・・ドレインバイアス
用品インピーダンスライン、１１・・・・・・ゲートバ
イアス用ボンディングバンド、１２・・・・・・ドレイ
ンバイアス用ボンゲイングバラド、１３・・・・・・入
力用ポンディングパッド、１４・・・・・・出力用ポン
ディングパッド、１５・・−・・ｕｋ体層、１６・・・
・・・半絶縁性ヒ化ガリウム基板。
代理人 弁理士 内 原 晋Fig. 1 is a plan view of a microwave monolink collection'AW circuit according to an embodiment of the present invention, and Fig. 2 is a plan view of a microwave monolink collection'AW circuit according to an embodiment of the present invention. jr, is a cross-sectional view of an example of one actual Jfa shown in the figure. ■...Gate electrode, 2...Source electrode that also serves as a grounding pad, 3...Drain electrode,
4... Input matching circuit grounding conductor, 5...
Output matching circuit ground conductor, 6...Input matching circuit micromatrix line, 7...Output matching circuit microstrip line, 8...Through hole contact, 9... . . . High impedance line for gate bias, lO . . . Impedance line for drain bias supplies, 11 . . . Bonding band for gate bias, 12 . . . Bonding band for drain bias, 13... Input bonding pad, 14... Output bonding pad, 15... UK body layer, 16...
...Semi-insulating gallium arsenide substrate. Agent Patent Attorney Susumu Uchihara
Claims (1)
つ接地導体と同電位を有する第一の金属化層と、該第−
の金属化層の一生表面上に形成された誘電体層と、該誘
電体層の一生表面上に選択的に形成された第二の金属化
層とから成る伝送線路を含んで（１り成される整合回路
を有することを特徴とする半導体装置。a first metallization layer formed on the surface of the semi-insulating gallium arsenide substrate and having the same potential as the ground conductor;
a transmission line comprising a dielectric layer formed on the surface of a metallized layer and a second metallization layer selectively formed on the surface of the dielectric layer; A semiconductor device characterized by having a matching circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16141483A JPS6053089A (en) | 1983-09-02 | 1983-09-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16141483A JPS6053089A (en) | 1983-09-02 | 1983-09-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6053089A true JPS6053089A (en) | 1985-03-26 |
Family
ID=15734641
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16141483A Pending JPS6053089A (en) | 1983-09-02 | 1983-09-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6053089A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60249374A (en) * | 1984-05-24 | 1985-12-10 | Mitsubishi Electric Corp | Field effect ultrahigh frequency transistor device |
| JPS63292701A (en) * | 1987-05-25 | 1988-11-30 | A T R Koudenpa Tsushin Kenkyusho:Kk | Passive circuit device for microwave integrated circuit |
| JPH02120839U (en) * | 1989-03-16 | 1990-09-28 | ||
| JPH0637119A (en) * | 1992-03-17 | 1994-02-10 | Toshiba Corp | Compound semiconductor integrated circuit |
| WO2010054685A1 (en) * | 2008-11-12 | 2010-05-20 | Telefonaktiebolaget Lm Ericsson (Publ) | An improved large area photo detector |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5892270A (en) * | 1981-11-27 | 1983-06-01 | Mitsubishi Electric Corp | Gaas microwave monolithic integrated circuit device |
-
1983
- 1983-09-02 JP JP16141483A patent/JPS6053089A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5892270A (en) * | 1981-11-27 | 1983-06-01 | Mitsubishi Electric Corp | Gaas microwave monolithic integrated circuit device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60249374A (en) * | 1984-05-24 | 1985-12-10 | Mitsubishi Electric Corp | Field effect ultrahigh frequency transistor device |
| JPS63292701A (en) * | 1987-05-25 | 1988-11-30 | A T R Koudenpa Tsushin Kenkyusho:Kk | Passive circuit device for microwave integrated circuit |
| JPH02120839U (en) * | 1989-03-16 | 1990-09-28 | ||
| JPH0637119A (en) * | 1992-03-17 | 1994-02-10 | Toshiba Corp | Compound semiconductor integrated circuit |
| WO2010054685A1 (en) * | 2008-11-12 | 2010-05-20 | Telefonaktiebolaget Lm Ericsson (Publ) | An improved large area photo detector |
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