JPS60233911A - Monolithic amplifier - Google Patents
Monolithic amplifierInfo
- Publication number
- JPS60233911A JPS60233911A JP8968784A JP8968784A JPS60233911A JP S60233911 A JPS60233911 A JP S60233911A JP 8968784 A JP8968784 A JP 8968784A JP 8968784 A JP8968784 A JP 8968784A JP S60233911 A JPS60233911 A JP S60233911A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- lower electrode
- electrode
- substrate
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 239000003990 capacitor Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 4
- 238000003486 chemical etching Methods 0.000 abstract description 3
- 239000004020 conductor Substances 0.000 abstract description 3
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 239000000956 alloy Substances 0.000 abstract description 2
- 238000007747 plating Methods 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Microwave Amplifiers (AREA)
- Amplifiers (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はモノリシック増幅器に関し、くわしくはＲＦＶ
Ｍ−ト用キャパシタの下部電極に対して設けた貫通孔に
より接地を行ない、チップの小形化をはかっ九屹ノリシ
ック増幅器圧関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a monolithic amplifier, and in particular to an RFV amplifier.
A through hole provided in the lower electrode of the M-total capacitor is used for grounding, thereby reducing the size of the chip.
近来、超高周波半導体トランジスタにりいて、単体レベ
ルから整合回路やバイアス回路をも半導体基板上に一体
構成し、大量生産によシ低価格化を目指したモノリシッ
ク増幅器が注目され、その研究が盛んである。超高周波
帯で動作するモノリシック増幅器においては、回路整合
等に影響を及はさない様に能動素子およびバイアス回路
の接地を取る事が重要となる。従来、モノリシック増幅
器に対する接地はチップ内任意の位置に接地領域を設け
、一方接地インダクタンスも低減される事から、半導体
基板に貫通孔、いわゆるバイアホールを設け、該貫通孔
の内面及び半導体基板の裏面の範囲で導体金属を被着せ
しめて接地を取る事がなされていた。この様なバイアホ
ール構造により接地を取る従来のモノリシック増幅器は
、実際にはマイクロウェーブ・ジャーナＩＬＩ誌１９８
１年３月号に掲載されているり、 Ｒ，ＣＨＥＮらの論
文に掲載されておシ、その構造は第１図に示すように１
半導体基板１１の表面上にトランジスタのソース領域１
２およびバイアス回路ＲＦ Ｓ’ ！ｌ −）用キャパ
シタ１４の下部電極１８から取シ出したアース領域１５
に対して半導体基板１１に裏面よル貫通孔１６を化学エ
ッチングによって開け、該貫通孔１６の内面に導体金属
１７を被着してこれをアース領域１５Ｊｌｃ結合すると
とＫよシ、半導体基板１１の裏面と導通を取）、これを
接地面としていた。しかしながら、従来のこのようなア
ース領域１５に対してバイアホーμにより接地を取るモ
ノリシック増幅器忙おいては、まず、化学エツチングに
よシ貫通孔１６を開けた場合には深さ、方向のエツチン
グ量がサイドエツチング量と同等となシ、例えば半導体
基板の厚さが１５０１ｍｓの場合Ｋｕ、裏面面積は３０
０μｍ角以上を必要とし、一方、ＲＦ Ｓ／ ｇ−）用
キャパシタとしてはＸ帯の周波数では４ｆ以上（インピ
ーダンスは１８ ＧＨｚにおいて、８．８２０）の容量
を必要とし、その時、誘電体に５ＩＯｓを用いたとして
、厚みがピンホール或いは下部電極のエツジでの膜厚の
減少によるシ露−トを防ぐために厚めの４ｏｏｏＸの場
合には電極サイズは２００μ惰角になる。従って、能動
素子、整合回路およびバイアス回路を含めたモノリシッ
ク一段増幅器のチップサイズはＬ８閣ＸＬａ■と大きく
、モノリシック増幅器のチップを小形化する上での欠点
となっていた。In recent years, monolithic amplifiers using ultra-high frequency semiconductor transistors, which integrate matching circuits and bias circuits on a semiconductor substrate from a single unit level, have been attracting attention and are being actively researched. be. In a monolithic amplifier operating in an ultra-high frequency band, it is important to ground the active elements and bias circuit so as not to affect circuit matching. Conventionally, for grounding a monolithic amplifier, a grounding area is provided at any position within the chip, and since the grounding inductance is also reduced, a through hole, so-called via hole, is provided in the semiconductor substrate, and a grounding area is provided at an arbitrary position within the chip. Grounding was achieved by depositing a conductive metal within the range. Conventional monolithic amplifiers that are grounded using such a via hole structure are actually
It was published in the March issue of 1999, and in a paper by R. CHEN et al., and its structure is 1 as shown in Figure 1.
A source region 1 of a transistor is formed on the surface of a semiconductor substrate 11.
2 and bias circuit RF S'! Earth region 15 taken out from the lower electrode 18 of the capacitor 14 for
If, on the other hand, a through-hole 16 is formed on the back side of the semiconductor substrate 11 by chemical etching, a conductive metal 17 is coated on the inner surface of the through-hole 16, and this is connected to the ground region 15Jlc, as shown in FIG. Conductivity was established with the back surface), and this was used as the grounding surface. However, in the case of a conventional monolithic amplifier in which the earth region 15 is grounded by a via hole μ, first, when the through hole 16 is made by chemical etching, the amount of etching in depth and direction is limited. For example, if the thickness of the semiconductor substrate is 1501 ms, Ku, the back surface area is 30
On the other hand, as a capacitor for RF S/g-), a capacitance of 4f or more (impedance is 8.820 at 18 GHz) is required for the X-band frequency, and at that time, 5IOs is required for the dielectric. If the thickness is 4oooX, which is thick to prevent exposure due to pinholes or reduction in film thickness at the edge of the lower electrode, the electrode size will be 200μ coast angle. Therefore, the chip size of a monolithic single-stage amplifier including active elements, matching circuits, and bias circuits is as large as L8×XLa, which is a drawback in reducing the size of the monolithic amplifier chip.
本発明の目的は、このような従来の欠点を除去せしめて
、チップの小形化をはかったモノリシック増幅器を提供
する事にある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate such conventional drawbacks and provide a monolithic amplifier with a smaller chip size.
本発明は半導体基板上に形成されたバイアス回路をｌｉ
ｐ！／ｍ−）用キャパシタを通して接地するモノリシッ
ク増幅器において、前記キャパシタの下部電極を接地用
電極として用い、半導体基板の裏面の貫通孔に被着され
た導体金属を前記下部電極に結合したことを特徴とする
モノリシック増幅器である。The present invention provides a bias circuit formed on a semiconductor substrate.
p! /m-) in a monolithic amplifier grounded through a capacitor, the lower electrode of the capacitor is used as a grounding electrode, and a conductive metal deposited in a through hole on the back side of a semiconductor substrate is coupled to the lower electrode. It is a monolithic amplifier.
本発明は、Ｒｐ Ｓ／ ｍ −）用キャパシタの下部電
極ヲハイアホール対向電極とする事忙よシ、アース領域
に大面積を必要とせず、従って、チップサイズが小形化
されたモノリシック増幅器が得られるようにしたもので
ある。The present invention makes it possible to use the lower electrode of a capacitor for (Rp S/m -) as a higher hole counter electrode, so that a large area is not required for the ground region, and therefore a monolithic amplifier with a small chip size can be obtained. This is what I did.
以下、本発明の典型的な一実施例について、ガリウム砒
素（以下ＧａＡｓ と称す）モノリシック増幅器を例に
とって図面を参照して説明する。第２図に本発明の典型
的な一実施例であるＧａＡｓモノリシック増幅器の構造
を示す。すなわち、本発明はＧＢＡＢ ＭＥＳＦＥＴ
２２を有する半導体基板２１の表面に形成されたＲＦシ
ョート用ＭＩＭキャパシタ２３の造り灯ゲート電極と同
一金属である下部電極２４に対向し、基板裏面から下部
電極謁に到達するまで基板２１を化学エツチングにより
除去して貫通孔２５を設け、該貫通孔２５の内面及び基
板２１の裏面にん又はその合金、或いは加メッキの導体
金属２６を設け、該導体金属２６を下部電極２４に結合
して電気的導通を取り、これを接地したものである。Hereinafter, a typical embodiment of the present invention will be described with reference to the drawings, taking a gallium arsenide (hereinafter referred to as GaAs) monolithic amplifier as an example. FIG. 2 shows the structure of a GaAs monolithic amplifier which is a typical embodiment of the present invention. That is, the present invention is a GBAB MESFET.
The substrate 21 is chemically etched from the back surface of the substrate until it reaches the lower electrode 24 facing the lower electrode 24 which is made of the same metal as the lighting gate electrode of the MIM capacitor 23 for RF shorting formed on the surface of the semiconductor substrate 21 having 22. A through hole 25 is formed by removing the through hole 25, a conductive metal 26 made of an alloy thereof or a plated metal is provided on the inner surface of the through hole 25 and the back surface of the substrate 21, and the conductive metal 26 is connected to the lower electrode 24 to conduct electricity. This is done by establishing electrical conductivity and grounding it.
本発明は、ＲＦ Ｖ−１−）用キャパシタの下部電極を
接地用バイアホーμ対向電極としたため、アース領域に
大面積を必要とせず、従来の一段増幅器ではそのチップ
寸法が１．８ ａｍ Ｘ １．８ ｍであったのに対し
、本発明によればｌＮｌ×１．２ｍに小形化できる。In the present invention, since the lower electrode of the RF V-1-) capacitor is a grounding via hole μ counter electrode, a large area is not required for the grounding area, and the chip size of the conventional single-stage amplifier is 1.8 am x 1. According to the present invention, the size can be reduced to 1Nl×1.2m.
したがって、本発明によれば、チップの小型化によクモ
ノリ５フツク増幅熱の特徴をさらに増大できる効果を有
するものである。Therefore, according to the present invention, it is possible to further increase the characteristics of the five-hook amplified heat by reducing the size of the chip.
第１図は従来のモノリシック増幅器の断面図、第２図は
本発明のモノリシック増幅器の断面図である。
１１．２１・・・半導体基板、１２・・・ソース電極、
１８ 、２４・・・下部電極、１４２３・・・ＲＦショ
ート用キャパシタ、１５・・・アース領域、１６．２５
・・・貫通孔、１７．２６・・・導体金属、２２・・・
ＦＥＴ ０
特許出願人 日本電気株式会社FIG. 1 is a sectional view of a conventional monolithic amplifier, and FIG. 2 is a sectional view of the monolithic amplifier of the present invention. 11.21... Semiconductor substrate, 12... Source electrode,
18, 24... Lower electrode, 1423... RF shorting capacitor, 15... Earth region, 16.25
...Through hole, 17.26...Conductor metal, 22...
FET 0 Patent applicant NEC Corporation
Claims (1)
目−ト用キャパシタを通して接地するモノリシック増幅
器において、前記キャパシタの下部電極を接−地用電極
として用い、半導体基板の裏面の貫通孔に被着された導
体金属を前記下部電極に結合したことを特徴とするモノ
リシック増幅器。(1) In a monolithic amplifier in which a bias circuit formed on a semiconductor substrate is grounded through an RF sheet capacitor, the lower electrode of the capacitor is used as a grounding electrode and is covered with a through hole on the back side of the semiconductor substrate. A monolithic amplifier characterized in that a deposited conductive metal is coupled to the lower electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8968784A JPS60233911A (en) | 1984-05-04 | 1984-05-04 | Monolithic amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8968784A JPS60233911A (en) | 1984-05-04 | 1984-05-04 | Monolithic amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60233911A true JPS60233911A (en) | 1985-11-20 |
| JPH0527262B2 JPH0527262B2 (en) | 1993-04-20 |
Family
ID=13977673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8968784A Granted JPS60233911A (en) | 1984-05-04 | 1984-05-04 | Monolithic amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60233911A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0637844A2 (en) * | 1993-08-05 | 1995-02-08 | Nec Corporation | Semi conductor device constituting multi-stage power amplifier |
| US6137129A (en) * | 1998-01-05 | 2000-10-24 | International Business Machines Corporation | High performance direct coupled FET memory cell |
| US6297531B2 (en) | 1998-01-05 | 2001-10-02 | International Business Machines Corporation | High performance, low power vertical integrated CMOS devices |
-
1984
- 1984-05-04 JP JP8968784A patent/JPS60233911A/en active Granted
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0637844A2 (en) * | 1993-08-05 | 1995-02-08 | Nec Corporation | Semi conductor device constituting multi-stage power amplifier |
| EP0637844A3 (en) * | 1993-08-05 | 1998-02-18 | Nec Corporation | Semi conductor device constituting multi-stage power amplifier |
| US6137129A (en) * | 1998-01-05 | 2000-10-24 | International Business Machines Corporation | High performance direct coupled FET memory cell |
| US6297531B2 (en) | 1998-01-05 | 2001-10-02 | International Business Machines Corporation | High performance, low power vertical integrated CMOS devices |
| US6426530B1 (en) | 1998-01-05 | 2002-07-30 | International Business Machines Corporation | High performance direct coupled FET memory cell |
| US6518112B2 (en) | 1998-01-05 | 2003-02-11 | International Business Machines Corporation | High performance, low power vertical integrated CMOS devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0527262B2 (en) | 1993-04-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |