JPH0184449U - - Google Patents

Info

Publication number
JPH0184449U
JPH0184449U JP1987180583U JP18058387U JPH0184449U JP H0184449 U JPH0184449 U JP H0184449U JP 1987180583 U JP1987180583 U JP 1987180583U JP 18058387 U JP18058387 U JP 18058387U JP H0184449 U JPH0184449 U JP H0184449U
Authority
JP
Japan
Prior art keywords
lead frame
lead
shape
semiconductor
tip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987180583U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987180583U priority Critical patent/JPH0184449U/ja
Publication of JPH0184449U publication Critical patent/JPH0184449U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す上面概略図、
第2図は第1図のA―A線断面図、第3図は従来
のリードフレームを使用したモールド封止済の断
面概略図である。 1……アイランド、2,2a,2b,2c……
リード、3……半導体素子、4,4a,4b,4
c……ボンデイングワイヤー、5……モールド樹
脂。
FIG. 1 is a schematic top view showing an embodiment of the present invention;
FIG. 2 is a cross-sectional view taken along the line AA in FIG. 1, and FIG. 3 is a schematic cross-sectional view of a mold-sealed device using a conventional lead frame. 1... Island, 2, 2a, 2b, 2c...
Lead, 3...Semiconductor element, 4, 4a, 4b, 4
c...Bonding wire, 5...Mold resin.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体装置に使用されるリードフレームであつ
て、半導体素子を搭載する部分と外部電極となる
リード部分が同一平面にない形状を有するリード
フレームの内部リード先端部を凹状に加工したこ
とを特徴とする半導体装置用リードフレーム。
A lead frame used in a semiconductor device, the lead frame having a shape in which a portion on which a semiconductor element is mounted and a lead portion serving as an external electrode are not on the same plane, and is characterized in that the tip of the internal lead is processed into a concave shape. Lead frame for semiconductor devices.
JP1987180583U 1987-11-26 1987-11-26 Pending JPH0184449U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987180583U JPH0184449U (en) 1987-11-26 1987-11-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987180583U JPH0184449U (en) 1987-11-26 1987-11-26

Publications (1)

Publication Number Publication Date
JPH0184449U true JPH0184449U (en) 1989-06-05

Family

ID=31472097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987180583U Pending JPH0184449U (en) 1987-11-26 1987-11-26

Country Status (1)

Country Link
JP (1) JPH0184449U (en)

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