JPH0151110B2 - - Google Patents

Info

Publication number
JPH0151110B2
JPH0151110B2 JP7220183A JP7220183A JPH0151110B2 JP H0151110 B2 JPH0151110 B2 JP H0151110B2 JP 7220183 A JP7220183 A JP 7220183A JP 7220183 A JP7220183 A JP 7220183A JP H0151110 B2 JPH0151110 B2 JP H0151110B2
Authority
JP
Japan
Prior art keywords
phase
complex multiplier
input
signals
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP7220183A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59198052A (ja
Inventor
Tomohiko Taniguchi
Shigeyuki Umigami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7220183A priority Critical patent/JPS59198052A/ja
Publication of JPS59198052A publication Critical patent/JPS59198052A/ja
Publication of JPH0151110B2 publication Critical patent/JPH0151110B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
    • H04L27/06—Demodulator circuits; Receiver circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
JP7220183A 1983-04-26 1983-04-26 位相同期回路 Granted JPS59198052A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7220183A JPS59198052A (ja) 1983-04-26 1983-04-26 位相同期回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7220183A JPS59198052A (ja) 1983-04-26 1983-04-26 位相同期回路

Publications (2)

Publication Number Publication Date
JPS59198052A JPS59198052A (ja) 1984-11-09
JPH0151110B2 true JPH0151110B2 (enrdf_load_stackoverflow) 1989-11-01

Family

ID=13482378

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7220183A Granted JPS59198052A (ja) 1983-04-26 1983-04-26 位相同期回路

Country Status (1)

Country Link
JP (1) JPS59198052A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100238284B1 (ko) * 1997-05-12 2000-01-15 윤종용 위상 보정 회로 및 그 방법

Also Published As

Publication number Publication date
JPS59198052A (ja) 1984-11-09

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