JPH0149973B2 - - Google Patents

Info

Publication number
JPH0149973B2
JPH0149973B2 JP58121951A JP12195183A JPH0149973B2 JP H0149973 B2 JPH0149973 B2 JP H0149973B2 JP 58121951 A JP58121951 A JP 58121951A JP 12195183 A JP12195183 A JP 12195183A JP H0149973 B2 JPH0149973 B2 JP H0149973B2
Authority
JP
Japan
Prior art keywords
binary number
signal line
circuit
absolute value
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58121951A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6014326A (ja
Inventor
Teru Ishizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP58121951A priority Critical patent/JPS6014326A/ja
Publication of JPS6014326A publication Critical patent/JPS6014326A/ja
Publication of JPH0149973B2 publication Critical patent/JPH0149973B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/544—Indexing scheme relating to group G06F7/544
    • G06F2207/5442—Absolute difference

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
JP58121951A 1983-07-05 1983-07-05 絶対値演算回路 Granted JPS6014326A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58121951A JPS6014326A (ja) 1983-07-05 1983-07-05 絶対値演算回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58121951A JPS6014326A (ja) 1983-07-05 1983-07-05 絶対値演算回路

Publications (2)

Publication Number Publication Date
JPS6014326A JPS6014326A (ja) 1985-01-24
JPH0149973B2 true JPH0149973B2 (en, 2012) 1989-10-26

Family

ID=14823950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58121951A Granted JPS6014326A (ja) 1983-07-05 1983-07-05 絶対値演算回路

Country Status (1)

Country Link
JP (1) JPS6014326A (en, 2012)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62142010U (en, 2012) * 1986-03-04 1987-09-08
KR870009295A (ko) * 1986-03-28 1987-10-24 엔. 라이스 머레트 멀티플렉스된 바이패스 경로를 갖고있는 비트 슬라이스 프로세서용 alu
JPH07122845B2 (ja) * 1986-11-06 1995-12-25 日本電気株式会社 演算装置
JP2681968B2 (ja) * 1988-02-12 1997-11-26 松下電器産業株式会社 演算処理装置
JPH0223746U (en, 2012) * 1988-07-28 1990-02-16
JPH038018A (ja) * 1989-06-06 1991-01-16 Toshiba Corp 符号付き絶対値加減算器
US5699287A (en) * 1992-09-30 1997-12-16 Texas Instruments Incorporated Method and device for adding and subtracting thermometer coded data
CN1106616A (zh) * 1993-04-02 1995-08-09 古河电气工业株式会社 光纤端部及其制造方法和将该端部连接到光学器件的构造

Also Published As

Publication number Publication date
JPS6014326A (ja) 1985-01-24

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