JPH0146949B2 - - Google Patents
Info
- Publication number
- JPH0146949B2 JPH0146949B2 JP8254279A JP8254279A JPH0146949B2 JP H0146949 B2 JPH0146949 B2 JP H0146949B2 JP 8254279 A JP8254279 A JP 8254279A JP 8254279 A JP8254279 A JP 8254279A JP H0146949 B2 JPH0146949 B2 JP H0146949B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- memory cell
- erase
- memory
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015654 memory Effects 0.000 claims description 119
- 239000004020 conductor Substances 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 26
- 239000011159 matrix material Substances 0.000 claims description 10
- 230000008569 process Effects 0.000 description 16
- 238000007667 floating Methods 0.000 description 14
- 238000009792 diffusion process Methods 0.000 description 5
- 238000007599 discharging Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
Landscapes
- Read Only Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19782828836 DE2828836C2 (de) | 1978-06-30 | 1978-06-30 | Wortweise elektrisch löschbarer, nichtflüchtiger Speicher |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS558697A JPS558697A (en) | 1980-01-22 |
JPH0146949B2 true JPH0146949B2 (fr) | 1989-10-11 |
Family
ID=6043234
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8254279A Granted JPS558697A (en) | 1978-06-30 | 1979-06-29 | Nonnvolatile memory erasable electrically in word unit |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS558697A (fr) |
DE (1) | DE2828836C2 (fr) |
FR (1) | FR2430064B1 (fr) |
GB (1) | GB2029145B (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USRE41456E1 (en) | 1993-09-21 | 2010-07-27 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1224062B (it) * | 1979-09-28 | 1990-09-26 | Ates Componenti Elettron | Metodo di programmazione per una memoria a semiconduttore non volatile elettricamente alterabile |
US4797856A (en) * | 1987-04-16 | 1989-01-10 | Intel Corporation | Self-limiting erase scheme for EEPROM |
US4875188A (en) * | 1988-01-12 | 1989-10-17 | Intel Corporation | Voltage margining circuit for flash eprom |
KR900019027A (ko) * | 1988-05-23 | 1990-12-22 | 미다 가쓰시게 | 불휘발성 반도체 기억장치 |
US5095344A (en) * | 1988-06-08 | 1992-03-10 | Eliyahou Harari | Highly compact eprom and flash eeprom devices |
US4888738A (en) * | 1988-06-29 | 1989-12-19 | Seeq Technology | Current-regulated, voltage-regulated erase circuit for EEPROM memory |
US5844842A (en) | 1989-02-06 | 1998-12-01 | Hitachi, Ltd. | Nonvolatile semiconductor memory device |
JP2654596B2 (ja) * | 1989-02-06 | 1997-09-17 | 株式会社日立製作所 | 不揮発性記憶装置 |
EP0675502B1 (fr) | 1989-04-13 | 2005-05-25 | SanDisk Corporation | Système EEPROM avec effacement en bloc contenant des puces multiples |
FR2647941B1 (fr) * | 1989-06-06 | 1991-08-30 | Gemplus Card Int | Procede d'effacement de points memoire, dispositif destine a sa mise en oeuvre, et son utilisation dans un dispositif a memoire non alimente |
DE69013237T2 (de) * | 1989-06-19 | 1995-02-23 | Texas Instruments Inc | Schaltung und Verfahren zur Vorbereitung gelöschter EEPROMS vor der Programmierung. |
JP3448051B2 (ja) * | 1990-03-31 | 2003-09-16 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP2709751B2 (ja) * | 1990-06-15 | 1998-02-04 | 三菱電機株式会社 | 不揮発性半導体記憶装置およびそのデータ消去方法 |
US5361227A (en) * | 1991-12-19 | 1994-11-01 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and memory system using the same |
US6781895B1 (en) | 1991-12-19 | 2004-08-24 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and memory system using the same |
JP3512833B2 (ja) * | 1993-09-17 | 2004-03-31 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP3202498B2 (ja) * | 1994-03-15 | 2001-08-27 | 株式会社東芝 | 半導体記憶装置 |
JP2987105B2 (ja) * | 1996-06-10 | 1999-12-06 | ハライ エリヤホウ | フラッシュEEpromメモリシステムとその使用方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5193638A (fr) * | 1975-02-14 | 1976-08-17 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2643987C2 (de) * | 1974-09-20 | 1984-03-29 | Siemens AG, 1000 Berlin und 8000 München | n-Kanal-Speicher-FET |
JPS5823677B2 (ja) * | 1976-05-18 | 1983-05-17 | 三菱電機株式会社 | 記憶消去装置 |
JPS5330838A (en) * | 1976-09-03 | 1978-03-23 | Fujitsu Ltd | Erasing method of erasable rom |
-
1978
- 1978-06-30 DE DE19782828836 patent/DE2828836C2/de not_active Expired
-
1979
- 1979-06-28 GB GB7922592A patent/GB2029145B/en not_active Expired
- 1979-06-28 FR FR7916728A patent/FR2430064B1/fr not_active Expired
- 1979-06-29 JP JP8254279A patent/JPS558697A/ja active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5193638A (fr) * | 1975-02-14 | 1976-08-17 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USRE41456E1 (en) | 1993-09-21 | 2010-07-27 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
USRE41468E1 (en) | 1993-09-21 | 2010-08-03 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
USRE41950E1 (en) | 1993-09-21 | 2010-11-23 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
USRE42120E1 (en) | 1993-09-21 | 2011-02-08 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
Also Published As
Publication number | Publication date |
---|---|
DE2828836A1 (de) | 1980-01-03 |
GB2029145A (en) | 1980-03-12 |
JPS558697A (en) | 1980-01-22 |
GB2029145B (en) | 1982-06-16 |
DE2828836C2 (de) | 1983-01-05 |
FR2430064B1 (fr) | 1985-10-18 |
FR2430064A1 (fr) | 1980-01-25 |
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