JPH0140516B2 - - Google Patents

Info

Publication number
JPH0140516B2
JPH0140516B2 JP55138801A JP13880180A JPH0140516B2 JP H0140516 B2 JPH0140516 B2 JP H0140516B2 JP 55138801 A JP55138801 A JP 55138801A JP 13880180 A JP13880180 A JP 13880180A JP H0140516 B2 JPH0140516 B2 JP H0140516B2
Authority
JP
Japan
Prior art keywords
thick film
resistors
circuit
metal foil
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55138801A
Other languages
Japanese (ja)
Other versions
JPS5763852A (en
Inventor
Hiroshi Ootsu
Hiromi Isomae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55138801A priority Critical patent/JPS5763852A/en
Publication of JPS5763852A publication Critical patent/JPS5763852A/en
Publication of JPH0140516B2 publication Critical patent/JPH0140516B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H01L27/016Thin-film circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Description

【発明の詳細な説明】 本発明は混成集積回路に係り、特に抵抗値温度
係数が小さく、かつ高精度が要求される抵抗体を
含む混成集積回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit, and more particularly to a hybrid integrated circuit including a resistor that requires a small temperature coefficient of resistance and high accuracy.

厚膜混成集積回路に使用されている厚膜抵抗体
はセラミツク基板上に、導体、低抗体を印刷焼成
することにより形成される。この厚膜抵抗体の温
度係数(以下TCRと略す)は導体や抵抗体材料、
焼成プロセス等により決まるが、材料、プロセス
のばらつきの影響で現状ではTCRが0±
50ppm/℃程度が限界である。また、抵抗値の精
度はレーザトリミングやサンドブラストトリミン
グで精度よく調整した場合でも±0.5程度である。
Thick film resistors used in thick film hybrid integrated circuits are formed by printing and firing a conductor and a low antibody on a ceramic substrate. The temperature coefficient (hereinafter abbreviated as TCR) of this thick film resistor is determined by the conductor and resistor material.
It is determined by the firing process, etc., but currently TCR is 0± due to variations in materials and processes.
The limit is about 50ppm/℃. Further, the accuracy of the resistance value is about ±0.5 even when precisely adjusted by laser trimming or sandblasting trimming.

一方厚膜回路基板よりも精度の高い所をねらう
場合に使用されている薄膜抵抗体は蒸着やスパツ
タにより形成されるので特性は優れているが
TCRは0±30ppm/℃、精度は0.05%程度であ
る。
On the other hand, thin film resistors, which are used when aiming at higher precision locations than thick film circuit boards, are formed by vapor deposition or sputtering, so they have superior characteristics.
The TCR is 0±30ppm/℃, and the accuracy is about 0.05%.

このため高精度の抵抗が要求される回路とし
て、例えばD/A(デジタルアナログ)コンバー
タ回路の場合を考えると、ビツト数が1つ増える
毎に抵抗値精度は2倍の高精度が要求され、14ビ
ツトのD/Aコンバータ回路の場合には抵抗値精
度は上位ビツトでは±0.01%の精度が要求され
TCRも0±10ppm以下の特性を必要とするので、
従来ではD/Aコンバータ用抵抗としては薄膜抵
抗のTCRや抵抗値を測定選別して、回路特性に
合うものを使用していた。このためD/Aコンバ
ータは製作するのに多大な手数がかかり、歩留り
も低く価格が高いという欠点を有していた。
For this reason, if we consider the case of a D/A (digital-to-analog) converter circuit as a circuit that requires high-precision resistance, for example, the resistance value accuracy is required to be twice as high as the number of bits increases by one. In the case of a 14-bit D/A converter circuit, resistance value accuracy of ±0.01% is required for the upper bits.
Since TCR also requires characteristics of 0±10ppm or less,
Conventionally, resistors for D/A converters have been selected by measuring the TCR and resistance values of thin film resistors, and using resistors that match the circuit characteristics. For this reason, the D/A converter has disadvantages in that it takes a lot of effort to manufacture, and the yield is low and the price is high.

本発明は以上説明した従来の欠点をなくし、
TCRが小さく、かつ高精度の抵抗体を含む歩留
りの高い混成集積回路を提供するにある。
The present invention eliminates the conventional drawbacks described above,
An object of the present invention is to provide a high-yield hybrid integrated circuit that has a small TCR and includes a high-precision resistor.

上記目的はTCRの小さい高精度抵抗体として
金属箔抵抗体チツプを使用し、一方高精度の要求
されない抵抗体を厚膜抵抗体で形成することで達
成できる。
The above object can be achieved by using a metal foil resistor chip as a high precision resistor with a small TCR, while forming a resistor that does not require high precision with a thick film resistor.

以下本発明を実施例により詳述する。第1図は
本発明の一実施例を示す混成集積回路の平面図で
ある。1は厚膜回路板であり、アルミナ等のセラ
ミツク基板2にPd−Ag導体パターン3が印刷焼
成により形成され、RuO2系厚膜抵抗体4が同じ
く印刷焼成により形成される。ここで厚膜抵抗体
4は必要に応じて所定の値にトリミングが行われ
る。5は金属箔抵抗体チツプであり、厚膜抵抗体
1の上に搭載され、金属箔抵抗体5と厚膜導体パ
ターン6とは接続用導線7により接続され、回路
が形成されている。8は厚膜回路基板1の上に搭
載された半導体等のチツプ部品であり、リード端
子が接続され混成集積回路となる。
The present invention will be explained in detail below with reference to Examples. FIG. 1 is a plan view of a hybrid integrated circuit showing one embodiment of the present invention. Reference numeral 1 designates a thick film circuit board, in which a Pd--Ag conductor pattern 3 is formed on a ceramic substrate 2 made of alumina or the like by printing and firing, and a RuO 2 -based thick film resistor 4 is also formed by printing and firing. Here, the thick film resistor 4 is trimmed to a predetermined value as necessary. A metal foil resistor chip 5 is mounted on the thick film resistor 1, and the metal foil resistor 5 and the thick film conductor pattern 6 are connected by a connecting lead 7 to form a circuit. 8 is a chip component such as a semiconductor mounted on the thick film circuit board 1, and lead terminals are connected to form a hybrid integrated circuit.

第2図は第1図に示す金属箔抵抗体の詳細を示
す平面図である。11は金属箔抵抗体でNiCrを
主成分とする特殊合金の箔であり、その特徴とす
るところは温度係数が非常に小さく0±5ppm/
℃程度のものが安定して得られるところにある。
この箔抵抗パターンは図に示すようにジクザクパ
ターンで形成されているが、一部分のジクザクパ
ターンは短絡パターン12で短縮した状態に形成
しておき、短絡パターン12を順次切断すること
により抵抗値を高い方向に調整することができ、
この短絡パターン12を設けたジクザクパターン
の形状を変えることにより±0.01%の精度まで調
整が可能である。13は箔抵抗体を保持するため
の絶縁基板である。
FIG. 2 is a plan view showing details of the metal foil resistor shown in FIG. 1. 11 is a metal foil resistor, which is made of a special alloy foil whose main component is NiCr, and its characteristic is that it has a very small temperature coefficient of 0 ± 5 ppm/
It is a place where temperatures around ℃ can be obtained stably.
This foil resistance pattern is formed in a zigzag pattern as shown in the figure, but some of the zigzag patterns are formed in a shortened state with short circuit patterns 12, and the resistance value is increased by sequentially cutting the short circuit patterns 12. can be adjusted in the direction,
By changing the shape of the zigzag pattern in which the short circuit pattern 12 is provided, the accuracy can be adjusted to ±0.01%. 13 is an insulating substrate for holding the foil resistor.

次に混成集積回路を動作状態とし、回路の特性
が所定の値となるように必要な厚膜抵抗あるいは
金属箔抵抗をトリミングして調整を行うものであ
る。
Next, the hybrid integrated circuit is brought into operation, and necessary thick film resistors or metal foil resistors are trimmed and adjusted so that the characteristics of the circuit reach predetermined values.

本発明は以上説明したような構成であり、特に
TCRの小さい箔抵抗体チツプはそれだけの性能
が必要とされる個所にのみ使用し、それ以外は厚
膜抵抗体で形成することで高精度の必要な混成集
積回路ができるので、従来の薄膜抵抗のように
TCRを測定選別する手間が必要でなくなる。ま
た回路は動作状態で抵抗値をトリミングするいわ
ゆる機能トリミングを行うので回路特性は目標値
に精度よく調整ができる。
The present invention has the configuration as described above, and in particular
Foil resistor chips with a low TCR are used only where such performance is required, and thick film resistors are used in other areas to create hybrid integrated circuits that require high precision. like
The effort of measuring and selecting TCR is no longer necessary. Further, since the circuit performs so-called functional trimming in which the resistance value is trimmed in the operating state, the circuit characteristics can be precisely adjusted to the target value.

従つて本発明によれば高精度な金属箔抵抗体チ
ツプを使用することにより混成集積回路を歩留よ
く製作することができ価格も安くすることができ
る。
Therefore, according to the present invention, by using a highly accurate metal foil resistor chip, a hybrid integrated circuit can be manufactured at a high yield and at a low price.

本発明の具体的応用としてはD/Aコンバータ
において高精度が要求される上位ビツト側に金属
箔抵抗体チツプを使用し、下位ビツト側に厚膜抵
抗体を使用することにより14ビツト程度のD/A
コンバータでも精度よく製作でき、価格も大幅に
低減されるものである。
A specific application of the present invention is to use a metal foil resistor chip on the upper bit side where high precision is required in a D/A converter, and a thick film resistor chip on the lower bit side to achieve a D/A converter of about 14 bits. /A
Even a converter can be manufactured with high precision, and the cost can be significantly reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す平面図、第2
図は金属箔抵抗体チツプの平面図である。 1:厚膜回路板、4:厚膜抵抗体、5:金属箔
抵抗体チツプ。
FIG. 1 is a plan view showing one embodiment of the present invention, and FIG.
The figure is a plan view of a metal foil resistor chip. 1: Thick film circuit board, 4: Thick film resistor, 5: Metal foil resistor chip.

Claims (1)

【特許請求の範囲】[Claims] 1 セラミツク基板上に導体、抵抗等を形成した
厚膜回路基板上に、少なくとも金属箔抵抗体チツ
プを搭載した混成集積回路において、少なくとも
一部の厚膜抵抗体は予じめ所定の値に調整すると
共に、一部の厚膜抵抗体と金属箔抵抗体または必
要な金属箔抵抗体のみを回路を動作状態として機
能トリミングを行い、所定の回路特性となるよう
に調整したことを特徴とする混成集積回路。
1. In a hybrid integrated circuit in which at least a metal foil resistor chip is mounted on a thick film circuit board on which conductors, resistors, etc. are formed on a ceramic substrate, at least some of the thick film resistors are adjusted to predetermined values in advance. At the same time, the circuit is functionally trimmed with some of the thick film resistors and metal foil resistors or only the necessary metal foil resistors in the operating state, and adjusted to have predetermined circuit characteristics. integrated circuit.
JP55138801A 1980-10-06 1980-10-06 Hybrid integrated circuit Granted JPS5763852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55138801A JPS5763852A (en) 1980-10-06 1980-10-06 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55138801A JPS5763852A (en) 1980-10-06 1980-10-06 Hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPS5763852A JPS5763852A (en) 1982-04-17
JPH0140516B2 true JPH0140516B2 (en) 1989-08-29

Family

ID=15230543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55138801A Granted JPS5763852A (en) 1980-10-06 1980-10-06 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5763852A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03113154U (en) * 1990-03-02 1991-11-19
DE112005001155T5 (en) 2004-05-18 2007-04-19 NGK Spark Plug Co., Ltd., Nagoya Resistive element, its precursor, and method of resistance adjustment

Also Published As

Publication number Publication date
JPS5763852A (en) 1982-04-17

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