JPH0137889B2 - - Google Patents
Info
- Publication number
- JPH0137889B2 JPH0137889B2 JP319083A JP319083A JPH0137889B2 JP H0137889 B2 JPH0137889 B2 JP H0137889B2 JP 319083 A JP319083 A JP 319083A JP 319083 A JP319083 A JP 319083A JP H0137889 B2 JPH0137889 B2 JP H0137889B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- oscillator
- output
- pll
- mixer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000010355 oscillation Effects 0.000 claims description 10
- 230000002238 attenuated effect Effects 0.000 claims 1
- 230000006866 deterioration Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
Landscapes
- Circuits Of Receivers In General (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP319083A JPS59128833A (ja) | 1983-01-12 | 1983-01-12 | 受信機の回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP319083A JPS59128833A (ja) | 1983-01-12 | 1983-01-12 | 受信機の回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59128833A JPS59128833A (ja) | 1984-07-25 |
JPH0137889B2 true JPH0137889B2 (enrdf_load_stackoverflow) | 1989-08-10 |
Family
ID=11550480
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP319083A Granted JPS59128833A (ja) | 1983-01-12 | 1983-01-12 | 受信機の回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59128833A (enrdf_load_stackoverflow) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6002924A (en) * | 1996-12-31 | 1999-12-14 | Aor, Ltd. | Full-spectrum all-mode radio receiver apparatus and method |
-
1983
- 1983-01-12 JP JP319083A patent/JPS59128833A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS59128833A (ja) | 1984-07-25 |