JPH0137889B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to an improvement in a digital tuning circuit for a PLL control unit oscillator. [Prior art] Conventionally, in the digital tuning system in which the local oscillator of the receiver is controlled by PLL, it is difficult to reduce the minimum frequency to a sufficiently small order in order to improve the operating speed and C/N. Great sacrifices are made in the circuit and in the method of allocating frequency settings to both the first mixer and the second mixer in order to prevent the occurrence of cross spurious and deterioration of C/N. [Problem to be Solved by the Invention] However, in the above-mentioned conventional technology, the cause of cross spurious is that the circuit includes multiple oscillators and mixers, and unnecessary frequencies generated from complicated frequency relationships cannot be completely removed by filters. It is for the sake of
The main reason for the deterioration of the C/N is that the reference frequency becomes lower, making it difficult to remove ripples in the carrier. The present invention aims to provide a circuit that improves the drawbacks of such digital tuning circuits. [Means for Solving the Problems] The reference frequencies of all the PLL circuits in the present invention are supplied from one reference oscillator, and each
The circuit is configured to keep the reference frequency of the PLL high, thereby preventing the occurrence of cross spurious and achieving a good C/N ratio. [Example] The configuration of the digital tuning circuit of the present invention will be explained based on the drawings using a circuit (indicated by a dotted line) to which claim 2 is added. In FIG.
The reference oscillation frequency obtained from (hereinafter referred to as _R0 )
A frequency division code for setting an upper frequency is input into the PLL 6a, which uses the reference frequency (hereinafter referred to as _R1 ) obtained by the frequency divider/multiplier 7a as appropriate, to oscillate the local oscillation frequency of the mixer stage 1a. Similarly, the PLL 6 uses _R0 as the reference frequency (hereinafter referred to as _R2 ) obtained by the frequency divider/multiplier 7b.
The output obtained by inserting the frequency division code for the lower frequency setting into b is divided through the frequency divider 5 until the desired frequency step is obtained, and the output obtained is mixed with the output of BFO 4 in mixer stage 1c, and the second input to mixer 1b. Here, the circuit shown in dotted lines in the drawings in claim 2, that is, the frequency divider/multiplier 7c for _R0 .
The reference frequency _R3 obtained by mixing the frequency obtained by mixing with the mixer stage 1c is mixed with the mixer 1d and injected as the local oscillation frequency of the second mixer stage 1b of the signal circuit. It is also injected into The above is an overview of the main configuration of the receiver circuit of the present invention, but since it is difficult to analyze its operating principle with a general solution, an example of the frequency configuration of a full-wave receiver is shown in FIG. This proves that it is an excellent circuit system that can be implemented and solves the above-mentioned problems. The reception frequency range of this receiver is 0 to 30MHz, the first intermediate frequency is 75.105MHz, the reference oscillator is 8
is set to 15MHz. The highest digit of the frequency adjustment is often selected to be 1MHz in general-purpose machines, but this machine is variable in 500kHz steps in consideration of amateur band use. The local oscillation frequency of the mixer stage 1a is preferably set higher than the intermediate frequency from the viewpoint of image removal, so it is set from 75.1 MHz to 105.09 MHz, but it is divided between two VCOs in consideration of stability. Applicable VCO
Part of the output is from 5MHz to 19.5M in mixer stage M1
It is converted to Hz, passed through BPF, divided by 10 to 39 by programmable frequency divider D1, and compared with 500kHz _R1 obtained by dividing the reference oscillation by 30 by phase comparator PD1.
The differential control signal is fed back to the VCO through the LPF, and since the frequency division ratio of this PLL 6a is small and the reference frequency is high, the operation is stable and the C/N is good. Since the frequency change of this PLL 6a is in 500 kHz steps, the other PLL 6c circuit interpolates up to 10 kHz steps, and Table 1 shows the results. However, simply using a 10kHz step PLL
In the oscillation circuit, the comparison reference frequency is 10kHz, and there is a problem with the time constant of the loop filter, so the comparison frequency is 100kHz, which is obtained by dividing the reference oscillator's 15MHz by 150, and the VCO output is divided by 10 instead. 10kHz steps are obtained. VCO3 is 101MHz to 105.9MHz, and 11M is mixed with 90MHz, which is 6 times the reference oscillation.
Hz to 15.9MHz with programmable frequency divider D2
The frequency is divided from 110 to 159, and the phase is compared with 100kHz obtained by dividing the reference oscillation by 150 using phase comparator PD2. Divide the output of VCO3 by 10 and use the reference oscillator 8.
Obtained by mixing with 60MHz obtained by multiplying 15MHz by 4.
The upper part of Table 1 and Table 2 illustrate that by injecting 70.1MHz to 70.59MHz into the mixer stage M1 of the PLL6a circuit, the output frequency of the VCO1 can be adjusted in 10kHz steps. In addition, by dividing the output of VCO3 by 10 and injecting 85.59MHz from the 85.1MHz obtained by mixing with 75MHz obtained by multiplying the reference oscillator's 15MHz by 5 into the mixer stage M1 of the PLL6a circuit, The lower part of Table 1 and Table 2 illustrate that the output frequency can be adjusted from 90.1MHz to 905.09MHz in 10kHz steps. The first intermediate frequency of the output of mixer stage 1a is
75.105MHz, but since the tuning is in 10kHz steps, the signal exists between 75.1MHz and 75.10999MHz, so it is desirable to have characteristics that pass this range flatly and attenuate as steeply as possible outside the band.
Preferably, such a filter is one that is practically used as a VHF band crystal filter. The PLL 6b circuit injected into the second mixer stage 1b is configured to interpolate between the 10 kHz steps in 0.01 kHz steps and output a constant frequency signal to the narrow band second intermediate frequency stage 2b.

【table】

Claims (1)

[Claims] 1. (a) A PLL or multiple PLL circuit controlled by a reference frequency based on one reference oscillator, and for coarse steps controlling the main PLL circuit.
The reference frequency of the PLL circuit is sufficiently higher than the cutoff frequency of the loop filter of the main PLL circuit, and the reference frequency oscillator of the coarse step PLL remaining in the output of the coarse step PLL,
Alternatively, a first mixer stage whose local oscillator is an oscillator configured so that its harmonic components can be sufficiently attenuated by the loop filter of the main PLL circuit. (b) A first intermediate frequency stage having a passband width corresponding to at least the frequency of the coarse step. (c) an output of a second relatively high frequency PLL oscillator that is controlled by a reference frequency based on the one reference oscillator and interpolates between the coarse step frequencies of the first mixer in finer steps; A second mixer stage that uses the frequency obtained by mixing the output obtained by dividing the frequency with the output of a carrier oscillator (BFO) that supplies a carrier to the demodulator as the local oscillator frequency. A receiver circuit comprising: 2 The local oscillation frequency input to the second mixer is obtained by mixing the frequency obtained by mixing the output of the second PLL circuit and the output of the carrier oscillator with the frequency based on the one reference oscillator. , whose frequency is the local oscillation frequency of the second mixer.