JPS59128833A - Receiver circuit - Google Patents

Abstract

PURPOSE:To eliminate the apprehension of generation of spurious radiation because of interference between plural oscillators by using an output of a single oscillator after frequency-division and multiplication as a reference comparison frequency of three kinds of PLL circuits. CONSTITUTION:A local oscillating frequency of a mixer M1 is formed by giving a frequency-division code for setting an upper frequency to the PLL1 in which an fR1 obtained by frequency-dividing or multiplying suitably a reference frequency fR0 is used as a reference frequency. Similarly, a frequency obtained by mixing an output which is obtained by giving a frequency-division code for a lower frequency setting to the PLL2 taking an fR2 obtained from the frequency- division or multiplication of the frequency fR0 as the reference frequency with an output of a carrier oscillator BFO at a mixer M3 and then mixing the mixed result with a frequency fR3 obtained by frequency-dividing or multiplying the frequency fR0 at a mixer M4, is injected to a mixer M2 of a signal circuit as a local oscillating frequency. Further, the output of the BFO is injected to a demodulator.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in the circuitry of a PLL controlled local oscillator digitally tuned receiver.

In a digital tuning system in which the local oscillator of the receiver is controlled by PLL, it is difficult to make the minimum frequency sufficiently small in order to achieve both operational speed and performance, and multiple PLL circuits, etc.
Although great sacrifices are made in distributing frequency settings to both the first mixer and the second mixer to prevent the occurrence of cross spurs and the deterioration of C and 4J, the cause of cross spurs is the circuit. This is because the filter has multiple oscillators and mixers, and unnecessary frequencies generated from complex frequency relationships cannot be completely removed by a filter.In C/N, the reference frequency becomes low, making it difficult to remove ripples in the carrier. The cause is big. In view of the above, in the present invention, the reference frequencies of all PLL circuits are supplied from one reference oscillator, and the circuit is configured so as to maintain the reference frequency of each PLL high, thereby eliminating cross snorias. prevent the occurrence of
I was able to decoy a good one.

That is, the present invention provides a PLL controlled by a reference frequency with a temperature difference between one reference oscillator or a multiple PLL.
A first mixer stage having an oscillator as a local oscillator, which is constructed by a circuit, and whose frequency change has the lowest step at a value such that the leakage of the reference frequency can be sufficiently attenuated by the loop filter of the final loop, and at least the frequency of the minimum step. A first intermediate frequency stage having a passband width corresponding to 4 times the amount of change, and a reference frequency that makes the one reference oscillator a temperature difference, further finely changing the minimum step frequency of the first mixer. a second relatively high frequency PL complementary to the step;
The frequency obtained by dividing the output of the L oscillator and the output of the carrier oscillator (BFO) that supplies carriers to the demodulator is mixed with the output of the carrier oscillator (BFO) that supplies carriers to the demodulator. This is a receiver circuit characterized in that it further includes a second mixer stage which uses the frequency obtained by mixing the signal as a local oscillation frequency, and an example of the block circuit is shown in FIG.

In FIG. 1, the local oscillation frequency of the first mixer Ml is created by inputting a frequency division code for setting an upper frequency into a PLLI which has a reference frequency of 8 obtained by appropriately dividing or multiplying the reference oscillation frequency fRO.

Similarly, the output obtained by inserting the frequency division code for the lower frequency setting into PLL 2, which uses fR□ obtained by dividing or multiplying RO as the reference frequency, is divided through the frequency divider until the desired frequency step is reached. The output obtained is the output of BFO and M
3, and if necessary, the frequency obtained by dividing or multiplying fRo and mixing with M4 is injected as the local oscillation frequency of the second mixer stage M2 of the signal circuit, and BFO is naturally injected into the demodulator as well.

The above is an overview of the main configuration of the receiver circuit of the present invention.
Since it is difficult to analyze its operating principle with a general solution, an example of the frequency configuration of a full-wave receiver is shown in FIG. This proves that the circuit system is

The receivable frequency range of this receiver is 0 to 30 MHz, the first intermediate frequency is set at 75°105 MHz, and the reference oscillator is set at 15 MHz. The highest digit of the frequency adjustment is often set to I MHz in general-purpose machines, but this machine is variable in 500kHz steps in consideration of the use of the amateur band.

It is desirable to set the local frequency of mixer M1 higher than the IF frequency from the viewpoint of image removal, so it is 75.1 to 105.
09 MHz, but considering stability, two VCOs are installed.
It is divided into A part of the VCO output is 5~ by mixer MH.
It is converted to 19.5 MHz, passed through BPF, divided by 10 to 39 by programmable frequency divider D1, and compared with 'R1a of 500 kHz obtained by dividing the reference oscillation by 30 using a phase comparator. The control signal is fed back to the VCO through the LPF, and since the frequency division ratio of this PLL is small and the reference frequency is high, the operation is stable and the C/N is good.

The frequency change of this PLL1a is 500 kHz.In the step-type PLL oscillation circuit, the comparison difference single frequency is 10 kHz.
However, since there is a problem with the time constant of the loop filter, the baseline oscillator's 15 MI (10
0 kHz is used as a comparison frequency, and p 10 kHz steps are obtained by dividing the VCO output by 10 instead.

VCO3 is 101~105.9 MHz Teah”C1
The 11-15.9 MHz, which is a mixture of this and 901 Hz, which is the standard oscillation multiplied by 6, is divided by 110-159 using the programmable frequency division BD2, and the 100 kHz and phase of fR4b, which is the standard frequency divided by 150, are I'm comparing.

Divide the output of VCO3 by 10 to obtain 15 M of the reference oscillator.
By injecting 60 MHz obtained by multiplying Hz by 4 and 70.1 to 70.59 MHz obtained by mixing it with 70.1 to 70.59 MHz to the mixer Mll of the PLLI a circuit, the output frequency of VCO1 can be expressed as 1°. 1 Table 2 Also, divide the output of VCO3 by 10 and divide the output of the reference oscillator by 15
By injecting 85.1 to 85.59 MHz obtained by mixing with 75 MHz obtained by multiplying MI (z by 5) to mixer Mll of the PLL circuit, the output frequency of VCO2 is 90, 1~105.09MHz to 10kHz
In the z step, the first intermediate frequency of the output of the mixer M1 is 7.
5.105 MHz, but since the tuning is in 10 kHz steps, the signal is 75.1-75.10999 M
Hz, it is desirable that the filter pass flatly through this range and attenuate as steeply as possible outside the band, and such a filter is preferably one that is practically used as a VHF band crystal filter.

The PLL 2 circuit injected into the second mixer M2 is 10k.
Interpolate between Hz steps in 0.01 kHz steps,
This configuration outputs a signal at a constant frequency to the narrow-band second intermediate frequency stage.

The VCO4 of PLL 2 with is 100-109.99 M
Hz, which is 90MH which is 6 times the reference frequency.
z and mixer M2. lO mixed at ~19.99 MH
z from 1000 to 1999 with programmable frequency divider D3
The frequency is divided to 1 00 k, which is the comparison frequency of PLL1b.
The phase is compared with 10 kHz obtained by further dividing Hz by 10. Therefore, the change step of this PLL oscillation is 10 kHz, but this output is divided by 1000 to 100 to 109.99 kHz (7) 0.01
I am getting kHz speed. This is further mixed with the BFO output at a mixer distance, but since the second intermediate frequency is set at 9 MHz (actually, a slight fraction is added to avoid internal spurious, but for convenience of calculation, the fraction is is round)
BFO is 9,001 MHz with 1 kHz offset
(The BFO frequency is ±1.5k for SSB.
For Hz and CW, it is normal to offset by about ±8'0 OHZ, so here it is set to +1 kHz for convenience).

3. The output frequency of death is 9.101~9.110994? 84.101 to 84.1 iHz was obtained by mixing with 75 MHz, which is the standard frequency multiplied by 5 using mixer h.
11099R4I (z is the injection frequency of mixer M2. The value obtained by subtracting 9 MHz of the second IF from this frequency is the LIP', but this frequency is determined by the position of the carrier (the second
In IF, it corresponds to 9.0011i11Hz), so
Center frequency needs to be corrected by 1 kHz, mixer M
2 input frequency (1st IF) is converted to 75.1~7
・5.10999MHz. This change range is 9.9
At 9 kHz, the digit went up in the next stay 7' and l O
kHz and less, 10 kHz step of PLLI
It can be seen that interpolation is performed in Hz steps.

The configuration of PLL 2 has a low comparison frequency of 10 kHz (however, it is high enough for a 10 Hz step PLL), and the frequency division ratio of frequency divider D3 is also large, so this is a disadvantageous condition for a PLL. By dividing the output frequency by 1000, the CA and stability are greatly improved, so the overall rating is 3, although there is no problem at all. There is no problem in providing an independent injection oscillator, but using it with a BFO as in the circuit shown in Figure 2 is not only economical, but also due to the loop operation including M2 and the second intermediate frequency stage. It is advantageous to share the oscillator because it automatically compensates for frequency fluctuations.

A feature of the configuration of the present invention is that the output of a single oscillator is divided and multiplied and used as the reference comparison frequency for the three types of PLL circuits, so there is no risk of spurious generation due to interference between multiple oscillators. Since the same output frequency can be used in common for the multiplier, which is shown separately in the figure, the implementation can be further simplified.

LPF -? included in the circuit throughout? BPF
Although I have omitted the explanation, in general, the rejection frequency is higher than the pass frequency, and the frequencies are also far apart, so removal is relatively easy, and there are many parts where inexpensive and small filters such as ceramic filters can be used. is also advantageous.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of a receiver circuit according to the present invention, and FIG. 2 is an example of an implementation circuit for explaining the operation. Ml r M2 y M3 + M4...mixer stage, PLL 1. PLL 2...PLL oscillation circuit, fRO...reference oscillator. Patent applicant Yaesu Musen Co., Ltd.

Claims (1)

[Claims] (a) A PLL controlled by a reference frequency based on one reference oscillator is constructed by a multiple PLL circuit, and the minimum step of frequency change is determined by the leakage of the reference frequency. A first mixer stage whose local oscillator is an oscillator whose value can be sufficiently attenuated by the loop filter of the loop. (b) A first intermediate frequency stage having a passband width that accommodates at least the amount of frequency change of the minimum step. (c) A second relatively high frequency PLL that is controlled by a reference frequency based on the one reference oscillator and interpolates between the minimum step frequencies of the first mixer in finer steps. A carrier oscillator (BFO) divides the output of the oscillator and supplies the carrier to the demodulator.
) and, if necessary, further mixed with a frequency originating from the reference oscillator as the local oscillation frequency. A receiver circuit comprising: