JPS59128833A - 受信機の回路 - Google Patents

受信機の回路

Info

Publication number
JPS59128833A
JPS59128833A JP319083A JP319083A JPS59128833A JP S59128833 A JPS59128833 A JP S59128833A JP 319083 A JP319083 A JP 319083A JP 319083 A JP319083 A JP 319083A JP S59128833 A JPS59128833 A JP S59128833A
Authority
JP
Japan
Prior art keywords
frequency
oscillator
mixer
output
pll
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP319083A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0137889B2 (enrdf_load_stackoverflow
Inventor
Koji Akiyama
秋山　好司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaesu Musen Co Ltd
Original Assignee
Yaesu Musen Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaesu Musen Co Ltd filed Critical Yaesu Musen Co Ltd
Priority to JP319083A priority Critical patent/JPS59128833A/ja
Publication of JPS59128833A publication Critical patent/JPS59128833A/ja
Publication of JPH0137889B2 publication Critical patent/JPH0137889B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers

Landscapes

  • Circuits Of Receivers In General (AREA)
JP319083A 1983-01-12 1983-01-12 受信機の回路 Granted JPS59128833A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP319083A JPS59128833A (ja) 1983-01-12 1983-01-12 受信機の回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP319083A JPS59128833A (ja) 1983-01-12 1983-01-12 受信機の回路

Publications (2)

Publication Number Publication Date
JPS59128833A true JPS59128833A (ja) 1984-07-25
JPH0137889B2 JPH0137889B2 (enrdf_load_stackoverflow) 1989-08-10

Family

ID=11550480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP319083A Granted JPS59128833A (ja) 1983-01-12 1983-01-12 受信機の回路

Country Status (1)

Country Link
JP (1) JPS59128833A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6002924A (en) * 1996-12-31 1999-12-14 Aor, Ltd. Full-spectrum all-mode radio receiver apparatus and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6002924A (en) * 1996-12-31 1999-12-14 Aor, Ltd. Full-spectrum all-mode radio receiver apparatus and method

Also Published As

Publication number Publication date
JPH0137889B2 (enrdf_load_stackoverflow) 1989-08-10

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