JPH01298745A - Semiconductor integrated circuit device having shielded multilayer wiring - Google Patents

Abstract

PURPOSE:To effectively prevent the malfunction of a circuit caused by cross talk, etc., and decrease the area of a chip, by shielding between adjacent wiring layers including signal lines with a conductive layer exclusively used for a neutral signal. CONSTITUTION:A metal layer 20 is formed on the whole surface above first layer wirings 12-14 through a layer insulating film 15. The metal layer 20 is connected to wiring 14 for a GND line through the through hole of the layer insulating film 15. Third layer metal wiring 22 is formed on the metal layer 20 through a layer insulating film 21 and a passivation film 23 is formed on the wiring 22. Forming the metal layer 20 on the whole surface and making the layer insulating films 15 and 21 of for example 1.2mum or more thickness respectively can reduce the parasitic capacity enough to ignore.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device having multilayer wiring, and in particular to a semiconductor integrated circuit device equipped with a shielding means for preventing malfunction of the circuit due to crosstalk between signal lines. It is related to.

(Prior Art) FIGS. 3 and 4 show an example of a conventional semiconductor integrated circuit device.

Field regions vi3, 4 separated by a field oxide film 2 are formed on the surface of a P-type silicon substrate l. In the field region 3, N+ diffusion regions 5 and 6 are formed, and on the channel region between both the diffusion regions 5 and 6, a gate electrode 7 made of polysilicon is provided via a gate oxide film to form an NMOS transistor. has been done. Similarly, in field region 4, N+ diffusion regions 8, 9
An NMOS transistor is formed by a polysilicon gate electrode 10 provided on a channel region between both diffusion regions 8 and 9 via a gate oxide film.

First metal interconnections 1'2, 13.14 are formed via an interlayer insulating film 11 such as a PSG film. The wiring 12 is connected to the diffusion region 8 through the contact hole of the interlayer insulating film 11.
This is the ffi source line that contacts the power source Vcc and supplies the power source Vcc. The wiring 13 is an output signal line that contacts the diffusion regions 6 and 9 of both MOS transistors through a contact hole in the interlayer insulating film 11, and leads an output signal to an output terminal (OUT). Further, the wiring 14 contacts the diffusion region 5 through the contact hole of the interlayer insulating film 11, and connects the diffusion region 5 to GND (
(GND) terminal is connected to the GND line.

On the first wiring layer, second metal wirings 16 and 17 are further formed via an interlayer insulating film 15 such as a PSG film. The wiring 16 is a clock signal line that supplies a clock signal (CLK).

The wiring 17 is a GND line, and is connected to the first layer GND wiring 14 through a contact hole in the interlayer insulating film 15. The wiring 17 is a wiring provided to prevent crosstalk.

23 is a passivation film.

In this example, wiring 13.16 is a signal line for normal signals, and in order to prevent crosstalk between wiring 13.16, GND line wiring 17 is placed between wiring 13.16 on a plane layout. .

(Problem to be Solved by the Invention) In the method of arranging the GND line wiring 17 so that the signal lines are shielded by a flat surface, the shield wiring 17 is on the same layer as any of the signal line wirings. This increases the wiring area and the chip area.

In addition, such shield wiring 17 must be consciously designed by the layout designer, and parts overlooked by the designer may not be properly shielded, which may cause circuit malfunctions due to crosstalk, etc. The incidence of defective semiconductor integrated circuit devices increases.

Furthermore, it is difficult to automatically design such shield wiring.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device equipped with a shielding mechanism that allows easy shielding between signal lines and does not increase the chip area.

(Means for Solving the Problems) In the present invention, a conductive layer exclusively for neutral signals is spread across the entire surface of the wiring layer except for through holes, with an insulating film interposed between adjacent wiring layers where signal lines are formed. Ru.

A neutral signal is a DC signal such as GND or power supply.

(Function) Signal lines in adjacent wiring layers are shielded from each other by a conductor layer dedicated to neutral signals provided between the wiring layers, thereby preventing crosstalk and the like.

(Example) Figure 1 is a plan view showing an example, and Figure 2 is a B-B thereof.
It is a cross-sectional view at the line position.

Two field regions 3° 4 are formed on the surface of the P-type substrate 1, and one field region 3 has an N″) diffusion region 5.
. and 1 car diffusion area 8,
An NMOS transistor is formed by a polysilicon gate electrode 10 provided in a channel region 1 between 9 and 9 with a gate oxide film interposed therebetween.

1st layer metal wiring via interlayer insulating film 11] 2.13
．． 14 are formed and connected to predetermined diffusion regions 8.9 and 6.5 through contact holes in interlayer insulating film 11, respectively. For example, the wiring 12 is a power supply line, the wiring 13 is an output signal line, and the wiring 14 is a GND line. The structure up to this point is the same as that in FIGS. 3 and 4.

A metal layer 20 is further formed over the entire surface of the first layer wirings 12, 13, and 14 with an interlayer insulating film 15 interposed therebetween. The metal layer 20 is connected to the GND line wiring 14 via a through hole in the interlayer insulating film 15.

A third layer of metal wiring 22 is further formed on the metal layer 20 with an interlayer insulating film 21 interposed therebetween.

The wiring 22 is, for example, a clock signal line. If it is necessary to connect the third layer wiring 22 with the first layer wiring,
Through holes are provided in the interlayer insulating film 15.21 and the metal layer 20 to form contacts.

A passivation film 23 is formed on the wiring 22.

By forming the metal layer 20 on the entire surface, parasitic containment occurs between the first layer signal line wiring 13 and the second layer metal layer 20, and the second layer 20 and the third layer signal line Although the parasitic capacitance between the wiring 22 and the wiring 22 may become a problem, the parasitic capacitance can be reduced to such an extent that it does not become a problem by making each interlayer insulating film +5° 21 1.2 μm or more, for example.

Although the embodiment has a three-layer wiring structure, the present invention can also be applied to a structure with five or more layers. In the case of a 5-layer sliding structure, for example, the second wiring layer is formed over the entire surface for GND, and the wiring layer for the fourth layer is also formed over the entire surface.
．． It can be used as a source. Further, the present invention can be similarly applied to multilayer structures.

(Effects of the Invention) In the present invention, since the space between adjacent wiring layers including signal lines is shielded with a conductor layer for neutral signal w, it is possible to effectively prevent circuit malfunctions due to crosstalk, etc. Chip area can be reduced.

Furthermore, since the conductor layer for shielding of the present invention is of a shape that is spread over the entire surface, it is difficult to arrange signal lines.

There is no need to consider crosstalk etc. when using a membrane meter.
Conventionally used CAD software for placement and wiring can be used.

[Brief explanation of the drawing]

The first part is a plan view showing one embodiment, and the second part is a plan view showing an example.
3 is a plan view showing a conventional semiconductor integrated circuit device, and FIG. 4 is a sectional view taken along line A--A in FIG. 3. 12.13.14...1st layer wiring, 15°21...Interlayer insulating film, 20...2nd layer G
ND metal layer, 22...3rd layer wiring.

Claims (1)

[Claims] (1) Between adjacent wiring layers where signal lines are formed,
A semiconductor integrated circuit device that has a conductor layer dedicated to neutral signals that is spread across the entire surface of the device, except for through holes, with an insulating film in between.