JPS63143843A - Power source wiring device for semiconductor integrated circuit - Google Patents
Power source wiring device for semiconductor integrated circuitInfo
- Publication number
- JPS63143843A JPS63143843A JP29174786A JP29174786A JPS63143843A JP S63143843 A JPS63143843 A JP S63143843A JP 29174786 A JP29174786 A JP 29174786A JP 29174786 A JP29174786 A JP 29174786A JP S63143843 A JPS63143843 A JP S63143843A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal layer
- semiconductor layer
- metal
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 90
- 229910052751 metal Inorganic materials 0.000 claims abstract description 90
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000003990 capacitor Substances 0.000 claims abstract description 16
- 230000001052 transient effect Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 6
- 108091006146 Channels Proteins 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、小型にして電圧変動の少ない安定性の高い半
導体集積回路装置の電源配線に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power supply wiring for a semiconductor integrated circuit device that is small in size and highly stable with little voltage fluctuation.
従来、半導体集積回路装置において、内部回路の動作に
必要な電源電圧は、電源パッドを介し、信号配線に使用
する金属配線に比較して幅の広い第２．第３の金属配線
を半導体基板上に形成した厚い酸化膜上に形成して伝え
られ、半導体基板上に形成したトランジスタ等内部素子
の所定の位置に分配していた。第７図に従来の電源線の
一構成例、第８図に第７図２０の拡大平面パターン図、
第９図に第７図２０の断面構造図を示す。図において１
は外部より電源電圧を供給するためのパッド、２は接地
電位を供給するためのパッド、３は入出力信号を供給、
とり出すためのパッド、３０５は人出力バツファに電源
電圧を供給するための第３の金属配線層で形成した電源
配線、３０５は入出力バッファに接地電位を供給するた
めの第３の金属配線層で形成した接地配線、３０３は内
部回路ブロックに電源電圧を供給するための第３の金属
配線層で形成した電源配線、３０３′は内部回路ブロッ
クに接地電位を供給するための第３の金属配線層で形成
した接地配線、３０４は内部回路ブロックに電源電圧を
供給するための第２の金属配線層で形成した電源配線、
３０４′は内部回路ブロックに接地電位を供給するため
の第２の金属配線層で形成した接地配線、３０２はトラ
ンジスタ等内部素子に電源電圧を供給するための第２の
金属配線層で形成した電源配線、３０２′はトランジス
タ等内部素子に接地電位を供給するための第２の金属配
線層で形成した接地配線、１００はｎ型半簿体基板、２
０１ 、２０２．２０３は半導体基板に形成した厚い絶
縁膜、ＩＯは第２の金属層と第３の金属層を接続するた
めの穴２０は第８図、第９図にその平面パターン図およ
び構造断面図をそれぞれ示す領域である。このように構
成されていたので、電源配線を形成する金属配線層が有
する寄生の抵抗成分、インダクタンス成分が内部回路の
動作に従って流れる過渡的な電流によって供給電源電位
の変動をもたらすという欠点があった。また、この問題
を回避するためには、電源配線を形成する第２．第３の
金属配線層の幅の広げ、寄生する抵抗成分、およびイン
ダクタンス成分を小とする必要が生じるが、これは電源
配線に必要な領域の面積拡大をもたらすという欠点があ
った。Conventionally, in a semiconductor integrated circuit device, the power supply voltage required for the operation of internal circuits is applied via a power supply pad to a second wire, which is wider than the metal wiring used for signal wiring. The third metal wiring was formed on a thick oxide film formed on the semiconductor substrate and distributed at predetermined positions of internal elements such as transistors formed on the semiconductor substrate. FIG. 7 shows an example of the configuration of a conventional power supply line, and FIG. 8 shows an enlarged planar pattern diagram of FIG. 7 20.
FIG. 9 shows a cross-sectional structural diagram of FIG. 720. In the figure 1
is a pad for supplying power supply voltage from the outside, 2 is a pad for supplying ground potential, 3 is a pad for supplying input/output signals,
305 is a power supply wiring formed of a third metal wiring layer for supplying a power supply voltage to the human output buffer; 305 is a third metal wiring layer for supplying a ground potential to the input/output buffer; 303 is a power supply wiring formed from a third metal wiring layer for supplying a power supply voltage to the internal circuit block, and 303' is a third metal wiring for supplying a ground potential to the internal circuit block. 304 is a power supply wiring formed from a second metal wiring layer for supplying power supply voltage to the internal circuit block;
304' is a ground wiring formed of a second metal wiring layer for supplying a ground potential to the internal circuit block, and 302 is a power supply formed of a second metal wiring layer for supplying power supply voltage to internal elements such as transistors. Wiring, 302' is a grounding wiring formed of a second metal wiring layer for supplying ground potential to internal elements such as transistors, 100 is an n-type semicircular substrate, 2
01, 202 and 203 are thick insulating films formed on the semiconductor substrate, IO is a hole 20 for connecting the second metal layer and the third metal layer, and the planar pattern diagram and structure thereof are shown in FIGS. 8 and 9. These are regions each showing a cross-sectional view. This configuration had the disadvantage that the parasitic resistance and inductance components of the metal wiring layer that formed the power supply wiring caused fluctuations in the supply potential due to transient currents flowing in accordance with the operation of the internal circuit. . In addition, in order to avoid this problem, it is necessary to form a second . Although it is necessary to increase the width of the third metal wiring layer and to reduce the parasitic resistance component and inductance component, this has the drawback of increasing the area required for the power supply wiring.
本発明の目的は、過渡的な電流による供給電源電圧の変
動を小型にして抑制する点を解決した電源配線を提供す
ることにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a power supply wiring in which fluctuations in supply voltage due to transient currents are reduced and suppressed.
本発明は従来未使用であった第７図３０３．３０３’お
よび３０４ 、３０４の金属電源配線層および接地配線
層直下の半導体基板内に大なる容量を同時に作り込み、
前記の容量を電源供給用金属配線に接続することを最も
主要な特徴とする。従来の技術とは、電源供給用金属配
線層直下の未使用領域を有効に利用し、前記領域に大な
る容量を作り込み、該金属配線と接続することによって
、該金属配線の幅を拡大することなく、該金属配線上を
流れる過渡的な電流によって生じる電圧変動を該大なる
容量の効果によって抑制する点が異なる。The present invention simultaneously creates a large capacitance in the semiconductor substrate directly under the metal power supply wiring layer and ground wiring layer of FIG.
The most important feature is that the capacitor is connected to the metal wiring for power supply. The conventional technology effectively utilizes the unused area directly under the power supply metal wiring layer, builds a large capacity in the area, and connects it to the metal wiring to expand the width of the metal wiring. The difference is that voltage fluctuations caused by transient current flowing on the metal wiring are suppressed by the effect of the large capacitance.
第１図は本発明の第１の実施例を説明する平面パターン
図、第２図はその構造断面図であって、第７図２０の部
分に相当する。１００はｎ型半導体基板、１０２は低濃
度ｐ型ウェル、１０３は高濃度ｎ型半導体層、１１０は
高濃度ｐ型チャネルストップ層、２０１は半導体基板表
面上の厚い酸化膜、２０１′は半導体基板表面上に形成
した薄いゲート酸化膜、２０２．２０３は異なる金属配
線層を絶縁する為の厚い酸化膜、３０１は容量を形成す
る為の第１の金属層、３０２．３０３は内部回路に電源
電圧を供給する為の第２、第３の金属配線層、１１は第
１の金属配線層と第２の金属配線層を接続する為の穴、
３０２ 、３０３’は内部回路に接地電位を供給する為
の第２．第３の金属配線層、１２は高濃度半導体層と第
２の金属配線層を形成する穴、ｌＯは第２．第３の金属
配線層を接続する穴である。このような構造になってい
るから、３０３′および３０２′から１０３を介して１
０２に接地電位を与え、３０３および３０２から３０１
へ電源電圧を与え、３０１．２０１’ 、１０２から構
成される容量を形成することができ、２０１は薄い酸化
膜であるから、大なる容量を３０２．３０３より構成さ
れる電源供給用金属配線に接続することが出来る。その
効果としては、電源配線上に流れる過渡的な電流による
電位変動をこの大なる容量によって抑制することができ
、該容量はこれら電源配線直下に形成されているから電
源配線領域の占有面積拡大を抑制することができる。FIG. 1 is a plane pattern diagram illustrating a first embodiment of the present invention, and FIG. 2 is a structural sectional view thereof, which corresponds to the portion shown in FIG. 7 and 20. 100 is an n-type semiconductor substrate, 102 is a low concentration p-type well, 103 is a high concentration n-type semiconductor layer, 110 is a high concentration p-type channel stop layer, 201 is a thick oxide film on the surface of the semiconductor substrate, 201' is a semiconductor substrate A thin gate oxide film formed on the surface, 202 and 203 a thick oxide film to insulate different metal wiring layers, 301 a first metal layer to form a capacitor, and 302 and 303 a power supply voltage for internal circuits. 11 is a hole for connecting the first metal wiring layer and the second metal wiring layer,
302 and 303' are second. 12 is a hole for forming a high concentration semiconductor layer and a second metal wiring layer; lO is a hole for forming a second metal wiring layer; This is a hole that connects the third metal wiring layer. Because of this structure, 1 is connected from 303' and 302' through 103.
02 is given a ground potential, and 303 and 302 to 301
By applying a power supply voltage to 301, 201', and 102, a capacitor composed of 301.201' and 102 can be formed. Since 201 is a thin oxide film, a large capacitance can be applied to the power supply metal wiring composed of 302, 303. Can be connected. The effect is that potential fluctuations caused by transient currents flowing on the power supply wiring can be suppressed by this large capacitance, and since the capacitance is formed directly under these power supply wirings, the area occupied by the power supply wiring area can be expanded. Can be suppressed.
第３図は本発明の第２の実施例を説明する平面パターン
図、第４図はその構造断面図であって、第７図２０の部
分に相当する。１００はｎ型半導体基板、１０２は低濃
度ｐ型ウェル、１０３は高濃度ｎ型半導体層、１０５は
高濃度ｎ型半導体層、１１０は高濃度チャネルストップ
層、２０１は半導体基板表面ヒの厚い酸化膜、２０１は
半導体基板表面上に形成した薄い酸化膜、２０２．２０
３は異なる金属配線層を絶縁する為の厚い酸化膜、３０
２．３０３は内部回路へ電源電圧を供給する為の第２．
第３の金属配線層、３０２ ’、 ３０３ ／は内部回
路へ接地電位を供給する為の第２．第３の金属配線層で
ある。このような構造になっているから、３０３′およ
び３０２′から１０３を介して１０２へ接地電位を与え
、３０３および３０２がら１０５へ電源電圧を与え、１
０５と１０２から構成される接合容量を形成することが
でき、該容量を電源供給用金属配線に接続することがで
きる。その効果としては前記第１の実施例と同一の効果
を提供することができる。FIG. 3 is a planar pattern diagram illustrating a second embodiment of the present invention, and FIG. 4 is a structural sectional view thereof, which corresponds to the portion shown in FIG. 7 and 20. 100 is an n-type semiconductor substrate, 102 is a low concentration p-type well, 103 is a high concentration n-type semiconductor layer, 105 is a high concentration n-type semiconductor layer, 110 is a high concentration channel stop layer, 201 is a thick oxidation layer on the semiconductor substrate surface Film, 201 is a thin oxide film formed on the surface of the semiconductor substrate, 202.20
3 is a thick oxide film for insulating different metal wiring layers, 30
2.303 is the second .303 for supplying power supply voltage to the internal circuit.
The third metal wiring layer 302', 303/ is a second metal wiring layer 302', 303/ for supplying a ground potential to the internal circuit. This is the third metal wiring layer. With this structure, the ground potential is applied from 303' and 302' to 102 via 103, the power supply voltage is applied from 303 and 302 to 105, and 1
A junction capacitor composed of 05 and 102 can be formed, and this capacitor can be connected to a power supply metal wiring. As for the effect, it is possible to provide the same effect as the first embodiment.
第５図は本発明の第３の実施例を説明する平面パターン
図、第６図はその構造断面図であって、１００はｎ型半
導体基板、１０２は低濃度ｐ型ウェル、１０３は高濃度
ｎ型半導体層、１０４は１０３より浅く形成されたｎ型
半導体層、１０５は１０３と同程度の深さに形成され１
０４と接続されたｎ型半導体層、２０１は半導体基板表
面に形成された厚い酸化膜、２０１′は半導体基板表面
に形成された薄い酸化膜、２０２．２０３は異なる金配
線層を絶縁する為の厚い酸化膜１，３０１は容量を形成
する為の第１の金属層、３０２ 、３０３は内部回路へ
電源電圧を供給する為の第２、第３の金属配線層、３０
２’ 、 ３０３ ’は内部回路へ接地電位を供給する
為の第２．第３の金属配線層である。このような構造に
なっているから、３０２およびび３０３から１０５を介
して１０４に電源電圧を与え、３０２および３０３′か
ら１０３を介して１０２に接地電位を与え、３０２／お
よび３０３′から３０１へ接地電位を与えることにより
、３０１．２０１’、１０４から形成される容量と、１
０４．１０２から形成される接合容量を電源配線に並列
に接続することが出来る。その効果としては、小型にし
て実施例１．実施例２よりさらに大なる容量を電源配線
に接続することができ、さらに電源電位の安定化を期待
することができる。FIG. 5 is a plane pattern diagram illustrating a third embodiment of the present invention, and FIG. 6 is a cross-sectional view of its structure, in which 100 is an n-type semiconductor substrate, 102 is a low concentration p-type well, and 103 is a high concentration An n-type semiconductor layer 104 is an n-type semiconductor layer formed shallower than 103, and 105 is an n-type semiconductor layer formed to the same depth as 103.
201 is a thick oxide film formed on the surface of the semiconductor substrate, 201' is a thin oxide film formed on the surface of the semiconductor substrate, 202 and 203 are for insulating different gold wiring layers. A thick oxide film 1, 301 is a first metal layer for forming a capacitor, 302, 303 is a second and third metal wiring layer for supplying a power supply voltage to an internal circuit, 30
2' and 303' are the second .2' and 303' for supplying the ground potential to the internal circuit. This is the third metal wiring layer. With this structure, power supply voltage is applied from 302 and 303 to 104 through 105, ground potential is applied from 302 and 303' to 102 through 103, and from 302/ and 303' to 301. By applying a ground potential, the capacitance formed from 301.201', 104 and 1
The junction capacitance formed from 04.102 can be connected in parallel to the power supply wiring. As for the effect, Example 1. A larger capacitance can be connected to the power supply wiring than in Example 2, and further stabilization of the power supply potential can be expected.
上記の実施例おいて、第１の導電型としてｎ型、第２の
４電型としてｐ型を用いた場合について説明したが、第
１の導電型としてｐ型、第２の導電型としてｎ型を用い
、接続法をかえた場合も容易に類推され゛る。さらに第
２．第３の金属層より上層にも電源配線があった場合も
同様である。In the above embodiment, a case was explained in which n type was used as the first conductivity type and p type was used as the second quaternary conductivity type, but p type was used as the first conductivity type and n type was used as the second conductivity type. It can also be easily inferred by using types and changing the subjunctive method. Furthermore, the second. The same applies when there is a power supply wiring in a layer above the third metal layer.
尚、本実施例は通常のＣＭＯＳプロセスで実現可能であ
り、特に第３の実施例１０４の半導体層はチャネルドー
プの工程と共用化できる。Note that this embodiment can be realized by a normal CMOS process, and in particular, the semiconductor layer of the third embodiment 104 can be used in common with the channel doping process.
以上説明したように、従来金属配線層のみで形成してい
た電源配線、接地配線直下の半導体基板は未使用であっ
たが、この部分に大なる容量を容易に形成することがで
き、該容量を電源配線に容易に接続することができるか
ら、内部回路の動作に伴なう過渡的に流れる電源電流に
よって生じる電源変動を小面積にして安定化できるとい
う利点がある。As explained above, the semiconductor substrate directly below the power supply wiring and ground wiring, which were conventionally formed only with metal wiring layers, was unused, but it is possible to easily form a large capacitance in this area, and the capacitance Since it can be easily connected to the power supply wiring, there is an advantage that power fluctuations caused by transient power supply current flowing due to the operation of the internal circuit can be stabilized in a small area.
また、本電源配線形成には回路間を接続するための第２
．第３の金属配線層を必要とすることがないから、回路
間を接続する信号線の配線は特別な制約を課する必要が
ないという利点がある。In addition, in this power supply wiring formation, a second
．． Since there is no need for a third metal wiring layer, there is an advantage that there is no need to impose any special restrictions on the wiring of signal lines connecting circuits.
第１図は年発明の特徴を最も良く表わしている第１の実
施例の平面パターン図、第２図は本発明第１の実施例の
構造断面図、第３図は本発明の特徴を最もよく表わして
いる第２の実施例の平面パターン図、第４図は本発明第
２の実施例の構造断面図、第５図は本発明の特徴を最も
よ（表わしている第３の実施例の平面パターン図、第６
図は本発明第３の実施例の構造断面図である。
第７図は従来から用いられている半導体集積回路の電源
配線、接地配線の一構成例、第８図は金属配線層のみを
備えた従来の電源、接地配線の平面パターン図、第９図
は従来の電源配線部の構造断面を示す。
図において、
ｌ・・・電源電圧供給用パッド、２・・・接地電位供給
用パッド、３・・・入出力信号接続パッド、ｌＯ・・・
第２の金属層と第３の金属層を接続する穴、１１・・・
第１の金属層と第２の金属層を接続する穴、１２−・・
高濃度半導体層と第２の金属層を接続する穴、２０・・
・第１図〜第５図及び第８図、第９図に示す部分を示す
領域、１００−・・第１の半導体層（ｎ型基板）、１０
２・・・第２の半導体層（ｐ型ウェル） 、１０３・・
・第３の半導体層（ｐ型半導体層） 、１０４−・・第
５の半導体層（）ｌいｎ型半導体層） 、１０５・・・
第４の半導体層（ｎ型半導体層） 、１１０・・・チャ
ネルストップ（ｐ型半導体層） 、２０１・・・半導体
表面上の厚い酸化膜、２０１′・・・半導体表面の薄い
酸化膜、２０２・・・第１の金属層と第２の金属層を絶
縁する酸化膜、２０３・・・第２の金属層と第３の金属
層を絶縁する酸化膜、３０１・・・第１の金属層、３０
２−・・第２の金属層（電源電位） 、３０２’・・・
第２の金属層（接地電位）、３０３・・・第３の金属層
（電源電位） 、３０３’・・・第３の金属Ｂ５（接地
電位）
特許出願人 日本電信電話株式会社
代理人 弁理士 玉 蟲 久五部
（外２名）
第 ５ 図
第 ６ 図
第 ８ 図
第 ９ 図Fig. 1 is a plane pattern diagram of the first embodiment that best represents the features of the invention, Fig. 2 is a structural sectional view of the first embodiment of the invention, and Fig. 3 shows the features of the invention best. FIG. 4 is a structural sectional view of the second embodiment of the present invention, and FIG. 5 is a plan pattern diagram of the second embodiment that best represents the features of the present invention. Plane pattern diagram, No. 6
The figure is a structural sectional view of a third embodiment of the present invention. Fig. 7 is an example of a configuration of a conventional power supply wiring and ground wiring of a semiconductor integrated circuit, Fig. 8 is a planar pattern diagram of a conventional power supply wiring and ground wiring having only a metal wiring layer, and Fig. 9 is a A structural cross-section of a conventional power supply wiring section is shown. In the figure, l...pad for power supply voltage supply, 2... pad for ground potential supply, 3... input/output signal connection pad, lO...
A hole connecting the second metal layer and the third metal layer, 11...
A hole connecting the first metal layer and the second metal layer, 12-...
A hole connecting the high concentration semiconductor layer and the second metal layer, 20...
・Region showing the parts shown in FIGS. 1 to 5 and FIGS. 8 and 9, 100--First semiconductor layer (n-type substrate), 10
2... Second semiconductor layer (p-type well), 103...
- Third semiconductor layer (p-type semiconductor layer), 104-... Fifth semiconductor layer (n-type semiconductor layer), 105...
Fourth semiconductor layer (n-type semiconductor layer), 110... Channel stop (p-type semiconductor layer), 201... Thick oxide film on semiconductor surface, 201'... Thin oxide film on semiconductor surface, 202 ... Oxide film insulating the first metal layer and the second metal layer, 203 ... Oxide film insulating the second metal layer and the third metal layer, 301 ... First metal layer , 30
2-...Second metal layer (power supply potential), 302'...
Second metal layer (ground potential), 303...Third metal layer (power supply potential), 303'...Third metal B5 (ground potential) Patent applicant Nippon Telegraph and Telephone Corporation Agent Patent attorney Tamamushi Kugobe (2 others) Figure 5 Figure 6 Figure 8 Figure 9
Claims (1)
層と、前記の半導体基板の主表面の一部領域に形成され
た第２の導電型のウェル領域を形成する第２の半導体層
と、前記のウェル領域内の一部に形成されたウェル深さ
より充分浅い、高濃度の第２の導電型の第３の半導体層
と、これら前記の半導体表面上部に設けた薄い第１の絶
縁膜と、前記絶縁膜表面上部に設け、前記の第３の半導
体層と一定の距離を設けた第１の金属層と、前記金属層
をおおう厚い第２の絶縁膜と、前記の絶縁膜表面上部に
設けた第２の金属層と、前記金属層と第３の厚い絶縁膜
を介して設けた第３の金属層を備え、第３の半導体層上
で第１、第２の絶縁膜に所定の大きさの穴を設け、第２
の金属層と第３の半導体層を接続し、第１の金属層上で
第２の絶縁膜に所定の大きさの穴を設け、第１の金属層
と第２の金属層を接続し、第３の半導体層に接続される
第２の金属層を接地電位とし、第１の金属層に接続され
る第２の金属層を他方の電源電位とし、第２の金属層上
で第３の絶縁膜の所定の位置に所定の大きさの穴を設け
、２つの異なる第３の金属層をこの穴を介してそれぞれ
接地電位である第２の金属層と他方の電源電位にある第
２の金属層に接続し、第２、第３の金属層で形成される
電源配線直下にＰウェル、第１の絶縁膜、第１の金属層
で形成される容量を接続することを特徴とする半導体集
積回路電源配線装置。 ２、前記特許請求範囲第１項において、前記ウェル領域
内の一部に前記第３の半導体層と所定の距離を設けて形
成した第１の導電型の第４の半導体層を設け、第１の金
属層をとり払い、第１、第２の酸化膜に所定の大きさの
穴を設け、電源電位にある第２の金属層と該第４の半導
体層を接続し、該第４の半導体層で形成される接合容量
を第２、第３の金属層で形成される電源配線直下でこれ
と接続することを特徴とする半導体集積回路電源配線装
置。 ３、前記特許請求範囲第２項において、第１の導電型の
第４の半導体層を第３の半導体層より、より薄く形成し
、前記第４の半導体層に隣接して、第３の半導体層とほ
ぼ同一の深さを有する第１の導電型の第５の半導体層を
形成して、第４の半導体層と接続し、前記特許請求範囲
第１項と同様に前記の第４の半導体層表面上部に第１の
薄い絶縁膜を介して第１の金属層を設け、前記第１の金
属層を接地電位にある第２、第３の金属層と接続し、第
５の半導体層を電源電位にある第２、第３の金属層と接
続させ、第２、第３の金属層で形成される電源配線直下
に、第１の金属層と第５の半導体層で形成される容量お
よび第５の半導体層と第２の半導体層で形成される容量
を第２、第３の金属配線層で形成される電源配線に並列
に接続することを特徴とする半導体集積回路電源配線装
置。[Claims] 1. A first semiconductor layer forming a semiconductor substrate of a first conductivity type, and a well region of a second conductivity type formed in a partial region of the main surface of the semiconductor substrate. a second semiconductor layer to be formed, a highly concentrated third semiconductor layer of a second conductivity type that is sufficiently shallower than the well depth formed in a part of the well region, and a third semiconductor layer of a second conductivity type with a high concentration, and a thin first insulating film provided, a first metal layer provided above the surface of the insulating film and provided at a certain distance from the third semiconductor layer, and a thick second insulating film covering the metal layer. a second metal layer provided above the surface of the insulating film; a third metal layer provided via the metal layer and a third thick insulating film; , a hole of a predetermined size is provided in the second insulating film, and the second
connecting the metal layer and the third semiconductor layer, forming a hole of a predetermined size in the second insulating film on the first metal layer, and connecting the first metal layer and the second metal layer; A second metal layer connected to the third semiconductor layer is set to a ground potential, a second metal layer connected to the first metal layer is set to the other power supply potential, and a third A hole of a predetermined size is provided at a predetermined position in the insulating film, and two different third metal layers are connected through the hole to the second metal layer at the ground potential and the second metal layer at the other power supply potential. A semiconductor characterized in that a capacitor formed of a P-well, a first insulating film, and a first metal layer is connected to a metal layer and directly below a power supply wiring formed of a second and third metal layer. Integrated circuit power wiring equipment. 2. In claim 1, a fourth semiconductor layer of the first conductivity type formed at a predetermined distance from the third semiconductor layer is provided in a part of the well region; remove the metal layer, make holes of a predetermined size in the first and second oxide films, connect the second metal layer at the power supply potential and the fourth semiconductor layer, and connect the fourth semiconductor layer to the fourth semiconductor layer. 1. A semiconductor integrated circuit power supply wiring device, characterized in that a junction capacitance formed by a layer is connected to a power supply wiring formed by a second and third metal layer directly below the power supply wiring. 3. In claim 2, the fourth semiconductor layer of the first conductivity type is formed thinner than the third semiconductor layer, and the third semiconductor layer is formed adjacent to the fourth semiconductor layer. A fifth semiconductor layer of the first conductivity type having substantially the same depth as the fourth semiconductor layer is formed and connected to the fourth semiconductor layer. A first metal layer is provided on the layer surface through a first thin insulating film, the first metal layer is connected to the second and third metal layers at ground potential, and a fifth semiconductor layer is formed. A capacitor and a capacitor formed by the first metal layer and the fifth semiconductor layer are connected to the second and third metal layers at the power supply potential, and directly under the power supply wiring formed by the second and third metal layers. A semiconductor integrated circuit power wiring device characterized in that a capacitor formed by a fifth semiconductor layer and a second semiconductor layer is connected in parallel to a power wiring formed by second and third metal wiring layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29174786A JPS63143843A (en) | 1986-12-08 | 1986-12-08 | Power source wiring device for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29174786A JPS63143843A (en) | 1986-12-08 | 1986-12-08 | Power source wiring device for semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63143843A true JPS63143843A (en) | 1988-06-16 |
Family
ID=17772884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29174786A Pending JPS63143843A (en) | 1986-12-08 | 1986-12-08 | Power source wiring device for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63143843A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02302074A (en) * | 1989-05-16 | 1990-12-14 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
| US5684304A (en) * | 1993-12-27 | 1997-11-04 | Sgs-Thomsn Microelectronics S.A. | Structure for testing integrated circuits |
| EP0817272A2 (en) * | 1996-06-26 | 1998-01-07 | Oki Electric Industry Co., Ltd. | Integrated circuit |
-
1986
- 1986-12-08 JP JP29174786A patent/JPS63143843A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02302074A (en) * | 1989-05-16 | 1990-12-14 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
| US5684304A (en) * | 1993-12-27 | 1997-11-04 | Sgs-Thomsn Microelectronics S.A. | Structure for testing integrated circuits |
| EP0817272A2 (en) * | 1996-06-26 | 1998-01-07 | Oki Electric Industry Co., Ltd. | Integrated circuit |
| EP0817272A3 (en) * | 1996-06-26 | 1998-05-06 | Oki Electric Industry Co., Ltd. | Integrated circuit |
| US6121645A (en) * | 1996-06-26 | 2000-09-19 | Oki Electric Ind Co Ltd | Noise-reducing circuit |
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