JPS62244160A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62244160A JPS62244160A JP8872086A JP8872086A JPS62244160A JP S62244160 A JPS62244160 A JP S62244160A JP 8872086 A JP8872086 A JP 8872086A JP 8872086 A JP8872086 A JP 8872086A JP S62244160 A JPS62244160 A JP S62244160A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- inductor
- substrate
- wirings
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 abstract description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F2017/0046—Printed inductances with a conductive path having a bridge
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体集積回路に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit.
従来、半導体基板上にトランジスタと、仁のトランジス
タに接続されるようく形成したインダクタ配線および抵
抗とから成る半導体集積回路において、このインダクタ
配線およびこれに接続されるように形成した抵抗の構造
を第８回国ないしく胸に示す。第３回国ないし１ＢＩＦ
ｉ、従来例による構造の平面図および、同回国の要部断
面図である。Conventionally, in a semiconductor integrated circuit consisting of a transistor on a semiconductor substrate, and an inductor wiring and a resistor formed to be connected to the underlying transistor, the structure of the inductor wiring and the resistor formed to be connected to the inductor wiring is Show it to the country or chest 8 times. 3rd Country or 1BIF
i, a plan view of a structure according to a conventional example, and a sectional view of a main part of the same country;
この従来例においては、例えばＧａＡａなどの半導体基
板１１３の表面部に、同回国に示すような、インダクタ
として動作するパターンを有し、金属薄膜で形成され九
インダクタ配線（２Ｉと、所定の電子濃旋を有する抵抗
層（３）とを有し、前記インダクタ配線８と前記抵抗層
８を、例えば空気などの絶縁層（６）で前記インダクタ
配線（！１との交叉部分を絶縁して、図示しなめトラン
ジスタに接続される配線金属（６１により接続した構造
をもつものである。In this conventional example, the surface of a semiconductor substrate 113 made of, for example, GaAAa has a pattern that operates as an inductor, as shown in the same issue, and is formed of a metal thin film with nine inductor wiring (2I and a predetermined electron concentration). The inductor wiring 8 and the resistance layer 8 are insulated at their intersections with the inductor wiring (!1) with an insulating layer (6) made of air, for example. It has a structure in which the wiring metal (61) is connected to the diagonal transistor.
〔発明が解決しようとする問題点）
しかしながら、前記従来例による半導体装置にお−ては
、第８回国に示したように、インダクタ配線（２）と抵
抗層１３＋の占有面積が大きく、集積化の点で不利であ
る。[Problems to be Solved by the Invention] However, in the semiconductor device according to the conventional example, as shown in the 8th National Conference, the area occupied by the inductor wiring (2) and the resistance layer 13+ is large, and it is difficult to integrate the semiconductor device. It is disadvantageous in this respect.
また、絶縁層１６）の絶縁破壊の可能性もあり、信頼性
向上を図る上で問題が生じ易いと共に、製造工程も複雑
であるという欠点を有している。Further, there is a possibility of dielectric breakdown of the insulating layer 16), which tends to cause problems in improving reliability, and has the disadvantage that the manufacturing process is complicated.
この発明は、上記従来例の半導体装置のもつ欠点を改善
しようとするもので、パターンの必要上する面積が少な
く、信頓性が高く、かつ工作も容易である構造の半導体
装置’に提供することを目的とする。The present invention aims to improve the drawbacks of the conventional semiconductor devices described above, and provides a semiconductor device with a structure that requires less area for a pattern, has high reliability, and is easy to work with. The purpose is to
前記目的を達成するために、この発明による半導体装置
は、半導体基板の表面上に形成するインダクタ配線と、
このインダクタ配線と接続され、かつ重畳されるように
、前記半導体基板内に形成される抵抗層とを備えたもの
である。In order to achieve the above object, a semiconductor device according to the present invention includes an inductor wiring formed on a surface of a semiconductor substrate;
The device includes a resistance layer formed within the semiconductor substrate so as to be connected to and overlap the inductor wiring.
この発明における半導体装置は、半導体基板表面に形成
したインダクタ配線と、半導体基板内に形成した抵抗層
を重畳させているから集積化の点で有利であり、また、
インダクタ配線と配線金属との交叉がな−ので、信頓性
が向上し、同時に、製造工程の数も減らすことができる
。The semiconductor device according to the present invention is advantageous in terms of integration because the inductor wiring formed on the surface of the semiconductor substrate and the resistance layer formed inside the semiconductor substrate are overlapped, and
Since there is no crossover between the inductor wiring and the wiring metal, reliability is improved and at the same time, the number of manufacturing steps can be reduced.
以下、この発明に係る半導体装置の一実施例につき第１
回置ないしｉＢｌを参照して詳細に説明する。Hereinafter, the first embodiment of the semiconductor device according to the present invention will be described.
This will be explained in detail with reference to rotation or iBl.
第１回置ないしｉＢｌは、この実施例による、インダク
タ線路とこのインダクタ線路に接続された抵抗層とから
なる半導体装置を示す平面図および同回国の要部断面図
である。この実施例の半導体装置は、例えばＧａＡｓな
どの半導体基板１．１’ｌの表面部にあって、インダク
タとして作用するパターンを有し、金属薄膜で形成した
インダクタ配線（！１と、前記インダクタ配線＋２１と
その一端子で接続され、かつ重畳されるように形成され
、前記半導体基板１１）内にあプ、例えばｎ形の導電性
で所定の電子濃度を有する抵抗層（３）と、前記抵抗層
（３１と前記インダクタ配線（意）および図示しなめト
ランジスタに接続される配線金Ｘ （６１との所定の接
続部に前記抵抗層＋３１よシミ子濃度が高（同じ導電形
を有するｎ十形層（４）とから成るものである。1A to 1B are a plan view and a sectional view of a main part of the same embodiment, respectively, showing a semiconductor device including an inductor line and a resistance layer connected to the inductor line, according to this embodiment. The semiconductor device of this embodiment has a pattern that acts as an inductor on the surface of a semiconductor substrate 1.1'l made of, for example, GaAs, and has an inductor wiring (!1) formed of a metal thin film and an inductor wiring (! +21 and one terminal of the resistor layer (3), which is formed so as to be overlapped with the resistor layer (3), and which is formed in the semiconductor substrate 11) and has, for example, n-type conductivity and a predetermined electron concentration; The resistor layer +31 has a higher smear concentration (n-type wire having the same conductivity type) at a predetermined connection portion with the layer (31) and the inductor wire (not shown) and the wiring gold X (61) connected to the not shown transistor. It consists of a layer (4).
かかる構造の半導体装置におｈては、インダクタとして
動作するインダクタ配線（！１と、抵抗層１１１を重畳
させて構成し、ｎ十形層ｉ４＋によ）、インダクタ線路
（引及び配線金属ｔｓ＞と抵抗層（３）′とのオーミッ
ク性接合を行なって−るので、パターン占有面積の少な
いインダクタと抵□抗との接続回路ｔ−英現している・
なお、前記実施例にお−ては、ｎ形の抵抗層ｔｓｔと、
オーミック性接合をもたせるためのｎ十層（４）を用−
る場合について述べたが、ｐ形の抵抗層とｐ十層ａ瞼も
同様である。また、前記実施例においては、Ｇａム−基
板を用−る場合にクーで述べたが、必ずしもこれに限定
されるものではなく、ｘｎＰなどその他の半導体基板を
用いる場合にも適用でき仁とは言うまでもな−。In a semiconductor device h having such a structure, an inductor wiring (!1 and a resistance layer 111 are overlapped to form an n-shaped layer i4+) which operates as an inductor, an inductor line (wire and wiring metal ts> Since an ohmic connection is made between the inductor and the resistor layer (3)', a connection circuit between the inductor and the resistor that occupies a small pattern area is formed. , an n-type resistance layer tst,
Using n10 layers (4) to provide ohmic contact.
Although the case has been described above, the same applies to the p-type resistance layer and the p-layer alid. Furthermore, although the above embodiments have been described in terms of the case where a Ga semiconductor substrate is used, the invention is not necessarily limited to this, and can also be applied to cases where other semiconductor substrates such as xnP are used. Needless to say.
以上のようｋこの発明の半導体装置によれば、インダク
タ配線とこれに接続され、かり、重畳されるように抵抗
層を半導体基板内に設けたので、パターン面積を少なく
シ、信頓性が高く、製造工程も少なくすることができる
という効果がある。As described above, according to the semiconductor device of the present invention, since the resistance layer is provided in the semiconductor substrate so as to be connected to and overlapped with the inductor wiring, the pattern area is reduced and the reliability is high. This has the effect of reducing the number of manufacturing steps.
第１回置ないしく瞬はこの発１ｊｌｌＫ係る半導体装置
の構造の一実施例を示すそれぞれ平面図および断面図、
第８回国ないし四は従来例の半導体装置を示すそれぞれ
平面図および断面図である。
＋１１はＧａＡ−基板（半導体基板） ％ ｌ！＋はイ
ンダクタ配線、ＩＩＩはｎ形紙抗層、１４） ｌｌ１ｎ
＋形層、（Ｉ）は配線金員、（６）は絶縁層である。
なお、図中同一符号はそれぞれ同一または相当部分を示
す。The first or second part is a plan view and a cross-sectional view showing an example of the structure of a semiconductor device, respectively,
Nos. 8 to 4 are a plan view and a sectional view, respectively, showing conventional semiconductor devices. +11 is GaA-substrate (semiconductor substrate) % l! + is inductor wiring, III is n-type paper layer, 14) ll1n
+ type layer, (I) is a wiring member, and (6) is an insulating layer. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
スタと接続されると共に、前記半導体基板の表面上に形
成されるインダクタ配線ととこのインダクタ配線と接続
され、かつ、重畳されるように、前記半導体基板内に形
成される抵抗層とを備えた半導体装置。A transistor formed on a semiconductor substrate, an inductor wiring formed on the surface of the semiconductor substrate that is connected to the transistor, and an inductor wiring formed on the surface of the semiconductor substrate. A semiconductor device comprising: a resistive layer formed in a semiconductor device;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8872086A JPS62244160A (en) | 1986-04-17 | 1986-04-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8872086A JPS62244160A (en) | 1986-04-17 | 1986-04-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62244160A true JPS62244160A (en) | 1987-10-24 |
Family
ID=13950738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8872086A Pending JPS62244160A (en) | 1986-04-17 | 1986-04-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62244160A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5095357A (en) * | 1989-08-18 | 1992-03-10 | Mitsubishi Denki Kabushiki Kaisha | Inductive structures for semiconductor integrated circuits |
| US5557138A (en) * | 1993-11-01 | 1996-09-17 | Ikeda; Takeshi | LC element and semiconductor device |
| US5629553A (en) * | 1993-11-17 | 1997-05-13 | Takeshi Ikeda | Variable inductance element using an inductor conductor |
| US6285069B1 (en) * | 1998-04-10 | 2001-09-04 | Nec Corporation | Semiconductor device having improved parasitic capacitance and mechanical strength |
| US8766390B2 (en) | 2011-06-10 | 2014-07-01 | Fujitsu Limited | Light-receiving device, light receiver using same, and method of fabricating light-receiving device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS501692A (en) * | 1973-05-07 | 1975-01-09 | ||
| JPS5198990A (en) * | 1975-02-18 | 1976-08-31 | ||
| JPS5327376A (en) * | 1976-08-26 | 1978-03-14 | Nippon Telegr & Teleph Corp <Ntt> | Forming method of high resistanc e layer |
-
1986
- 1986-04-17 JP JP8872086A patent/JPS62244160A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS501692A (en) * | 1973-05-07 | 1975-01-09 | ||
| JPS5198990A (en) * | 1975-02-18 | 1976-08-31 | ||
| JPS5327376A (en) * | 1976-08-26 | 1978-03-14 | Nippon Telegr & Teleph Corp <Ntt> | Forming method of high resistanc e layer |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5095357A (en) * | 1989-08-18 | 1992-03-10 | Mitsubishi Denki Kabushiki Kaisha | Inductive structures for semiconductor integrated circuits |
| US5557138A (en) * | 1993-11-01 | 1996-09-17 | Ikeda; Takeshi | LC element and semiconductor device |
| US5629553A (en) * | 1993-11-17 | 1997-05-13 | Takeshi Ikeda | Variable inductance element using an inductor conductor |
| US6285069B1 (en) * | 1998-04-10 | 2001-09-04 | Nec Corporation | Semiconductor device having improved parasitic capacitance and mechanical strength |
| US6383889B2 (en) | 1998-04-10 | 2002-05-07 | Nec Corporation | Semiconductor device having improved parasitic capacitance and mechanical strength |
| US8766390B2 (en) | 2011-06-10 | 2014-07-01 | Fujitsu Limited | Light-receiving device, light receiver using same, and method of fabricating light-receiving device |
| US9243952B2 (en) | 2011-06-10 | 2016-01-26 | Fujitsu Limited | Light-receiving device, light receiver using same, and method of fabricating light-receiving device |
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