JPH036853A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a noise induced in the grounding line of a first circuit block from leaking through the element isolation region of that circuit block and the element isolation region of the other circuit block such as a second circuit block by a method wherein the grounding line of the first circuit block and the element isolation region corresponding to the first circuit block are separated from each other. CONSTITUTION:The grounding potential point of a first circuit block 11 in which a relatively large noise is induced in its grounding potential is connected to a first grounding potential terminal 2 and, further, an element isolation region 7 corresponding to the first circuit block 11 is connected to a second grounding potential terminal 3 corresponding to a second circuit block 12 whose grounding potential is relatively stable or to an independent third grounding potential terminal to prevent the noise induced in the grounding line of the first circuit block 11 from leaking through the corresponding element isolation region and the element isolation region of the other circuit block such as a second circuit block.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and in particular, to a semiconductor integrated circuit device, which has an element isolation region using a PN junction, and which has a circuit that handles a large amplitude signal and a circuit that handles a small signal. The present invention relates to a technology that is effective for use in built-in monolithic semiconductor integrated circuit devices.

[Conventional technology]

Crosstalk between circuits refers to the propagation of signals from any circuit through parasitic paths such as resistance or capacitance, and other signals are superimposed on the signal that should be processed, resulting in the signal being processed by the signal circuit. This is a phenomenon that is amplified depending on the gain, frequency characteristics, etc. of the system and causes problems in the system. As an example of the prior art related to countermeasures against crosstalk between circuits in a monolithic semiconductor integrated circuit device, there is published No. 5G-51857.

[Problem to be solved by the invention]

In the conventional general design method for preventing crosstalk, for example, as shown in FIG. 4, when a circuit with a relatively large signal amplitude, such as an oscillation circuit VCO, and a small signal circuit are configured in the same semiconductor integrated circuit device. , the ground potential points of the VCO circuit 11 and the small signal circuit 12 are connected to independent ground terminals 2.
and 3.

At this time, the ground potential applied to the element isolation region of each circuit block is also connected to the ground potential point of each corresponding circuit block. That is, a diffusion layer (S
A diffusion layer (SU) 9 is connected to the ground terminal 2 corresponding to the circuit block 11 and provides ohmic contact with the element isolation region corresponding to the small signal circuit 12.
B) 9 is connected to the ground terminal 3 corresponding to the circuit block 12.

However, research by the present inventors has revealed that such a configuration causes a problem in that crosstalk occurs via the substrate resistance R1 as shown by the dotted line in the figure. That is, as shown in the equivalent circuit diagram of FIG.
On the O circuit 11 side, the signal amplitude is, for example, 1 to 2 V.
This is relatively large, and a noise of about 60 mV is generated by the power supply wiring resistance R2 and the like in response to the current change according to the oscillation operation. This noise is transmitted to the contact diffusion layer 9 in the element isolation region through the internal wiring. This element isolation region is electrically connected to the semiconductor substrate, and is connected to the contact diffusion layer 9 of the element isolation region of the 12 examples of circuit blocks via the substrate resistor R1.

Therefore, if the substrate resistance R2 is about 10Ω and the wiring resistance R3 on the circuit block 12 side (resistance value of the ground wire from the bonding pad) is about 2Ω, the ground potential noise on the small signal side will be about 10mV. . Therefore, if this noise is attenuated to, for example, 80% and propagated to the input line of the amplifier circuit AMP, and the gain of the amplifier circuit is 20 times, a noise of 160 mV will appear in the output.

An object of the present invention is to provide a semiconductor integrated circuit device that prevents crosstalk via substrate resistance.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the ground potential point of the first circuit block where relatively large noise occurs in the ground potential of the circuit is connected to the first ground potential terminal, and the element isolation region corresponding to the first circuit block is connected to the ground potential. is connected to a second ground potential terminal corresponding to a relatively stable second circuit block or to an independent third ground potential terminal, or placed in a high impedance state.

[For production]

According to the above-mentioned means, since the ground line of the first circuit block and the corresponding element isolation region are separated,
Noise generated in the ground line can be prevented from leaking through the element isolation region and the element bone HTJ region of other circuits such as the substrate and the second circuit block.

〔Example〕

FIG. 1 shows a schematic chim layout pattern of a basic embodiment of a semiconductor integrated circuit device according to the present invention.

The semiconductor integrated circuit device shown in the figure is formed using a single semiconductor substrate such as single crystal silicon by a known monolithic bipolar IC manufacturing technique.

Although not particularly limited, the semiconductor integrated circuit device of this example constitutes a color signal processing circuit for a video printer, and is a voltage controlled oscillation circuit (hereinafter simply referred to as VCO) that oscillates at 3 fsc (3 x 3° 58 MHz). omitted)
and a small signal circuit 12 that processes a color signal using the signal rsc.

The VCO circuit 11 and the small signal circuit 12 are separated by an isolation region 7 as indicated by diagonal lines. In the case of a monolithic IC, each element is separated by an isolation region, except for those in which the collector is shared as is well known. is shown illustratively as a representative.

In the isolation 7 of the VCO circuit 11, a relatively highly doped diffusion layer 9 is formed to obtain ohmic contact, as shown by the two-dot chain line in the figure. As this diffusion layer, a BR diffusion layer (also called SUB extraction) is used, which is formed by the same process as the base region of a bipolar transistor or a diffused resistor using a base region. In the figure, the BR diffusion layer 9 is drawn so as to protrude from the isolation region 7 in order to clearly show its existence, but it is actually formed within the isolation region 7. In this embodiment, although not particularly limited, of the isolation 7 forming a rectangle corresponding to the 100 circuits 11, the BR diffusion layer is formed in a U-shape on the side facing the small signal circuit 12 and on both sides sandwiching it. It is formed.

The ground potential of the VCO circuit is provided by a wiring 6 extending from a bonding pad 2 for an independent external terminal. Further, the operating voltage Vcc of the vCO circuit 11 is provided by a wiring 6 extending from a bonding pad 4 for an external terminal. The voltage Vcc is also applied to the collector buried layer 8 via the wiring 6 as required.

On the other hand, in the isolation 7 of the small signal circuit 12, a relatively highly doped diffusion layer 9 is formed to obtain an ohmic contact, as shown by the two-dot chain line in the figure. As this diffusion layer, a BR diffusion layer (also referred to as SUB extraction) is used, which is formed in the same process as the base region of a bipolar transistor or a diffusion resistor using a base region, as described above. In the figure, the BR diffusion layer 9 is drawn protruding from the isolation region 7 as described above, but it is actually formed within the isolation neck region. In this example, although not particularly limited,
Of the isolation 7 forming a rectangle corresponding to the small signal circuit 12, the BR diffusion layer is formed on a side close to the bonding pad 3 that provides a ground potential.

The ground potential of the small signal circuit 12 is provided by a wiring 6 extending from a bonding pad 3 for an independent external terminal. In this embodiment, the ground potential is also applied to the BR diffusion layer 9 formed in the isolation 7 through the wiring 6 at the same time.

Furthermore, the wiring extending upward from the bonding pad 3 is formed so as to overlap the U-shaped BR diffusion layer on the CO circuit side, and the ground potential from the pad 3 side is applied here as well. Further, the operating voltage Vcc of the small signal circuit 12 is provided by a wiring 6 extending from a bonding pad 5 for an external terminal. The voltage Vcc is also applied to the collector buried layer 8 via the wiring 6 as required.

In this embodiment, the isolation area corresponding to the circuit block (VCO) 11 in which relatively large noise is generated at the ground potential point of the circuit due to the signal amplitude being increased as described above, is The wiring 6 extends from the pad 3 that applies the ground potential to the circuit block (small signal circuit) 12 side, where the ground potential is stabilized by handling relatively small signals, instead of being given the ground potential of 11.
The ground potential is given by .

It should be noted that on the surface of the diffusion layer 9 corresponding to the circuits 11 and 12, there is a wiring 6 and a BR diffusion N9 as shown by dotted lines in the figure.
A contact hole 10 is provided in each case for connection.

FIG. 2 shows a circuit block diagram of an embodiment functionally representing the semiconductor integrated circuit device shown in FIG. 1 above.

Terminals 4 and 5 supply operating voltage Vcc to circuit blocks 11 and 12, respectively. Terminals 2 and 3 apply ground potential to upper circuit blocks 11 and 12, respectively. In addition to applying a ground potential to the circuit block 12 as described above, the terminal 3 also applies a ground potential to a contact area (without SUB) 9 formed in the isolation area of the circuit blocks 11 and 12. used. Therefore, the ground potential of the circuit block 11 where noise occurs as described above is connected to only one independent terminal 2. Incidentally, between the diffusion layers 9 corresponding to both the circuit blocks 11 and 12, there is the substrate resistance R1 as described above.

FIG. 3 shows a schematic element cross-sectional view of one embodiment of the semiconductor integrated circuit device.

The structure of each circuit element in the figure is the same as or similar to the element structure in a known bipolar IC. On the small signal circuit side, a structural cross-sectional view of one transistor is shown as a representative. That is, an N-type epitaxial IW (Ep layer) is formed on a P-type substrate. A collector buried layer of N' is formed between the P-type substrate and the N-Ep layer.

The N-Ep layer is surrounded by a P-type isolation region 7 extending from its surface to the surface of the P-type substrate. The region surrounded by the isolation region 7 in this manner serves as one electrically isolated element formation region, and a base region constituting a transistor is formed. By the same diffusion process as that for the base region, a diffusion N9 for ohmic contact is formed on the surface of the isolation region 7. In the base region, an N-type scattered layer is formed as an emitter, and on the surface of the NEp layer, an N°-type scattered layer is formed as an ohmic contact for the collector, which is formed simultaneously with the emitter. . Then, the oxide film on the surface is selectively removed to form a contact hole, and wiring is formed in the hole, thereby forming the emitter E, base B, and collector C electrodes of one transistor that constitutes a small signal circuit. It is formed.

On the VCO circuit side, a cross-sectional view of the structure of one typical diffused resistor is shown. That is, on a P-type substrate, an N-type epitaxial J! 1J(Ep[) is formed. A collector buried layer of N' is formed between the P-type substrate and N-EpiJ. The N-Ep layer is surrounded by a P-type isolation region 7 extending from its surface to the surface of the P-type substrate. In this way, the region surrounded by the isolation region 7 becomes an electrically isolated element formation region, and a diffused resistor is formed by the same diffusion process as the base region. By the same diffusion process, a diffusion layer 9 for ohmic contact is formed on the surface of the isolation region 7. Then, the oxide film on one end side of the diffusion layer is removed to form a contact hole, in which a wiring R is formed.

In this embodiment, as described above, the isolation 7 on the CO circuit side is connected to the ground line on the small signal circuit side and the similar diffusion layer 9 of the isolation 7 via the diffusion layer 9 for ohmic contact and wiring. Connected to ground terminal 3.

In this embodiment, the signal amplitude of the CO circuit 11 is made relatively large, such as 1 to 2, so that relatively large noise is generated on the ground potential line. However, the ground line of this VCO circuit 11 is connected only to an independent external terminal 2. Therefore, the above noise is VC
○It only occurs in the grounding wire of the circuit. That is, since the ground line of the circuit is not connected to the corresponding isolation region as in the conventional semiconductor integrated circuit device, noise does not enter the isolation region. Therefore, even if there is a substrate resistance R1 between both isolation regions between the two circuit blocks, it is possible to prevent noise from leaking through it.

In addition, in a semiconductor integrated circuit device, if there is enough terminal space, the circuit in which noise occurs in the ground line may be configured to have a terminal for each of the ground line and the isolation area to supply the ground potential. . Alternatively, the isolation region 7 corresponding to the circuit block 11 where noise occurs in the ground line may be placed in a high impedance state. That is, the circuit block 11
The isolation area corresponding to the above may not be provided with the above-mentioned ohmic contact area, but may be in an apparently floating state.

Even in this case, since the isolation region on the small signal circuit 12 side and the isolation region of the CO circuit are electrically connected by the substrate resistor R1 as described above, the isolation region on the VCO side There is no problem because a ground potential is applied to reverse bias the PN junction.

The effects obtained from the above examples are as follows. That is, (11) the ground potential point of the first circuit block where relatively large noise occurs in the ground potential of the circuit is connected to the first ground potential terminal, and the element isolation region corresponding to the first circuit block is connected to the first ground potential terminal; By connecting to the second ground potential terminal corresponding to the second circuit block whose ground potential is relatively stable or to an independent third ground potential terminal, or by setting it in a high impedance state, Noise generated in the grounding line can be caused by the element isolation region and the elements of other circuits such as the substrate and the second circuit block, etc.
This has the effect of preventing leakage through the area.

(2) According to (1) above, the first circuit that generates noise, which was conventionally separated into semiconductor integrated circuits according to empirical rules, and the second circuit that generates small signals can be combined into one semiconductor integrated circuit. can be converted into This has the effect of making it possible to make the semiconductor integrated circuit device multi-functional and large-scale.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. do not have. For example, the circuits built into one semiconductor integrated circuit device include one circuit that generates noise on the ground line as described above, and other circuits that handle small signals, as well as other circuits that generate noise on the ground line. The circuit may consist of a plurality of circuits. In this case, a ground terminal is provided corresponding to each circuit, and a ground potential is applied to the isolation area corresponding to each circuit block from a relatively stable circuit as described above, or A dedicated grounding terminal may be provided for this purpose. In addition to the circuits that handle analog signals such as color signals as in the above embodiments, the circuit configurations include circuits that handle digital signals, circuits that handle digital signals, and circuits that handle analog signals, etc. Embodiments can be adopted. In addition, the circuit configuration can be bipolar circuit, MC) SFET (insulated gate field effect transistor) circuit, or Bi-CMO which is a combination of these.
Various embodiments such as three circuits can be adopted. Alternatively, the conductivity types of the semiconductor elements may be reversed, and the circuit may be constructed from PNP transistors or the like.

The present invention can be widely used in semiconductor integrated circuit devices using PN isolation regions.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, the ground potential point of the first circuit block where relatively large noise occurs in the ground potential of the circuit is connected to the first ground potential terminal, and the element M'pM region corresponding to the first circuit block is connected to the first ground potential terminal. the first circuit block by connecting it to a second ground potential terminal corresponding to the second circuit block whose ground potential is relatively stable or to an independent third ground potential terminal, or by putting it in a high impedance state. It is possible to prevent noise generated in the ground line of the device from leaking through the device isolation region and device isolation regions of other circuits such as the substrate and the second circuit block.

[Brief explanation of the drawing]

FIG. 1 is a schematic layout pattern diagram showing a basic embodiment of a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a diagram functionally showing the semiconductor integrated circuit device shown in FIG. 1 above. FIG. 3 is a schematic cross-sectional view of an element showing one embodiment of the semiconductor integrated circuit device, and FIG. 4 is a functional representation of a semiconductor integrated circuit device considered prior to the present invention. FIG. 5 is a circuit block diagram showing an example of this, and is an equivalent circuit diagram thereof.

Claims (1)

[Claims] 1. The first circuit block includes a first circuit block in which relatively large noise occurs in the ground potential of the circuit and a second circuit block in which the ground potential of the circuit is relatively stable. while connecting the ground potential point of the first ground potential terminal to the first ground potential terminal,
The element isolation region corresponding to the first circuit block is
A semiconductor integrated circuit device, characterized in that it is connected to a second ground potential terminal or an independent third ground potential terminal corresponding to a circuit block. 2. A first circuit block in which relatively large noise occurs in the ground potential of the circuit and a second circuit block in which the ground potential of the circuit is relatively stable, and the ground potential point of the first circuit block is In addition to connecting to the ground potential terminal of 1,
A semiconductor integrated circuit device characterized in that an element isolation region corresponding to the first circuit block is brought into a high impedance state. 3. Of the device isolation regions surrounding the first circuit block, a relatively high concentration diffusion region for an ohmic contact that provides a ground potential to the device isolation region corresponds to the side where the second circuit block is present. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is provided as a semiconductor integrated circuit device.