JPS59208868A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS59208868A JPS59208868A JP8273883A JP8273883A JPS59208868A JP S59208868 A JPS59208868 A JP S59208868A JP 8273883 A JP8273883 A JP 8273883A JP 8273883 A JP8273883 A JP 8273883A JP S59208868 A JPS59208868 A JP S59208868A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- emitter
- output
- base
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 230000015556 catabolic process Effects 0.000 claims abstract description 5
- 230000000295 complement effect Effects 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 8
- 230000006378 damage Effects 0.000 description 6
- 238000000605 extraction Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0826—Combination of vertical complementary transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体集積回路装置（以下ＩＣと略称する）、
特にリニアＩＣにおけるエミッタフォロワの出力端子の
静電破壊レベルを高める技術に間する。[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device (hereinafter abbreviated as IC),
In particular, we are focusing on technology to increase the level of electrostatic damage at the output terminal of an emitter follower in a linear IC.
ＩＣに１６いて、たとえば第１図に示すようにｎｐｎ）
ランジスタＱ、のエミッタ側が出力端子となっている場
合、Ｑ、のベース・エミッタ間に■。16 in the IC, for example npn as shown in Figure 1)
If the emitter side of transistor Q is the output terminal, there is a ■ between the base and emitter of transistor Q.
（ｌ１ｆｊ方向電圧）がかかるときは問題ないが、ｖＩ
Ｎ（逆方向電圧）がかかるとき、すなわち出力としての
インピーダンスがイ氏く出力電圧が■。０よりも太きい
ときは、ベース・エミッタ接合が破壊されるおそれがあ
る。この対策としてＱ、のベース電極とエミッタ電極と
の間隔を充分太き（することによってベース−抵抗を太
き（し破壊レベルをあげることも考えられるが、Ｉｃの
集積度、トランジスタのペア性の関係で素子の寸法規格
を変えることはかんたんにはできない。There is no problem when (l1fj direction voltage) is applied, but vI
When N (reverse voltage) is applied, the impedance as an output decreases and the output voltage becomes ■. If it is thicker than 0, the base-emitter junction may be destroyed. As a countermeasure to this, the distance between the base electrode and the emitter electrode of Q should be made sufficiently large (by doing so, the base-resistance may be made thick (and the level of damage may be increased), but the Therefore, it is not possible to easily change the dimensional standards of elements.
本発明の目的はＩＣにおいて、素子の規格を変えること
なくエミッタフォロワの出力端子の破壊レベルを向上し
、信頼性を向上できる回路構造の提供にある。An object of the present invention is to provide a circuit structure in an IC that can improve the level of damage to the output terminal of an emitter follower and improve reliability without changing the specifications of the device.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、第１のトランジスタ例えばｎｐｌ
ｌ）ランジスタを有するエミッタフォロワ回路において
、出力側に第１のトランジスタと相補の型の第２のトラ
ンジスタすなわちｐｎｐトランジスタを接続してそのコ
レクタを接地することにより上記出力側の高電位による
第１のトランジスタの靜＠破ａｔ位を向上するものであ
る。To briefly explain the outline of a typical invention among the inventions disclosed in this application, a first transistor, for example, an NPL
l) In an emitter follower circuit having a transistor, a second transistor of a complementary type to the first transistor, that is, a pnp transistor, is connected to the output side, and its collector is grounded, so that the first transistor due to the high potential on the output side is connected. This improves the quietness of the transistor.
第２図は本発明によるエミッタフォロワの出力回路の一
実施例を示し、Ｑ、はｎｐｎ）ランジスタでそのエミッ
タＥ、側が出力端子となり、コレクタＣ３側には抵抗Ｒ
を介して電源電位ｖｃｏがかかる。FIG. 2 shows an embodiment of the output circuit of an emitter follower according to the present invention.
A power supply potential vco is applied through the terminal.
Ｑ２はｐｎｐ）ランジスタでそのエミッタＥ。Q2 is a pnp transistor and its emitter E.
側をＱ、の出力側に接続し、コレクタＣ７側（基板：サ
ブストレート）を接地する。Ｑ、のベースＢ、とＱ２の
ベースＢ、はともにｖｃｃに接続する。The side of the collector is connected to the output side of Q, and the collector C7 side (substrate) is grounded. Base B of Q and base B of Q2 are both connected to vcc.
このような回路にオ６いて、出力ピンにｖｃｃより高を
位の大電流１．が流れようとする場合、Ｑ２がＯＮする
ことによりＱ２のサブストレート（接地側）に電流Ｉ、
として流れることになり、Ｑ。In such a circuit, a large current higher than Vcc is applied to the output pin. is about to flow, when Q2 turns on, a current I,
Q.
の負担がな（なり、したがってＱ、の破壊レベルが高ま
ることになる。The burden on Q will increase, and therefore the level of destruction of Q will increase.
第３図は本発明によるエミッタフォロワの出力回路を一
つの半導体基板に形成した場合を模型的に示す断面図で
あり、第４図は第３図に対応する平面図である。FIG. 3 is a cross-sectional view schematically showing a case where an output circuit of an emitter follower according to the present invention is formed on one semiconductor substrate, and FIG. 4 is a plan view corresponding to FIG. 3.
同図において、ｌはｐ−型Ｓｉ基板（サブストレート）
、２はｎ＋型埋込層、３はエピタキシャルｎ型Ｓｉ層、
４はアイソレーションｐ型層である。このｐ型層４によ
って電気的に分離されたｎ型Ｓｉ層３の一方にｎｐｎ）
ランジスタＱ１、他方にｐｎｐｌ−ランジスタＱ、が形
成される。、５はＱ、のベースとなるｐ型層、６は同エ
ミッタとなるｎ＋匿層、７は同コレクタ取出し部となる
ｎ＋型層である。８はＱ、のエミッタとなる円形のｐ型
層、９は同コレクタとなるｐ型層であってエミッタを囲
むリング状延形成されアイソレーションｐ型層４と一部
で重なって短絡される。１０はＱ。In the same figure, l is a p-type Si substrate (substrate)
, 2 is an n+ type buried layer, 3 is an epitaxial n-type Si layer,
4 is an isolation p-type layer. npn) on one side of the n-type Si layer 3 electrically isolated by this p-type layer 4.
A transistor Q1 and a pnpl-transistor Q are formed on the other side. , 5 is a p-type layer serving as the base of Q, 6 is an n+ type layer serving as the emitter, and 7 is an n+ type layer serving as the collector extraction portion. Reference numeral 8 denotes a circular p-type layer that serves as the emitter of Q, and 9 indicates a p-type layer that serves as the collector of Q, which is formed in a ring shape surrounding the emitter, partially overlaps with the isolation p-type layer 4, and is short-circuited. 10 is Q.
のベース取出し部である。This is the base extraction part.
第４図において破線は拡散層によるｐｎ接合（表面部）
を示し、ｐｎｐ）ランジスタＱつ側で実線で囲まれハツ
チングした部分は各領域にコンタクトする電極となる金
属膜を示す。同図に示されるように、ｐｎｐトランジス
タＱ、において、円形のエミッタとリング形のコレクタ
との間隔を充分大きくとることにより、ベース・エミッ
タ間耐圧を大きくすることになるうたとえばｐｎｐトラ
ンジスタのベース・エミッタ耐圧は６０数■とすること
ができる。一方、ｎｐｎ）ランジスタのベース・エミッ
タ間耐圧は７■程度である。In Figure 4, the broken line is the pn junction (surface part) due to the diffusion layer.
, pnp) The hatched portion surrounded by solid lines on the Q side of the transistor indicates a metal film serving as an electrode in contact with each region. As shown in the figure, by making a sufficiently large distance between the circular emitter and the ring-shaped collector in the pnp transistor Q, the withstand voltage between the base and emitter can be increased. The emitter breakdown voltage can be set to about 60 mm. On the other hand, the base-emitter breakdown voltage of an npn transistor is about 7.
上記実施例中で述べたように、本発明によるエミッタフ
ォロワ出力回路においてはｎｐｎ）ランジスタの出力端
子にこれと相補形のＩ）ｎｐ）ランジスタを追加するこ
とによって、出力側に大電流が流れた場合もこのｐｎｐ
トランジスタがＯＮとなり接地側へ電流がながれること
によりｎｐｎ）ランジスタの破壊レベルを向上しりる。As described in the above embodiment, in the emitter follower output circuit according to the present invention, by adding a complementary I)np) transistor to the output terminal of the npn) transistor, a large current flows on the output side. In this case also pnp
When the transistor is turned on and current flows to the ground side, the level of damage to the npn transistor is improved.
この場合、素子としては一素子増加するが、素子の規格
を変えることなく破壊のレベルを向上でき使い易いＩＣ
を提供できる。In this case, the number of elements increases by one, but the level of destruction can be improved without changing the specifications of the element, and the IC is easy to use.
can be provided.
以上本発明によってなされた発明を実施例にもとづき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々に変更可
能である。Although the invention made by the present invention has been specifically explained based on the examples, the present invention is not limited to the above-mentioned examples, and can be variously modified without departing from the gist thereof.
本発明はリニアｌＣ一般に適用することができる。 The present invention can be applied to linear IC in general.
第４図はこれまでのエミッタフォロワの出力回路の例を
示す回路図である。
第２図は本発明によるエミッタフォロワの出力回路の一
例を示す回路図である。
第３図は本発明によるエミッタフォロワの出力回路を一
つの半導体基体上に形成した場合を模型的に示す断面図
、
第４図は第３図に対応する平面図である。
■・・・ｐ−型Ｓｉ基板、２・・・ｎ＋型埋込層、３・
・・エピタキシャルｎノｔＢｓ １ＩｔＬ ４・・・
アイソレーショ７ｐｍ層、５・・・ｎｐｎ）ランジスタ
のｐ型ベース、６・・・同ｎ＋型エミッタ、７・・・同
ｎ＋型コレクタ取出し部、８・・・ｐｎｐ）ランジスタ
のｐ型エミッタ、９・・・同ｐ型コレクタ、１０・・・
同ｎ＋型ベース取出し部。
第 １ 図
第 ２ 図
第 ３ 図
ｉ夕
（θ／）
（夕の第 ４ 図
θ／ 々２FIG. 4 is a circuit diagram showing an example of a conventional emitter follower output circuit. FIG. 2 is a circuit diagram showing an example of an output circuit of an emitter follower according to the present invention. FIG. 3 is a sectional view schematically showing the case where the output circuit of the emitter follower according to the present invention is formed on one semiconductor substrate, and FIG. 4 is a plan view corresponding to FIG. 3. ■... p- type Si substrate, 2... n+ type buried layer, 3...
...Epitaxial nnotBs 1ItL 4...
Isolation 7pm layer, 5...npn) p-type base of transistor, 6... n+-type emitter, 7... n+-type collector extraction part, 8... pnp) p-type emitter of transistor, 9 ...Same p-type collector, 10...
Same n+ type base extraction part. Figure 1 Figure 2 Figure 3
(Evening 4th figure θ/ 2
Claims (1)
力端子に第１のトランジスタと相補型になる第２のトラ
ンジスタが静電破壊電位向上用として接続されているこ
とを特徴とする半導体集積回路装置。 ２、第１のトランジスタはｎｐｎ）ランジスタであり、
第２のトランジスタはｐｎｐトランジスタである特許請
求の範囲第１項に記載の半導体集積回路装置。 ３、第１のトランジスタ及び第２のトランジスタのベー
スは共２ｍの電源電位に接続されている特許請求の範囲
第１項又は第２項に記載の半導体集積回路装置っ[Claims] 1. A second transistor complementary to the first transistor is connected to the output terminal of the emitter follower having the first transistor for improving electrostatic breakdown potential. Semiconductor integrated circuit device. 2. The first transistor is an npn) transistor,
2. The semiconductor integrated circuit device according to claim 1, wherein the second transistor is a pnp transistor. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the bases of the first transistor and the second transistor are both connected to a power supply potential of 2 m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8273883A JPS59208868A (en) | 1983-05-13 | 1983-05-13 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8273883A JPS59208868A (en) | 1983-05-13 | 1983-05-13 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59208868A true JPS59208868A (en) | 1984-11-27 |
Family
ID=13782752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8273883A Pending JPS59208868A (en) | 1983-05-13 | 1983-05-13 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59208868A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61102765A (en) * | 1984-10-26 | 1986-05-21 | Matsushita Electronics Corp | Semiconductor integrated circuit device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53108778A (en) * | 1977-03-04 | 1978-09-21 | Nec Corp | Transistor |
| JPS5740977A (en) * | 1980-08-25 | 1982-03-06 | Nippon Denso Co Ltd | Semiconductor device |
-
1983
- 1983-05-13 JP JP8273883A patent/JPS59208868A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53108778A (en) * | 1977-03-04 | 1978-09-21 | Nec Corp | Transistor |
| JPS5740977A (en) * | 1980-08-25 | 1982-03-06 | Nippon Denso Co Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61102765A (en) * | 1984-10-26 | 1986-05-21 | Matsushita Electronics Corp | Semiconductor integrated circuit device |
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