JPS59208868A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS59208868A
JPS59208868A JP8273883A JP8273883A JPS59208868A JP S59208868 A JPS59208868 A JP S59208868A JP 8273883 A JP8273883 A JP 8273883A JP 8273883 A JP8273883 A JP 8273883A JP S59208868 A JPS59208868 A JP S59208868A
Authority
JP
Japan
Prior art keywords
transistor
emitter
output
base
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8273883A
Other languages
Japanese (ja)
Inventor
Yukinori Kitamura
幸則 北村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP8273883A priority Critical patent/JPS59208868A/en
Publication of JPS59208868A publication Critical patent/JPS59208868A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H01L27/0826Combination of vertical complementary transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To enable the flow of current to the ground side in the state that a complementary P-N-P transistor turns on even by the flow of a large current to the output side and thus to improve the breakdown level of an N-P-N transistor by adding said P-N-P transistor to the output terminal of the N-P-N transistor. CONSTITUTION:The emitter E1 side of the N-P-N transistor Q1 serves as the output terminal, and a power source potential VCC is impressed on the collector C1 side via resistor R. The emitter E2 side of the P-N-P transistor Q2 is connected to the output side of the transistor Q1, and the collector C2 side (substrate) is grounded. The base B1 of the transistor Q1 and the base B2 of the transistor Q2 are both connected to the power source potential VCC. In such a circuit, when the large current I1 of a higher potential than said potential VCC flows to an output pin, it flows to the substrate (ground side) of the transistor Q2 as the current I2 by the ON-stage of the transistor Q2, resulting in no load for the transistor Q1. Accordingly, the breakdown level of the transistor Q1 enhances.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体集積回路装置(以下ICと略称する)、
特にリニアICにおけるエミッタフォロワの出力端子の
静電破壊レベルを高める技術に間する。
[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device (hereinafter abbreviated as IC),
In particular, we are focusing on technology to increase the level of electrostatic damage at the output terminal of an emitter follower in a linear IC.

〔背景技術〕[Background technology]

ICに16いて、たとえば第1図に示すようにnpn)
ランジスタQ、のエミッタ側が出力端子となっている場
合、Q、のベース・エミッタ間に■。
16 in the IC, for example npn as shown in Figure 1)
If the emitter side of transistor Q is the output terminal, there is a ■ between the base and emitter of transistor Q.

(l1fj方向電圧)がかかるときは問題ないが、vI
N(逆方向電圧)がかかるとき、すなわち出力としての
インピーダンスがイ氏く出力電圧が■。0よりも太きい
ときは、ベース・エミッタ接合が破壊されるおそれがあ
る。この対策としてQ、のベース電極とエミッタ電極と
の間隔を充分太き(することによってベース−抵抗を太
き(し破壊レベルをあげることも考えられるが、Icの
集積度、トランジスタのペア性の関係で素子の寸法規格
を変えることはかんたんにはできない。
There is no problem when (l1fj direction voltage) is applied, but vI
When N (reverse voltage) is applied, the impedance as an output decreases and the output voltage becomes ■. If it is thicker than 0, the base-emitter junction may be destroyed. As a countermeasure to this, the distance between the base electrode and the emitter electrode of Q should be made sufficiently large (by doing so, the base-resistance may be made thick (and the level of damage may be increased), but the Therefore, it is not possible to easily change the dimensional standards of elements.

〔発明の目的〕[Purpose of the invention]

本発明の目的はICにおいて、素子の規格を変えること
なくエミッタフォロワの出力端子の破壊レベルを向上し
、信頼性を向上できる回路構造の提供にある。
An object of the present invention is to provide a circuit structure in an IC that can improve the level of damage to the output terminal of an emitter follower and improve reliability without changing the specifications of the device.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、第1のトランジスタ例えばnpl
l)ランジスタを有するエミッタフォロワ回路において
、出力側に第1のトランジスタと相補の型の第2のトラ
ンジスタすなわちpnpトランジスタを接続してそのコ
レクタを接地することにより上記出力側の高電位による
第1のトランジスタの靜@破at位を向上するものであ
る。
To briefly explain the outline of a typical invention among the inventions disclosed in this application, a first transistor, for example, an NPL
l) In an emitter follower circuit having a transistor, a second transistor of a complementary type to the first transistor, that is, a pnp transistor, is connected to the output side, and its collector is grounded, so that the first transistor due to the high potential on the output side is connected. This improves the quietness of the transistor.

〔実施例〕〔Example〕

第2図は本発明によるエミッタフォロワの出力回路の一
実施例を示し、Q、はnpn)ランジスタでそのエミッ
タE、側が出力端子となり、コレクタC3側には抵抗R
を介して電源電位vcoがかかる。
FIG. 2 shows an embodiment of the output circuit of an emitter follower according to the present invention.
A power supply potential vco is applied through the terminal.

Q2はpnp)ランジスタでそのエミッタE。Q2 is a pnp transistor and its emitter E.

側をQ、の出力側に接続し、コレクタC7側(基板:サ
ブストレート)を接地する。Q、のベースB、とQ2の
ベースB、はともにvccに接続する。
The side of the collector is connected to the output side of Q, and the collector C7 side (substrate) is grounded. Base B of Q and base B of Q2 are both connected to vcc.

このような回路にオ6いて、出力ピンにvccより高を
位の大電流1.が流れようとする場合、Q2がONする
ことによりQ2のサブストレート(接地側)に電流I、
として流れることになり、Q。
In such a circuit, a large current higher than Vcc is applied to the output pin. is about to flow, when Q2 turns on, a current I,
Q.

の負担がな(なり、したがってQ、の破壊レベルが高ま
ることになる。
The burden on Q will increase, and therefore the level of destruction of Q will increase.

第3図は本発明によるエミッタフォロワの出力回路を一
つの半導体基板に形成した場合を模型的に示す断面図で
あり、第4図は第3図に対応する平面図である。
FIG. 3 is a cross-sectional view schematically showing a case where an output circuit of an emitter follower according to the present invention is formed on one semiconductor substrate, and FIG. 4 is a plan view corresponding to FIG. 3.

同図において、lはp−型Si基板(サブストレート)
、2はn+型埋込層、3はエピタキシャルn型Si層、
4はアイソレーションp型層である。このp型層4によ
って電気的に分離されたn型Si層3の一方にnpn)
ランジスタQ1、他方にpnpl−ランジスタQ、が形
成される。、5はQ、のベースとなるp型層、6は同エ
ミッタとなるn+匿層、7は同コレクタ取出し部となる
n+型層である。8はQ、のエミッタとなる円形のp型
層、9は同コレクタとなるp型層であってエミッタを囲
むリング状延形成されアイソレーションp型層4と一部
で重なって短絡される。10はQ。
In the same figure, l is a p-type Si substrate (substrate)
, 2 is an n+ type buried layer, 3 is an epitaxial n-type Si layer,
4 is an isolation p-type layer. npn) on one side of the n-type Si layer 3 electrically isolated by this p-type layer 4.
A transistor Q1 and a pnpl-transistor Q are formed on the other side. , 5 is a p-type layer serving as the base of Q, 6 is an n+ type layer serving as the emitter, and 7 is an n+ type layer serving as the collector extraction portion. Reference numeral 8 denotes a circular p-type layer that serves as the emitter of Q, and 9 indicates a p-type layer that serves as the collector of Q, which is formed in a ring shape surrounding the emitter, partially overlaps with the isolation p-type layer 4, and is short-circuited. 10 is Q.

のベース取出し部である。This is the base extraction part.

第4図において破線は拡散層によるpn接合(表面部)
を示し、pnp)ランジスタQつ側で実線で囲まれハツ
チングした部分は各領域にコンタクトする電極となる金
属膜を示す。同図に示されるように、pnpトランジス
タQ、において、円形のエミッタとリング形のコレクタ
との間隔を充分大きくとることにより、ベース・エミッ
タ間耐圧を大きくすることになるうたとえばpnpトラ
ンジスタのベース・エミッタ耐圧は60数■とすること
ができる。一方、npn)ランジスタのベース・エミッ
タ間耐圧は7■程度である。
In Figure 4, the broken line is the pn junction (surface part) due to the diffusion layer.
, pnp) The hatched portion surrounded by solid lines on the Q side of the transistor indicates a metal film serving as an electrode in contact with each region. As shown in the figure, by making a sufficiently large distance between the circular emitter and the ring-shaped collector in the pnp transistor Q, the withstand voltage between the base and emitter can be increased. The emitter breakdown voltage can be set to about 60 mm. On the other hand, the base-emitter breakdown voltage of an npn transistor is about 7.

〔効果〕〔effect〕

上記実施例中で述べたように、本発明によるエミッタフ
ォロワ出力回路においてはnpn)ランジスタの出力端
子にこれと相補形のI)np)ランジスタを追加するこ
とによって、出力側に大電流が流れた場合もこのpnp
トランジスタがONとなり接地側へ電流がながれること
によりnpn)ランジスタの破壊レベルを向上しりる。
As described in the above embodiment, in the emitter follower output circuit according to the present invention, by adding a complementary I)np) transistor to the output terminal of the npn) transistor, a large current flows on the output side. In this case also pnp
When the transistor is turned on and current flows to the ground side, the level of damage to the npn transistor is improved.

この場合、素子としては一素子増加するが、素子の規格
を変えることなく破壊のレベルを向上でき使い易いIC
を提供できる。
In this case, the number of elements increases by one, but the level of destruction can be improved without changing the specifications of the element, and the IC is easy to use.
can be provided.

以上本発明によってなされた発明を実施例にもとづき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々に変更可
能である。
Although the invention made by the present invention has been specifically explained based on the examples, the present invention is not limited to the above-mentioned examples, and can be variously modified without departing from the gist thereof.

〔利用分野〕[Application field]

本発明はリニアlC一般に適用することができる。 The present invention can be applied to linear IC in general.

【図面の簡単な説明】[Brief explanation of the drawing]

第4図はこれまでのエミッタフォロワの出力回路の例を
示す回路図である。 第2図は本発明によるエミッタフォロワの出力回路の一
例を示す回路図である。 第3図は本発明によるエミッタフォロワの出力回路を一
つの半導体基体上に形成した場合を模型的に示す断面図
、 第4図は第3図に対応する平面図である。 ■・・・p−型Si基板、2・・・n+型埋込層、3・
・・エピタキシャルnノtBs 1ItL  4・・・
アイソレーショ7pm層、5・・・npn)ランジスタ
のp型ベース、6・・・同n+型エミッタ、7・・・同
n+型コレクタ取出し部、8・・・pnp)ランジスタ
のp型エミッタ、9・・・同p型コレクタ、10・・・
同n+型ベース取出し部。 第  1  図 第  2  図 第  3  図 i夕 (θ/)                     
       (夕の第  4  図 θ/    々2
FIG. 4 is a circuit diagram showing an example of a conventional emitter follower output circuit. FIG. 2 is a circuit diagram showing an example of an output circuit of an emitter follower according to the present invention. FIG. 3 is a sectional view schematically showing the case where the output circuit of the emitter follower according to the present invention is formed on one semiconductor substrate, and FIG. 4 is a plan view corresponding to FIG. 3. ■... p- type Si substrate, 2... n+ type buried layer, 3...
...Epitaxial nnotBs 1ItL 4...
Isolation 7pm layer, 5...npn) p-type base of transistor, 6... n+-type emitter, 7... n+-type collector extraction part, 8... pnp) p-type emitter of transistor, 9 ...Same p-type collector, 10...
Same n+ type base extraction part. Figure 1 Figure 2 Figure 3
(Evening 4th figure θ/ 2

Claims (1)

【特許請求の範囲】 1、第1のトランジスタを有するエミッタフォロワの出
力端子に第1のトランジスタと相補型になる第2のトラ
ンジスタが静電破壊電位向上用として接続されているこ
とを特徴とする半導体集積回路装置。 2、第1のトランジスタはnpn)ランジスタであり、
第2のトランジスタはpnpトランジスタである特許請
求の範囲第1項に記載の半導体集積回路装置。 3、第1のトランジスタ及び第2のトランジスタのベー
スは共2mの電源電位に接続されている特許請求の範囲
第1項又は第2項に記載の半導体集積回路装置っ
[Claims] 1. A second transistor complementary to the first transistor is connected to the output terminal of the emitter follower having the first transistor for improving electrostatic breakdown potential. Semiconductor integrated circuit device. 2. The first transistor is an npn) transistor,
2. The semiconductor integrated circuit device according to claim 1, wherein the second transistor is a pnp transistor. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the bases of the first transistor and the second transistor are both connected to a power supply potential of 2 m.
JP8273883A 1983-05-13 1983-05-13 Semiconductor integrated circuit device Pending JPS59208868A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8273883A JPS59208868A (en) 1983-05-13 1983-05-13 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8273883A JPS59208868A (en) 1983-05-13 1983-05-13 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS59208868A true JPS59208868A (en) 1984-11-27

Family

ID=13782752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8273883A Pending JPS59208868A (en) 1983-05-13 1983-05-13 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS59208868A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61102765A (en) * 1984-10-26 1986-05-21 Matsushita Electronics Corp Semiconductor integrated circuit device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108778A (en) * 1977-03-04 1978-09-21 Nec Corp Transistor
JPS5740977A (en) * 1980-08-25 1982-03-06 Nippon Denso Co Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108778A (en) * 1977-03-04 1978-09-21 Nec Corp Transistor
JPS5740977A (en) * 1980-08-25 1982-03-06 Nippon Denso Co Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61102765A (en) * 1984-10-26 1986-05-21 Matsushita Electronics Corp Semiconductor integrated circuit device

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