JPH0425702B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to the structure of a transistor in a semiconductor integrated circuit.

Some transistors in integrated circuits have a base electrode electrically connected directly to a bonding pad leading to an external lead due to the circuit configuration.

For example, as shown in FIG. 1, among transistors Q ₂ and Q ₃ forming a differential amplifier circuit, the base electrode of transistor Q ₂ is connected to a bonding pad 50 to receive an input signal. The commonly connected emitters of transistors Q ₂ and Q ₃ are connected to transistor Q ₁ forming a current mirror circuit. In such a configuration, when a surge voltage or a surge pulse is applied to the pad 50 due to static electricity charged on a human body and its clothes, for example, the emitter-base junction of the transistor _Q2 is destroyed by the impact voltage. occurs. This phenomenon is hereinafter referred to as electrostatic breakdown. In a bipolar integrated circuit like the one shown in Figure 1, the transistor
Q ₁ to Q ₃ are formed in isolated N-type island regions on a P-type substrate, and the P-type substrate is
It is connected to the GND (ground) terminal 55. Therefore, when a negative high voltage pulse is applied to the pad 50 with respect to the GND terminal 55, the current flows through the GND wiring → the collector of the transistor Q ₁ → the emitter of the transistor Q ₂ → the base → the pad 50. Current flows instantaneously. The maximum value of the current is
This is determined by the impedance from GND to the external lead connected to pad A and the applied shock voltage, but it is usually more than 1A momentarily, causing the emitter-base junction of transistor _Q2 to become crystalline. destroyed.

In order to avoid this, it is possible to insert a resistor R between the base of the transistor Q ₂ and the pad 50 as shown in Figure 2, but the electrostatic breakdown strength
In order to maintain 200V or more, the value of resistor R should be 200Ω.
More than that is required. Therefore, transistors Q ₂ , Q ₃
This is not desirable in terms of circuit operation because the offset balance of the circuit becomes worse and the frequency characteristics, noise characteristics, etc. deteriorate. Another countermeasure is to reduce the current density by increasing the transistor _Q2 , but the matching transistor _Q3 must also be equally large, and as a result, the parasitic capacitance increases and the frequency characteristics deteriorate. This not only causes deterioration but also increases the device area.

When the current path 51 shown in FIG. 1 is shown in terms of device structure, the transistors shown in FIGS. 3 and 4 are
In the well-known structure of Q ₁ , since the P-type substrate 1 is at GND potential, when a shock pulse is applied to the substrate 1, the substrate 1 and the island-like region 3 (this region is formed by epitaxial growth and the substrate 1 and isolated by isolation region 4) is forward biased, and a large current momentarily flows mainly toward buried N ⁺ region 7.
As shown in FIGS. 3 and 4, a buried N ⁺ layer 2 is typically used to form a base region 5 and a collector contact for the purpose of lowering the series resistance of an NPN transistor.
It extends to the outside of the N ⁺ region 7, and therefore the resistance from the buried N ⁺ layer 2 to the collector contact N ⁺ layer 7 is small. Therefore, the current limit of transistor Q ₁ itself is very small, and the base-emitter connection of transistor Q ₂ is easily destroyed by static electricity.

Also, to limit the current, as shown in Figure 5, the collector of transistor _Q1 and the transistor
It has been proposed to connect a resistor r between the emitter of _Q2 . According to this configuration, disadvantages such as worse offset and worse noise characteristics compared to the second configuration can be prevented. However, static electricity is not limited to only between the terminals 50 and 55, but can also be supplied between the terminals 55 and the power supply terminal 60, so even in this case, in order to fully exhibit the function of preventing electrostatic damage, it is necessary to , the resistor r needs to be in a floating state with no electrical bias applied. Like a well-known semiconductor resistor, the resistance r is formed in a P-type region formed in an N-type island region.
When constructed, the device structure becomes as shown in FIG. That is, a P-type resistance region 12 is formed in an island region 3' different from the island region 3 in which the transistor _Q1 is formed, and one end thereof is connected to the transistor Q1.
It is connected to the collector contact region 7 of Q ₁ with a wiring 11, and the other end is connected to the transistor Q ₂ via a wiring 13.
The resistor r is connected to the emitter of the resistor r. As is well known, the island region 3' is connected to the power supply Vcc via a contact region 14 in order to isolate the P-type resistance region 12. Therefore, when static electricity is applied between the power supply terminal 60 and the terminal 50 (the polarity of the terminal 50 is positive), the terminal 50→
Transistor Q ₂ base → same emitter → wiring 1
3 → PN junction between P-type region 12 and island region → Vcc
Current flows to the power supply terminal 13, and the resistance region 12 does not function as a resistor r, but the transistor Q ₂
The base-emitter junction of the base-emitter will still be destroyed. Therefore, the resistor r must be in a floating state with no electrical bias, and setting it in a floating state will lead to an increase in the pellet area.

As mentioned above, in the circuit configuration shown in Figure 1, in order to protect the internal elements from shock pulses caused by static electricity from the outside, conventional techniques either sacrifice electrical characteristics or increase the pellet area. I was using it.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device having a structure that can be protected from shock pulses caused by static electricity without increasing the pellet area or deteriorating electrical characteristics.

The present invention is characterized in that the resistor r shown in FIG. 5 is constructed within the collector region of the transistor _Q1 . In other words, the buried layer for reducing the collector series resistance may be terminated under the base region without extending below the collector electrode lead-out portion, or an opposite conductivity type region may be formed in the collector region, and one end of the buried layer may be formed in the collector region. A current limiting resistor is constructed in the collector region by connecting the two ends and taking out the other end as a collector electrode. All of these can be constructed by simply changing the pattern mask, and no special isolation area is required.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 7 is a schematic structural sectional view of an embodiment of the present invention, and FIG. 8 is a plan view thereof. In particular, FIGS. 7 and 8 show the transistor _Q1 .
1 is a P-type substrate with a specific resistance of 1 to 3 Ω-cm, 2' is an N-type high concentration buried layer with a layer resistance of 20 to 30 Ω/hole, and 3 is a P-type substrate with a specific resistance of 1 to 3 Ω-cm and a thickness of 10 to 15 μm. This is an island region formed of an epitaxial layer. The major difference from FIG. 3 is that the buried N ⁺ layer 2' does not extend to the bottom of the collector contact N ⁺ region 7, but terminates near the base region 5.
According to this configuration, the impedance Z ₂ with respect to the current flowing from the buried N ⁺ layer 2' to the collector contact N ⁺ region 7 naturally becomes large. Furthermore, the impedance Z ₁ in the current path from the P substrate 1 to the collector contact N ⁺ layer 7 without passing through the buried N ⁺ layer 2' is determined by the concentration of the N-type epitaxial layer 3
Since the concentration is about 10 ³ lower than that of the N ⁺ layer 2', the resistance is considerably larger than the resistance in the buried N ⁺ layer 2'.

For the above reasons, the impedance from the P-type substrate 1 to the collector contact N ⁺ region 7 is
It is much larger than the conventional method shown in Figure 4,
The electrostatic breakdown strength of transistor Q ₂ (Figure 1) is 200V
It will increase more than that. That is, in the embodiments shown in FIGS. 7 and 8, the resistor r shown in FIG. 5 is formed in the collector region of the transistor _Q1 by changing the pattern shape of the buried region 2'. As can be seen from FIGS. 7 and 8, even by reducing the area of the buried N ⁺ layer 2' according to the present invention, the area of the PN junction formed between the P-type substrate 1 and the buried N ⁺ layer 2' is sufficiently large. Therefore, the current density is sufficiently small, and since a negative impact pulse is applied to the collector contact N ⁺ 7, the substrate 1 and the buried N ⁺ layer 2 are forward biased, and the electrostatic breakdown strength of the transistor Q ₂ according to the present invention is sufficient. It is. Furthermore, since the present invention can be achieved by simply changing the mask pattern, conventional manufacturing processes can be used as is. Furthermore, since there is no increase in the size of the transistor, there is no deterioration in high frequency characteristics.

FIG. 9 is a structural diagram of a transistor _Q1 showing another embodiment of the present invention. Functional parts that are the same as those in FIG. 7 are indicated by the same numbers, and their explanations will be omitted. In the transistor _Q1 shown in FIG. 9, the buried layer 2 is formed extending to the outside of the collector contact region 7, as in a normal transistor. Instead, a P-type region 13 having a conductivity type opposite to that of the collector region is formed in contact with the collector contact region 7, one end of which is connected to the collector contact region 7 by a wiring 14, and the other end connected to the collector contact region 7 by a wiring 15. is connected to the common emitter connection point of transistors _Q2 and _Q3 . The resistance of the P-type region 13 is approximately 200Ω, and is formed by co-diffusion with the base region 5 of the NPN transistor. Alternatively, it may be an ion-implanted resistor formed by, for example, ion-implanting another P-type impurity diffusion. With this configuration, it is possible to protect against static electricity applied between the terminals 50-55 and between the terminals 50-60. Further, the element area is greatly reduced compared to the case shown in FIG. 6 or the case of individual insulation, and the degree of freedom in pattern layout is also increased.

FIG. 10 shows still another embodiment of the present invention, in which the same functional parts as in FIG. 7 are designated by the same numbers and their explanations will be omitted. In the transistor _Q1 shown in FIG. 10, the N-type buried layer 2 is formed extending to the outside of the collector contact region 7, as in FIG. Layer resistance 150~250Ω/mouth P
A mold buried layer 16 is provided below the collector contact region 7. The P-type buried layer 16 does not require any special formation process, and can be formed when the insulating isolation region is formed by the rising region 4-1 from the substrate 1 side and the region 4-2 from the surface of the epitaxial layer. , are formed at the same time as the rising region (embedded region) 4-1 from one example of the substrate. Therefore, if the reverse bias of the PN combination formed by the N-type buried layer 2 and the P-type buried layer 16 is below the avalanche breakdown voltage, the P-type buried layer 16 is connected to the collector contact N ⁺ from the P-type substrate 1.
7 acts as a barrier to the current flowing towards it. Therefore, the current flowing from the P-type substrate 1 to the collector contact N ⁺ 7 flows around the P-type buried layer 16 as shown by the arrow in FIG. 10, so that the impedance from the substrate to the collector contact N ⁺ layer 7 decreases. naturally becomes larger. When a voltage higher than the avalanche breakdown voltage is applied to the PN junction formed by the N-type buried layer 2 and the P-type buried layer 16, the current flowing from the substrate 1 to the collector contact N ⁺ layer 7 changes from the P-type substrate 1→
N-type buried layer 2 → P-type buried layer 16 → N-type island-like epitaxial layer 3 → collector contact N ⁺ layer 7
Although the current flows in a straight line without detouring, the shock pulse voltage suffers a voltage loss due to avalanche breakdown, so the current flowing through the above route is smaller than the current flowing outside the P-type buried layer 16. In this way, P
The effect of the mold buried layer 16 serves as a barrier to the current flowing from the substrate 1 to the collector contact N ⁺ 7, and therefore the impedance increases significantly. As mentioned above, the P-type buried layer 16 is a buried P ⁺ type which is widely used and is called bottom isolation.
If used in simultaneous diffusion with layer 4-1, conventional processes can be used as is. Further, since the area of the transistor is sufficient with a minimum pattern, there is no deterioration of frequency characteristics due to junction capacitance.

FIG. 11 also shows yet another embodiment of the present invention, in which another wiring is connected over the collector region of transistor Q ₁ (over the collector region between the base electrode and collector electrode of transistor Q ₁ ). This is to deal with the case where the signal passes through an insulating film. Conventionally, when other wiring passes over the collector region in this way, as shown in FIG. It was close to 5. In other words, the other three interconnections 17 pass over the collector contact region 7. As described above, increasing the area of the collector contact region 7 reduces the impedance from the P-type substrate 1 to the collector contact region 7, so that the electrostatic breakdown resistance decreases.

Therefore, in the present invention, as shown in FIG. 11, the collector contact region 7 is made small to prevent it from being located under the wiring 17. As a result, the impedance between the substrate 1 and the collector contact region 7 increases, and the electrostatic breakdown resistance increases.

Furthermore, as shown in FIG. 12, by combining FIG. 11 and FIG. 7, the N-type buried region 2 is terminated below the base region 5 and is not formed to extend below the collector contact region 7. By doing so, the effect of preventing electrostatic damage is further increased.

As described above, according to the present invention, the frequency characteristics,
A semiconductor device with sufficiently high electrostatic breakdown strength is provided without deteriorating offset or noise characteristics and without increasing the element area etc. in a normal manufacturing process.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be similarly applied to a PNP type. Moreover, although the shape of the transistor has been described only as a rectangle, it is of course possible to take any shape within the spirit of the present invention. Further, although the case where only a single epitaxial layer is used has been described, the present invention can be similarly applied to other methods such as double epitaxial layer and partial concentration control by ion implantation. Furthermore, the transistor to which the structure of the present invention is applied is not limited to the differential amplifier shown in FIG. The passage is applied to a second transistor in a circuit connected in series between first and second external lead terminals.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example of a differential amplifier circuit, Figure 2 is a circuit diagram of a differential amplifier circuit with an example of electrostatic damage prevention measures, and Figures 3 and 4 are typical transistors. 5 is a circuit diagram of a differential amplifier circuit with another example of electrostatic damage prevention measures, and FIG. 6 is a cross-sectional view and a plan view showing the device structure of FIG. ₅ . 7 and 8 are cross-sectional views and plan views of a transistor showing one embodiment of the present invention, and FIG. 9 is a cross-sectional view showing another embodiment of the present invention, FIG. 10 is a sectional view showing still another embodiment of the present invention, FIGS. 11 and 12 are a plan view showing still another embodiment of the invention, and FIG. 13 is a plan view showing another conventional transistor. be. 1... P-type semiconductor substrate, 2, 2'... N-type buried region, 3, 3'... N-type island-like epitaxial region, 4, 4-1, 4-2... P-type insulation isolation region,
5... Base area, 6... Emitter area, 7...
Collector contact region, 8...Surface oxide film, 9
... Emitter electrode, 10 ... Base electrode, 11 ...
... Collector electrode, 12, 13 ... Resistance region, 13
~15, 17... Wiring, 16... P-type buried area, 50... Input bonding pad (input external lead-out terminal), 55... Grounding bonding pad (ground external lead-out terminal), 60... Power supply bonding pad (power supply external lead terminal).

Claims (1)

[Claims] 1 In an integrated circuit having a first and a second transistor, the first base-emitter current path and the collector-emitter current path of the second transistor are connected in series between two external lead-out terminals. , a current limiting resistor for a surge voltage supplied between the two external lead-out terminals is connected to the second
1. A semiconductor device configured in a collector region of a transistor.