JPH04323860A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent an erroneous operation of a semiconductor integrated circuit by providing a capacitor connected to a power source wiring and a ground wiring on a wiring region. CONSTITUTION:An area of a wiring region between units A and B is decided according to a power source wiring 7, a ground wiring 9, and signal wirings 11-1 - 11-4. A capacitor is formed of a lower layer wiring layer 6 and an N-type diffused layer 2 with a gate oxide film as a dielectric on the wiring region. The layer 2 of one electrode of the capacitor is connected to the wiring 9 via an N<+> type diffused layer 3 and a contact hole 10, and the layer 6 of the other electrode is connected to the wiring 7 via a contact hole 8. Noise of the wiring 7 can be absorbed to a ground point, noise of the wiring 9 can be absorbed to a power source, and the noise can be attenuated. Thus, an erroneous operation of a semiconductor integrated circuit can be prevented.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly to power supply wiring and ground wiring.

0002

[Prior Art] A mask pattern for a conventional semiconductor integrated circuit consists of an area where logic elements such as transistors are assembled to form one function (hereinafter referred to as a unit), and a wiring area where these elements do not exist. Figure 2
As shown in the figure, the power supply wiring 7 and the ground wiring 9 are drawn out from the power supply pad 7p and the ground pad 9p, respectively, and are supplied to the units A to E through the wiring area.

These power supply wiring 7 and ground wiring 9 are routed by metal wiring with extremely low resistance so as to withstand changes in current. Therefore, if noise gets onto the power supply wiring or ground wiring, the noise will be transmitted to each unit without being absorbed.

0004

[Problems to be Solved by the Invention] In the above-mentioned conventional semiconductor integrated circuit, no means for absorbing noise is provided in the power supply wiring or ground wiring, so if noise is picked up on these wiring, it is directly transmitted to the unit. , which caused malfunctions.

[0005]

[Means for Solving the Problems] The semiconductor integrated circuit of the present invention is such that a capacitor is provided in the wiring area of a semiconductor chip, with one electrode connected to a ground wiring and the other electrode connected to a power wiring. It is.

[0006]

Embodiment FIG. 1(a) is a plan view of a semiconductor chip showing an embodiment of the present invention, and FIG. 1(b) is a sectional view taken along the line X--X in FIG. 1(a).

The wiring area between unit A and unit B includes a power supply wiring 7, a ground wiring 9, and signal wiring 11-1 to 11-.
4 determines its area. In this wiring region, a lower wiring layer 6 such as a polysilicon film and an N-type diffusion layer 2 form a capacitor using the gate oxide film 5 as a dielectric. N type diffusion layer 2 which is one electrode of this capacitor
is connected to a ground wiring 9 through an N+ type diffusion layer 3 and a contact hole 10, and the lower wiring layer 6, which is the other electrode, is connected to a power supply wiring 7 through a contact hole 8.

[0008] With this capacitor, noise carried on the power supply wiring can be absorbed by the ground point, noise carried on the ground wiring can be absorbed by the power supply, and the noise can be attenuated. Such capacitors can be created anywhere on the chip where power supply wiring and ground wiring are present without changing the area of the chip.

In this embodiment, the present invention is applied to a CMOS IC.

0010

As explained above, the present invention provides a capacitor connected to the power supply wiring and the ground wiring in the wiring area, thereby absorbing noise on the power supply wiring and the ground wiring, thereby preventing malfunctions of semiconductor integrated circuits. can be prevented.

[0011]Furthermore, the charges stored in the capacitor can suppress fluctuations in the potential of the power supply wiring and the ground wiring, making it possible to supply more stable power supply potential and ground potential. Moreover, creating such a capacitor does not increase the chip area.

[Brief explanation of drawings]

FIG. 1 is a plan view (FIG. 1(a)) and a cross-sectional view (FIG. 1(b)) of a semiconductor chip showing one embodiment of the present invention.

FIG. 2 is a plan view showing an example of wiring layout in a semiconductor integrated circuit.

[Explanation of symbols]

1 P-type silicon substrate 2 N-type diffusion layer 3 N+ type diffusion layer 4 Field oxide film 5 Interlayer insulation film 6 Lower wiring layer 7 Power wiring 7p Power pad 8 Contact hole 9 Ground wiring 9p Ground pad 10 Contact hole 11-1 to 11-4 Signal wiring A~E Unit

Claims (1)

[Claims] 1. A semiconductor integrated circuit characterized in that a capacitor having one electrode connected to a ground wiring and the other electrode connected to a power supply wiring is provided in a wiring area of a semiconductor chip.