US20020008303A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- US20020008303A1 US20020008303A1 US09/760,800 US76080001A US2002008303A1 US 20020008303 A1 US20020008303 A1 US 20020008303A1 US 76080001 A US76080001 A US 76080001A US 2002008303 A1 US2002008303 A1 US 2002008303A1
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- layer
- wiring layer
- collector
- diffusion layer
- emitter
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- 239000004065 semiconductor Substances 0.000 title claims description 25
- 238000009792 diffusion process Methods 0.000 claims abstract description 68
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 167
- 239000000758 substrate Substances 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 208000032368 Device malfunction Diseases 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- QHGVXILFMXYDRS-UHFFFAOYSA-N pyraclofos Chemical compound C1=C(OP(=O)(OCC)SCCC)C=NN1C1=CC=C(Cl)C=C1 QHGVXILFMXYDRS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
Definitions
- the present invention relates to a semiconductor device such as lateral bipolar transistor and diode.
- FIG. 5 is a plan view showing a conventional semiconductor device, for example, a lateral bipolar transistor as shown in Japanese Patent No. 2,665,820
- FIG. 6 is a front view in section taken along the line II-II of FIG. 5.
- the lateral bipolar transistor is that the emitter, base, and collector are formed on the same surface as that of a substrate crystal, and components in parallel to the surface of the flow of minor careers which are injected from the emitter dominate the operation of the transistor.
- the present invention is implemented to solve the foregoing drawbacks. It is therefor an object of the present invention to provide a semiconductor device which is capable of preventing the occurrence of a leakage current from the emitter diffusion layer to the device isolation region, even under such a condition that a reverse bias is applied to the collector.
- a semiconductor device comprising: an epitaxial layer formed on a semiconductor substrate; a device isolation region formed with a predetermined surrounding frame pattern in the epitaxial layer; an emitter diffusion layer and a collector diffusion layer which are formed in the surface area of the epitaxial layer in the device isolation region, a frame pattern of the collector diffusion layer being laid out in a fashion to surround the emitter diffusion layer; an insulating layer formed on the epitaxial layer; an emitter electrode wiring layer that is led from the emitter diffusion layer through a first contact hole opened in the insulating layer; a collector electrode wiring layer that is led from the collector diffusion layer through a second contact hole opened in the insulating layer; and a control wiring layer which is laid down under the emitter electrode wiring layer, and which is applied a voltage according to a reverse bias voltage to be applied to the collector diffusion region.
- control wiring layer is be arranged on the insulating layer that is formed on the surface of the epitaxial layer, and that an interlayer dielectric is formed between the control wiring layer and the emitter electrode wiring layer.
- the semiconductor device may further comprise a base diffusion layer laid out on the outer surface area of the collector diffusion layer, and a base electrode wiring layer that is led from the base diffusion layer through a third contact hole opened in the insulating layer in the device isolation region.
- a voltage not less than a reverse bias voltage applied to the collector diffusion layer may be applied to the control wiring layer.
- a voltage less than a reverse bias voltage applied to the collector diffusion layer is applied to the control wiring layer.
- the base electrode wiring layer may be connected to the collector electrode wiring layer.
- FIG. 1 is a plan view showing a semiconductor device in accordance with an embodiment 1 of the present invention.
- FIG. 2 is a sectional front view taken along the line I-I of FIG. 1;
- FIG. 3 is a sectional front view enlarging a part of FIG. 2;
- FIG. 4 is a plan view showing a semiconductor device in accordance with an embodiment 4 of the present invention.
- FIG. 5 is a plan view showing a conventional semiconductor device
- FIG. 6 is a sectional front view taken along the line II-II of FIG. 5.
- FIG. 1 is a plan view showing a semiconductor device in accordance with an embodiment 1 of the present invention
- FIG. 2 is a sectional front view taken along the line I-I of FIG. 1
- FIG. 3 is a sectional front view enlarging a part of FIG. 2.
- reference numeral 21 designates a p+type semiconductor substrate
- 22 designates an n+type buried layer for reducing collector series resistances
- 23 designates an n or an- type epitaxial layer
- 24 designates a p+ type device isolation region with a rectangular frame pattern which connects to the substrate 21 .
- PSG
- the aforementioned wiring layers 32 , 33 , 34 , and 35 are typically constituted of an aluminum-based metal and the like.
- the frame patterns of the device isolation region 24 and the collector diffusion region 27 are rendered by lithography, are not limited to a rectangular pattern, and may be substituted by a circular, oval, square, polygonal, or other closed pattern.
- the semiconductor device according to the embodiment 1 is distinguishable from the conventional semiconductor device in the following points.
- control wiring layer 35 is laid down under the emitter electrode wiring layer 33 and on the insulating oxide 28 , and thus a voltage not less than a reverse bias voltage applied to the collector diffusion layer 27 or a voltage preventing the channel inversion of the epitaxial layer 23 has to be applied to the wiring layer 35 .
- the emitter electrode wiring layer 13 is put in a potential lower than that of the collector diffusion layer 7 .
- the application voltage of the collector diffusion layer 7 is raised to reach the reverse breakdown voltage BV EOC , as shown in FIG. 6, the inversion layer (hole 15 ) is formed on the surface of the epitaxial layer 3 under the emitter electrode wiring layer 13 .
- control wiring layer 35 works to shield an electric field generated by the emitter electrode wiring layer 33 because of the aforementioned distinction, thereby preventing the formation of the inversion layer in the region X as shown in FIG. 3. For this reason, there are no current flows from the collector diffusion layer 27 to the emitter diffusion layer 26 and, at the same time, there are no leakage current flows to the device isolation region 24 in connection with the occurrence of a leakage current from the emitter diffusion layer 26 .
- JP-A 59/151460 discloses a technique which arranges a wiring layer as described above over the whole effective base region.
- this technique does not assume such a situation that a reverse bias voltage is applied to the collector, and also is different from an aspect that the control wiring layer 35 is laid down at the underpart of the emitter electrode wiring layer 33 , thus to be incapable of preventing the occurrence of the leakage current from the emitter diffusion layer 26 .
- the control wiring layer 35 is laid down under the emitter electrode wiring layer 33 so that a certain voltage according to a reverse bias voltage to be applied to the collector diffusion layer 27 may be applied to the control wiring layer, thereby preventing the occurrence of a leakage current from the emitter diffusion layer 26 to the device isolation region 24 , even under a condition that a reverse bias voltage is applied to the collector. In such a way, power consumption and malfunction of the device may be reduced, and the enhancement of the reverse breakdown voltage BV EOC between the collector and emitter enables the operation range of the device.
- the embodiment 1 describes an example such that a voltage not less than the bias voltage to be applied to the collector diffusion layer 27 is applied to the wiring layer 35 , but a voltage less than the reverse voltage may be applied to the wiring layer 35 .
- the embodiment 1 describes an example that the emitter electrode wiring layer 33 is led to the right hand of the drawing, it is not limited to this, and may be led in the front (lower hand of FIG. 1) or rear (upper hand of FIG. 1) direction.
- the wiring layer 35 When the emitter electrode wiring layer 33 is led in the front direction of FIG. 1, the wiring layer 35 must be laid down under the emitter electrode wiring layer 33 between the front collector diffusion layer 27 and the emitter diffusion layer 26
- the wiring layer 35 must be laid down under the emitter electrode layer 33 between the rear collector diffusion layer 27 and the emitter diffusion layer 26 .
- the embodiment 1 describes an example that constructs a lateral transistor, as shown in FIG. 4, it may be used as a diode by connecting the base electrode wiring layer 32 and the collector electrode wiring layer 34 , thereby achieving the same effect as the aforementioned embodiment 1.
- the pnp bipolar transistor is described by way of illustrative example, but the same effect may be obtained also by an npn transistor.
- a control wiring layer is laid down under an emitter electrode wiring layer so that a voltage according to a reverse bias voltage to be applied to the collector diffusion layer may be applied to the control wiring layer, thereby preventing the occurrence of a leakage current even under a condition that a reverse bias voltage is applied to the collector.
- control wiring layer since the control wiring layer is arranged on an insulating layer formed on the surface of an epitaxial layer, the control wiring layer may be laid down under the emitter electrode wiring layer.
- control wiring layer is applied a voltage not less than a reverse bias volt-age that is applied to the collector diffusion layer, the occurrence of an inversion layer may-be prevented surely.
- the semiconductor device since the base and collector electrode wiring layers are connected to each other, the semiconductor device may be used as a diode.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device such as lateral bipolar transistor and diode.
- 2. Description of Related Art
- FIG. 5 is a plan view showing a conventional semiconductor device, for example, a lateral bipolar transistor as shown in Japanese Patent No. 2,665,820, and FIG. 6 is a front view in section taken along the line II-II of FIG. 5. In FIGS. 5 and 6,
reference numeral 1 designates a semiconductor substrate; 2 designates an n+ type buried layer; 3 designates an epitaxial layer; 4 designates a device isolation region; 5 designates a base diffusion region; 6 designates an emitter diffusion region; 7 designates a collector diffusion region; 8 designates an insulating oxide, which is an insulating layer; 9, 10, and 11 each designate a contact hole; 12 designates a wiring layer for a base electrode; 13 designates an emitter electrode wiring layer; 14 designates a collector electrode wiring layer; 15 designates a hole; 16 designates an electron; and 17 designates an interlayer dielectric. - Here, the lateral bipolar transistor is that the emitter, base, and collector are formed on the same surface as that of a substrate crystal, and components in parallel to the surface of the flow of minor careers which are injected from the emitter dominate the operation of the transistor.
- The operation will be next described below.
- Typically, under such a condition that a reverse bias voltage is applied to the collector of the lateral transistor, the potential of the emitter is lowered, while the potential applied to the
collector diffusion layer 7 is raised. Thus, when the voltage difference between the collector and the emitter is made larger than a reverse breakdown voltage BVEOC, there are some occasions that a current flows out from thecollector diffusion layer 7 to theemitter diffusion layer 6. In the example of FIGS. 5 and 6, however, since thecollector diffusion layer 7 is separated under the emitterelectrode wiring layer 13, there are no current flows from thecollector diffusion layer 7 to theemitter diffusion layer 6. - However, in the example of FIGS. 5 and 6, when the emitter
electrode wiring layer 13 has a lower potential than that of thecollector diffusion layer 7, and the application voltage of thecollector diffusion layer 7 is raised to reach the reverse breakdown voltage BVEOC, an inversion layer (hole 15) is formed on the surface of theepitaxial layer 3, which is positioned under the emitterelectrode wiring layer 13. For this reason, a leakage current from theemitter diffusion layer 6 occurs and flows out to thedevice isolation region 4. - Since the conventional semiconductor device is configured as described above, a leakage current occurs from the
emitter diffusion layer 6 under such a condition that a reverse bias is applied to the collector of the lateral transistor, and further the leakage current flows out to thedevice isolation region 4, causing increased consumption power, device malfunctions, and so on. Thus, the operation range of the device cannot be enlarged. - The present invention is implemented to solve the foregoing drawbacks. It is therefor an object of the present invention to provide a semiconductor device which is capable of preventing the occurrence of a leakage current from the emitter diffusion layer to the device isolation region, even under such a condition that a reverse bias is applied to the collector.
- According to a first aspect of the present invention, there is provided a semiconductor device comprising: an epitaxial layer formed on a semiconductor substrate; a device isolation region formed with a predetermined surrounding frame pattern in the epitaxial layer; an emitter diffusion layer and a collector diffusion layer which are formed in the surface area of the epitaxial layer in the device isolation region, a frame pattern of the collector diffusion layer being laid out in a fashion to surround the emitter diffusion layer; an insulating layer formed on the epitaxial layer; an emitter electrode wiring layer that is led from the emitter diffusion layer through a first contact hole opened in the insulating layer; a collector electrode wiring layer that is led from the collector diffusion layer through a second contact hole opened in the insulating layer; and a control wiring layer which is laid down under the emitter electrode wiring layer, and which is applied a voltage according to a reverse bias voltage to be applied to the collector diffusion region.
- Here, it is preferable that the control wiring layer is be arranged on the insulating layer that is formed on the surface of the epitaxial layer, and that an interlayer dielectric is formed between the control wiring layer and the emitter electrode wiring layer.
- In addition, the semiconductor device may further comprise a base diffusion layer laid out on the outer surface area of the collector diffusion layer, and a base electrode wiring layer that is led from the base diffusion layer through a third contact hole opened in the insulating layer in the device isolation region.
- Further, a voltage not less than a reverse bias voltage applied to the collector diffusion layer may be applied to the control wiring layer.
- Alternatively, a voltage less than a reverse bias voltage applied to the collector diffusion layer is applied to the control wiring layer.
- Furthermore, the base electrode wiring layer may be connected to the collector electrode wiring layer.
- FIG. 1 is a plan view showing a semiconductor device in accordance with an
embodiment 1 of the present invention; - FIG. 2 is a sectional front view taken along the line I-I of FIG. 1;
- FIG. 3 is a sectional front view enlarging a part of FIG. 2;
- FIG. 4 is a plan view showing a semiconductor device in accordance with an
embodiment 4 of the present invention; - FIG. 5 is a plan view showing a conventional semiconductor device; and
- FIG. 6 is a sectional front view taken along the line II-II of FIG. 5.
- An embodiment of the present invention will be described below.
- FIG. 1 is a plan view showing a semiconductor device in accordance with an
embodiment 1 of the present invention, FIG. 2 is a sectional front view taken along the line I-I of FIG. 1, and FIG. 3 is a sectional front view enlarging a part of FIG. 2. In FIGS. 1 to 3,reference numeral 21 designates a p+type semiconductor substrate; 22 designates an n+type buried layer for reducing collector series resistances; 23 designates an n or an- type epitaxial layer; and 24 designates a p+ type device isolation region with a rectangular frame pattern which connects to thesubstrate 21. -
Reference numeral 25 designates an n+ type base diffusion layer; 26 designates an p+ type emitter diffusion layer; 27 designates a p+ type collector diffusion layer in a fashion to surround theemitter diffusion layer 26; 28 designates an insulating oxide (insulating layer) such as silicon oxide formed on the surface of theepitaxial layer 23; 29, 30, and 31 designate third, first, and second contact holes, respectively; 32 designates a base electrode wiring layer that is led from theemitter diffusion layer 25 through thethird contact hole 29; 33 designates an emitter electrode wiring layer that is led from theemitter diffusion layer 26 through thefirst contact hole 30; 34 designates a collector electrode wiring layer that is led from thecollector diffusion layer 27 through thesecond contact hole 31; 35 designates a control wiring layer to which is applied a voltage corresponding to a reverse bias voltage to be applied to thecollector diffusion layer 27; and 36 designates a interlayer dielectric such as PSG (phosphosilicate glass). - The
aforementioned wiring layers device isolation region 24 and thecollector diffusion region 27 are rendered by lithography, are not limited to a rectangular pattern, and may be substituted by a circular, oval, square, polygonal, or other closed pattern. - The operation will be next described below.
- The semiconductor device according to the
embodiment 1 is distinguishable from the conventional semiconductor device in the following points. - First, the middle portion (i.e., in the vicinity of intersecting the above wiring layer33) on the right side of the
collector diffusion layer 27, which is formed in a rectangular frame pattern, is not separated, and a frame pattern of thecollector diffusion layer 27 is formed in a fashion to surround theemitter diffusion layer 26 by lithography. - Secondly, the
control wiring layer 35 is laid down under the emitterelectrode wiring layer 33 and on theinsulating oxide 28, and thus a voltage not less than a reverse bias voltage applied to thecollector diffusion layer 27 or a voltage preventing the channel inversion of theepitaxial layer 23 has to be applied to thewiring layer 35. - In the case of the prior art of FIG. 5, under such a condition that the reverse bias voltage is applied to the collector of the lateral transistor, the emitter
electrode wiring layer 13 is put in a potential lower than that of thecollector diffusion layer 7. When the application voltage of thecollector diffusion layer 7 is raised to reach the reverse breakdown voltage BVEOC, as shown in FIG. 6, the inversion layer (hole 15) is formed on the surface of theepitaxial layer 3 under the emitterelectrode wiring layer 13. - However, in the case of the
embodiment 1, thecontrol wiring layer 35 works to shield an electric field generated by the emitterelectrode wiring layer 33 because of the aforementioned distinction, thereby preventing the formation of the inversion layer in the region X as shown in FIG. 3. For this reason, there are no current flows from thecollector diffusion layer 27 to theemitter diffusion layer 26 and, at the same time, there are no leakage current flows to thedevice isolation region 24 in connection with the occurrence of a leakage current from theemitter diffusion layer 26. - Therefore, it is possible that the reverse breakdown voltage BVEOC between the collector and emitter is remarkably enhanced, which may ensure a wide operation range of the aforementioned lateral transistor or semiconductor device.
- On the other hand, JP-A 59/151460 discloses a technique which arranges a wiring layer as described above over the whole effective base region. However, this technique does not assume such a situation that a reverse bias voltage is applied to the collector, and also is different from an aspect that the
control wiring layer 35 is laid down at the underpart of the emitterelectrode wiring layer 33, thus to be incapable of preventing the occurrence of the leakage current from theemitter diffusion layer 26. - As described above, according to the
embodiment 1, thecontrol wiring layer 35 is laid down under the emitterelectrode wiring layer 33 so that a certain voltage according to a reverse bias voltage to be applied to thecollector diffusion layer 27 may be applied to the control wiring layer, thereby preventing the occurrence of a leakage current from theemitter diffusion layer 26 to thedevice isolation region 24, even under a condition that a reverse bias voltage is applied to the collector. In such a way, power consumption and malfunction of the device may be reduced, and the enhancement of the reverse breakdown voltage BVEOC between the collector and emitter enables the operation range of the device. - The
embodiment 1 describes an example such that a voltage not less than the bias voltage to be applied to thecollector diffusion layer 27 is applied to thewiring layer 35, but a voltage less than the reverse voltage may be applied to thewiring layer 35. - In this case, though it is possible that an inversion layer is formed slightly on the surface of the epitaxial layer, the formation degree of the inversion layer can be controlled smaller than that of the above-described prior art.
- Though the
embodiment 1 describes an example that the emitterelectrode wiring layer 33 is led to the right hand of the drawing, it is not limited to this, and may be led in the front (lower hand of FIG. 1) or rear (upper hand of FIG. 1) direction. - When the emitter
electrode wiring layer 33 is led in the front direction of FIG. 1, thewiring layer 35 must be laid down under the emitterelectrode wiring layer 33 between the frontcollector diffusion layer 27 and theemitter diffusion layer 26 - Alternatively, when the emitter
electrode wiring layer 33 is led in the rear direction thereof, thewiring layer 35 must be laid down under theemitter electrode layer 33 between the rearcollector diffusion layer 27 and theemitter diffusion layer 26. - Though the
embodiment 1 describes an example that constructs a lateral transistor, as shown in FIG. 4, it may be used as a diode by connecting the baseelectrode wiring layer 32 and the collectorelectrode wiring layer 34, thereby achieving the same effect as theaforementioned embodiment 1. - In the above-described embodiments, the pnp bipolar transistor is described by way of illustrative example, but the same effect may be obtained also by an npn transistor.
- As described above, according to the present invention, in a lateral bipolar transistor, a control wiring layer is laid down under an emitter electrode wiring layer so that a voltage according to a reverse bias voltage to be applied to the collector diffusion layer may be applied to the control wiring layer, thereby preventing the occurrence of a leakage current even under a condition that a reverse bias voltage is applied to the collector.
- According to the present invention, since the control wiring layer is arranged on an insulating layer formed on the surface of an epitaxial layer, the control wiring layer may be laid down under the emitter electrode wiring layer.
- According to the present invention, since the control wiring layer is applied a voltage not less than a reverse bias volt-age that is applied to the collector diffusion layer, the occurrence of an inversion layer may-be prevented surely.
- According to the present invention, since the base and collector electrode wiring layers are connected to each other, the semiconductor device may be used as a diode.
Claims (6)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2000-219325 | 2000-07-19 | ||
JP2000219325A JP2002043319A (en) | 2000-07-19 | 2000-07-19 | Semiconductor device |
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US20020008303A1 true US20020008303A1 (en) | 2002-01-24 |
US6399999B2 US6399999B2 (en) | 2002-06-04 |
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US09/760,800 Expired - Fee Related US6399999B2 (en) | 2000-07-19 | 2001-01-17 | Semiconductor device with extra control wiring for improving breakdown voltage |
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JP (1) | JP2002043319A (en) |
Cited By (1)
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CN102623793A (en) * | 2011-02-01 | 2012-08-01 | 华硕电脑股份有限公司 | Multi-input multi-output antenna system |
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DE10008635A1 (en) | 2000-02-24 | 2001-09-06 | Basf Ag | Process for the preparation of polyether polyols |
JP2003243522A (en) * | 2002-02-20 | 2003-08-29 | Mitsubishi Electric Corp | Semiconductor device using resistor element |
JP3882712B2 (en) * | 2002-08-09 | 2007-02-21 | 住友電気工業株式会社 | Submount and semiconductor device |
US8587023B2 (en) * | 2005-05-25 | 2013-11-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Guard rings with local coupling capacitance |
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JPS59151460A (en) | 1983-02-17 | 1984-08-29 | Ricoh Co Ltd | Semiconductor device |
JPH02220445A (en) | 1989-02-21 | 1990-09-03 | Mitsubishi Electric Corp | Semiconductor device |
JP2654268B2 (en) * | 1991-05-13 | 1997-09-17 | 株式会社東芝 | How to use semiconductor devices |
JP3818673B2 (en) * | 1993-03-10 | 2006-09-06 | 株式会社デンソー | Semiconductor device |
US6054752A (en) * | 1997-06-30 | 2000-04-25 | Denso Corporation | Semiconductor device |
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2000
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CN102623793A (en) * | 2011-02-01 | 2012-08-01 | 华硕电脑股份有限公司 | Multi-input multi-output antenna system |
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