JPH01241159A - Cmos circuit element - Google Patents

Abstract

PURPOSE:To suppress occurrence of latching up, by forming the edge regions of a parasitic thyristor with semiconductor materials having band gaps which are smaller than those of regions that are adjacent to the above edge regions and have polarity which is opposite to that of the foregoing edge regions. CONSTITUTION:The edge regions 14a' and 16a' of a parasitic thyristor which is formed in a CMOS circuit element are composed of semiconductor materials having band gaps which are smaller than those of regions 12 and 10 that are adjacent to the above regions 14a' and 16a' and have polarity which is opposite to that of the foregoing regions 14a' and 16a'. As this configuration makes the emitter injection efficiency of parasitic transistors 30 and 32 deteriorate, the current amplification factor of the parasitic transistors 30 and 32 decreases. Thus, positive feedback to loops which are formed by parasitic transistors 30 and 32 becomes difficult and the occurrence of latching up is suppressed.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (Figure 1) Working Example 1 Extended Example Effect of the Invention [Summary] With regard to CMOS circuit elements in which parasitic thyristors are formed, the end region of the parasitic thyristor formed in the CMOS circuit element is placed adjacent to and connected to the CMOS circuit element in order to prevent latch-up from occurring even when miniaturized. The region is made of a semiconductor material having a bandgap smaller than the bandgap of the region opposite in polarity.

[Industrial Application Field] The present invention is directed to a CMO in which a parasitic thyristor is formed inside.
Regarding S circuit elements.

[Conventional technology] FIG. 2 shows a cross-sectional structure of a conventional CMOS inverter.

In the figure, IO is an n-type Si substrate, 12 is a p-well, 14a is a source consisting of an n0 diffusion region, l 4 b 1. t n
16a is a source consisting of a p° diffusion region, 16b is a drain consisting of a p9 diffusion region, 18 and 20 are gate oxide films, 22 and 24 are gate electrodes, and 25 is a p well Ill. These are a p0 diffusion region for applying a potential, and an n° diffusion region for applying a potential to the n-type Si substrate No. 26.

The gate electrodes 22 and 24 are commonly connected to a signal input terminal 27, and the drains 14b and 16b are commonly connected to a signal output terminal 26.

In addition, 30 is a source 16a1n in the CMOS inverter.
It is a pnp type parasitic transistor naturally formed in the lateral direction by the Si substrate lO and the p well 12, and 32 is a CM
Source 14a% p-well and n-type S in OS inverter
This is an npn type parasitic transistor naturally formed in the vertical direction by the i-substrate IO. These parasitic transistors 30, 3
2 constitutes a parasitic thyristor. 34 and 36
is the parasitic substrate resistance.

As is well-known in this parasitic thyristor, for example, when a large noise current is applied from the drain 14b, the parasitic transistor 32 is turned on, a current flows from the Voo terminal to the GND terminal 1, the base voltage of the parasitic transistor 30 decreases, and the parasitic transistor T , is turned on. As a result, positive feedback is applied to the loop formed by the parasitic transistors 30 and 32, causing the pnpn thyristor to enter a low resistance state, and even when the noise current disappears, a steady large current flows, resulting in so-called latch-up.

As a measure to suppress this latch-up, the depth d of the p-well 12 is increased, and the distance Q between the p-well 12 and the source 16a is
It has been proposed to reduce the current amplification factors of the parasitic transistors 30 and 32 as long as .

The same applies to other CMOS circuit elements.

, [Problem to be solved by the invention] However, increasing the depth d and lengthening the distance g means C
This goes against the demand for higher integration due to miniaturization of MOS circuit elements.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a class circuit element that is less likely to cause love bubbles even when miniaturized.

[Means for Solving the Problems] The present invention will be described with reference to the configuration diagram of an embodiment shown in FIG.

In the figure, 14a', 16&'' are end regions of parasitic thyristors formed within the CMOS circuit element.

This end region 14a° or 16a' (one or both) is composed of a semiconductor material having a bandgap smaller than that of the region 12 or IO adjacent to and opposite in polarity to the end region 14a° or 16a'.

[Function] Parasitic transistor 30.32 forming a parasitic thyristor
Since the emitter injection efficiency of the parasitic transistors 30 and 32 decreases, the current amplification factors of the parasitic transistors 30 and 32 decrease.

Therefore, the occurrence of rubia tuberculosis is suppressed.

[Embodiments] (1) - Embodiment FIG. 1 is a block diagram of an embodiment of the present invention, showing a cross-sectional structure of a CMOS inverter, which is one of the CMOS circuit elements. In this figure, the same components as those in FIG. 2 are given the same reference numerals, and their explanations will be omitted.

This CMOS inverter consists of the one shown in Figure 2 and the pn
The source 14a' which is both end regions of the pn parasitic thyristor
and 16a' are different.

That is, the source 14 a' is made of a material (narrow gap material) whose band gap is smaller than that of the p-well adjacent to the source 14 a and having the opposite polarity.
, for example, is constructed using a 5iGe compound semiconductor. The source 14a' is formed on the p-well at a position corresponding to the source 14a shown in FIG. 2 by vapor phase growth. Similarly, the source 16a° has a bandgap equal to that of the source 16a.

It is composed of a material smaller than the bandgap of the n-type Si substrate IO, which is adjacent to and has the opposite polarity, such as a 5iGe compound semiconductor.
It is formed by vapor phase growth at a position corresponding to the source 16a shown in FIG.

According to this configuration, since the emitter injection efficiency of the parasitic transistors 30.32 decreases, the parasitic transistors 30.32.
The current amplification factor of 32 decreases. Therefore, positive feedback is less likely to be applied to the loop formed by parasitic transistors 30 and 32, and the occurrence of latch-up is suppressed.

As the source 14a', p-type S iG e (G e15%
), and the source 16a' is n-type S iG e (G
When using 15% (e15%), the holding voltage of the parasitic thyristor, which was conventionally about 2 to 3 V, increased to 12 to 13 V, and therefore love stubble could be sufficiently prevented.

Thereby, it is possible to further miniaturize the CMOS circuit element than in the past.

(2) Expansion Note that in the above embodiment, the case where both the sources 14a° and 16a', which are the end regions of the parasitic thyristor, are made of narrow-gap material is explained, but only one of the end regions is made of narrow-gap material. It may be composed of a gap material.

Further, although an inverter has been described as a CMOS circuit element, the present invention may be applied to any circuit element in which a parasitic thyristor is formed, and the present invention is of course applicable to other circuit elements.

Furthermore, if this CMOS circuit element is operated at a low temperature, the emitter injection efficiency will be reduced, so that negative layer latch-up can be suppressed.

[Effects of the Invention] As explained above, according to the present invention, the end region of the parasitic thyristor formed in the CMO8 circuit element is separated from the bandgap of the region adjacent to the region and opposite in polarity to the end region of the parasitic thyristor. It is made of a semiconductor material with a small bandgap, which reduces the emitter injection efficiency and the current amplification factor of the parasitic transistor that makes up the parasitic thyristor, which has the excellent effect of suppressing the occurrence of latch-up. , it greatly contributes to the miniaturization of CMOS circuit elements and the high integration of ICs.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view of a CMOS inverter showing the configuration of an embodiment of the present invention, and FIG. 2 is a vertical cross-sectional view of a conventional CMOS inverter. 10: N-type St substrate 12: P well 14a, 14a', 16a116a': Source 14b%
16b Nidrain 3G, 32: Parasitic transistor

Claims (1)

[Claims] A parasitic thyristor (1
6a', 10, 12, 14a) end regions (14a, 1
6a) adjacent to the region (14a', 16a') and having opposite polarity to the region (14a', 16a').
10) A CMO comprising a semiconductor material having a band gap smaller than the band gap of
S circuit element.