JPH02305460A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

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Publication number
JPH02305460A
JPH02305460A JP12732489A JP12732489A JPH02305460A JP H02305460 A JPH02305460 A JP H02305460A JP 12732489 A JP12732489 A JP 12732489A JP 12732489 A JP12732489 A JP 12732489A JP H02305460 A JPH02305460 A JP H02305460A
Authority
JP
Japan
Prior art keywords
electrode
capacitor
layer
circuit
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12732489A
Other languages
Japanese (ja)
Inventor
Taketoshi Shiine
雄寿 椎根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP12732489A priority Critical patent/JPH02305460A/en
Publication of JPH02305460A publication Critical patent/JPH02305460A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To lessen a capacitor in forming area and to enable a chopper type comparator to operate at a high speed by a method wherein the capacitor accumulating an analog voltage is composed of a first and a second electrode, and a semiconductor is biased by a power source independent of that of a circuit which deals with a digital signal. CONSTITUTION:A certain conductivity type semiconductor substrate 14, a reverse type conductivity type semiconductor layer 15 formed on the substrate 14, a capacitor first electrode 17 formed of a first layer polysilicon provided onto the semiconductor layer 15 through the intermediary of a field oxide film 16, and a capacitor second electrode 19 formed of a second layer polysilicon provided onto the first electrode 17 through the intermediary of an insulating film 18 are provided. The semiconductor layer 15 is biased by a power source independent of that of a circuit which deals with a digital signal. By this setup, digital noises are prevented from affecting the capacitor of an analog circuit and the capacitor is not required to be made unneessarily large, so that the capacitor can be made small in forming area and a chopper type comparator can be made to operate at a high speed.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は、デジタル信号を扱う回路とアナログ信号を扱
う回路が混在する半導体集積回路に関し、特に、アナロ
グ回路内に使用されるコンデンサの構造に関する。
Detailed Description of the Invention (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit in which a circuit that handles digital signals and a circuit that handles analog signals coexist, and in particular, the structure of a capacitor used in an analog circuit. Regarding.

(ロ)従来の技術 一般に、映像信号などのアナログ信号を久方してデジタ
ル信号に変換し、デジタル信号処理を行う集積回路にお
いては、アナログ回路とデジタル回路が混在して1つの
半導体基板上に形成される。
(b) Conventional technology In general, in integrated circuits that convert analog signals such as video signals into digital signals and perform digital signal processing, analog and digital circuits are mixed on one semiconductor substrate. It is formed.

従来、上述の集積回路では、チョッパ型コンパレータを
使用したA/D変換回路が多用される。
Conventionally, in the above-mentioned integrated circuit, an A/D conversion circuit using a chopper type comparator is often used.

第2図は、チョッパ型コンパレータの回路図であり、(
1)はアナログ入力電圧■1.Iを選択するアナログゲ
ート、(2)は基準電圧V 、E、を選択するアナログ
ゲート、(3)はアナログゲート(1)及び(2)の出
力に一方の電極が接続されたコンデンサ、(4)は、コ
ンデンサ(3)の他方の電極に入力が接続された反転増
幅回路、(5)は反転増幅回路(4)の入出力間に接続
されたアナログゲート、(6)は反転増幅回路(4)の
出力が印加されたインバータである。
Figure 2 is a circuit diagram of a chopper type comparator, (
1) is the analog input voltage ■1. (2) is an analog gate that selects reference voltages V and E, (3) is a capacitor whose one electrode is connected to the output of analog gates (1) and (2), and (4) is an analog gate that selects I. ) is an inverting amplifier circuit whose input is connected to the other electrode of the capacitor (3), (5) is an analog gate connected between the input and output of the inverting amplifier circuit (4), and (6) is an inverting amplifier circuit ( 4) is an inverter to which the output is applied.

第2図の回路の動作を簡単に説明すると、サンプル期間
にアナログゲート(1)がOFF、アナログゲート(2
)及びアナログゲート(5)がONになると、コンデン
サ(3)の両端の電圧はVTII−VIEP(V T□
は反転増幅回路(4)のスレショルド電圧)となる。こ
の状態で、次の比較期間にアナログゲート(1)がON
、アナログゲート(2)及び(5)がOFFになると、
反転増幅回路(4)の入力電圧は、アナログ入力端子■
いにコンデンサ(3)に充電された電圧が重畳された電
圧、(VIJI  VREF) +VTHとなる。従っ
て、V 、、−V RE、が正になるか負になるかによ
って反転増幅回路(4)の出力が“L”レベルあるいは
′H”レベルの方向に11幅され、インバータ(6)か
らVlsとVIIEFの比較結果が出力される。
To briefly explain the operation of the circuit in Fig. 2, during the sample period, the analog gate (1) is OFF, and the analog gate (2) is OFF.
) and the analog gate (5) are turned on, the voltage across the capacitor (3) becomes VTII-VIEP (V T□
is the threshold voltage of the inverting amplifier circuit (4). In this state, the analog gate (1) is turned on in the next comparison period.
, when analog gates (2) and (5) are turned off,
The input voltage of the inverting amplifier circuit (4) is connected to the analog input terminal■
The voltage obtained by superimposing the voltage charged in the capacitor (3) becomes (VIJI VREF) +VTH. Therefore, depending on whether V,, -VRE, becomes positive or negative, the output of the inverting amplifier circuit (4) is shifted by 11 degrees in the direction of "L" level or 'H' level, and Vls from the inverter (6). The comparison result between VIIEF and VIIEF is output.

ト述ノチョッパ型コンパレータに用いられるコンデンサ
(3)は、第3図の如く形成さ!Lる。N型の半導体基
板(7)の主面に周知のLOGO5技術によって形成さ
れたフィールド酸化膜(8)上に第1層ポリシリコンで
形成された第1電極(9)が設けられる。さらに、第t
t極(9)上に酸化膜(10ンを介して第2?1電極(
11)が第2層ポリシリコンによって形成される。また
、第2電極(11)上には酸化膜(12)を介して、ア
ルミニュームの第3tTh(13)が、第1電極(9)
とコンタクト孔を介して接続さ11で形成される。この
構造により、第1電掻(9)と第2電極(11)によっ
て形成されるコンデンサと第21電極(11)と第3電
極(]3)によって形成されるコンデンサとが並列接続
された形となる。
The capacitor (3) used in the chopper type comparator is formed as shown in Figure 3! L. A first electrode (9) made of a first layer of polysilicon is provided on a field oxide film (8) formed on the main surface of an N-type semiconductor substrate (7) by the well-known LOGO5 technique. Furthermore, the tth
On the t-electrode (9), the second to first electrodes (
11) is formed by the second layer polysilicon. Further, on the second electrode (11), a third tTh (13) made of aluminum is placed on the first electrode (9) via an oxide film (12).
A contact hole 11 is connected to the contact hole. With this structure, a capacitor formed by the first electrode (9) and the second electrode (11) and a capacitor formed by the 21st electrode (11) and the third electrode (]3) are connected in parallel. becomes.

(ハ)発明が解決しようとする課題 第3図に示された半導体基板(7)は電源電圧にバイア
スされており、半導体基板(7)と第1電極(9)の間
にもコンデンサが存在する。通常、電源電圧は、デジタ
ル回路部とアナログ回路部に共通に印加されているため
、デジタル回路部においてMOSトランジスタが多数同
時にオンした場合などに電源電圧の変動が発生すると、
半導体基板(7)と第1t極(9)の間のコンデンサに
より、チョッパ型コンパレータのコンデンサ(3)に充
電された電圧が変化し、チョッパ型コンパレータの閉度
が悪化する欠点がある。この様なデジタルノイズの影響
を小さくするには、コンデンサ(3)の容量を大きくす
ることが考えられるが、そうすると、コンデンサ(3)
が半導体基板上に占める面積が大きくなり、且つ、チョ
ッパ型コンパレータの動作速度が遅くなり好ましくない
(c) Problems to be solved by the invention The semiconductor substrate (7) shown in Figure 3 is biased to the power supply voltage, and a capacitor also exists between the semiconductor substrate (7) and the first electrode (9). do. Normally, the power supply voltage is commonly applied to the digital circuit section and the analog circuit section, so if a fluctuation in the power supply voltage occurs, such as when many MOS transistors are turned on at the same time in the digital circuit section,
There is a drawback that the voltage charged in the capacitor (3) of the chopper type comparator changes due to the capacitor between the semiconductor substrate (7) and the first t-pole (9), and the closing degree of the chopper type comparator deteriorates. In order to reduce the influence of such digital noise, it is possible to increase the capacitance of capacitor (3).
This is undesirable because it occupies a large area on the semiconductor substrate and slows down the operating speed of the chopper type comparator.

(ニ)課題を解決するための手段 本発明は上述した点に鑑みて創作されたものであり、−
4電型の半導体基板と、該半導体基板に形成された逆4
電型の半1!体層と、該半導体層上にフィールド酸化膜
を介して設けられ第1層ポリシリコンで形成されたコン
デンサの第1電極と、該第1電極上に絶縁膜を介して設
けられ第2層のポリシリコンで形成されたコンデンサの
第21電極とを備え、前記半導体層を前記デジタル信号
を扱う回路の電源と独立した電源でバイアスすることに
より、デジタルノイズによってチョンパ型コンパレータ
のコンデンサに蓄積された電圧の変動を防止することを
目的とする。
(d) Means for solving the problem The present invention was created in view of the above points, and -
A 4-electrode type semiconductor substrate and an inverted 4-electrode type semiconductor substrate formed on the semiconductor substrate.
Electric model half 1! a first electrode of a capacitor formed of first layer polysilicon provided on the semiconductor layer via a field oxide film; and a second layer of polysilicon provided on the first electrode via an insulating film. and a 21st electrode of a capacitor made of polysilicon, and by biasing the semiconductor layer with a power supply independent of the power supply of the circuit that handles the digital signal, the voltage accumulated in the capacitor of the Chompa type comparator due to digital noise can be reduced. The purpose is to prevent fluctuations in

(ホ)作用 上述の手段によれば、第1電極、第2電極及び第3電極
の直下にはデジタル回路部の電源とは分離独立した電圧
にバイアスされた半導体層が存在し、この半導体層が半
導体基板に印加された電源電圧の変動の影響を第1電極
、第2電極及び第3電極に及ぼすのを防止する。
(E) Effect According to the above-mentioned means, there is a semiconductor layer biased to a voltage that is separate and independent from the power supply of the digital circuit section, and this semiconductor layer is present directly under the first, second, and third electrodes. This prevents the first, second, and third electrodes from being affected by fluctuations in the power supply voltage applied to the semiconductor substrate.

(へ)実施例 第1図は、本発明の実施例を示す断面図である。半導体
基板(14)は、N型の不純物を含み、その−主面上に
は図示しないデジタル回路及びアナログ回路が形成され
、デジタル回路とアナログ回路に共通のt原電圧VDD
が印加される。チョッパ型コンパレータのコンデンサが
形成される半導体基板(14)内にはP型の不純物を含
むP−WELL(15)が形成され、P−WE L L
(15)の一部を除いて、周知のLOGO5技術により
フィールド酸化膜(I6)が形成される。このフィール
ド酸化膜(16)上には、MOSトランジスタのゲート
を形成する第1層ポリシリコンを選択的にエツチングす
ることによって、第1t極(17)が形成される。この
第1電極(17)を覆ってCVD法によりシリコン酸化
膜(18)が設けられ、更に、シリコン酸化膜(18)
を介して、第1電極(17)と重畳する位置に第2電極
(19)が、配線のための第2層ポリシリコンを選択的
にエツチングすることによって形成される。この第2″
1極(19)は、第2図に示された反転増幅回路(4)
の第1層ポリシリコンで構成されたゲートに延在され接
続される。また、第2層電極(19)ヒには、CVD法
によってシリコン酸化膜(20)が形成され、このシリ
コン酸化膜(20)を介してアルミニュームの第3電極
(21)が、シリコン酸化膜(18)(20)に形成さ
れたコンタクト孔によって第1電掻(17)と接続され
て形成される。この第3電極(21)は、シリコン酸化
膜(20)上を延在されて、第2図に示されたアナログ
ゲート(1)(2)の各出力に接続される。一方、P−
WE L L(14)内には、P+型のコンタクト領域
(22)が形成され、シリコン酸化膜(18)(20)
に形成されたコンタクト孔を介して電源型fJii(2
3)に接続される。@源電極(23)は、第3電極(2
1)と同時にアルミニュームで形成され、アナログ回路
の接地電源AV5.が接続される電源バンド(図示せず
)に延在接続される。接地電源AvSsは、デジタル回
路の接地電源D V s sとは完全に独立して設けら
れる。
(F) Embodiment FIG. 1 is a sectional view showing an embodiment of the present invention. The semiconductor substrate (14) contains N-type impurities, has a digital circuit and an analog circuit (not shown) formed on its main surface, and has a common voltage VDD for the digital circuit and the analog circuit.
is applied. A P-WELL (15) containing P-type impurities is formed in the semiconductor substrate (14) on which the capacitor of the chopper comparator is formed, and P-WE L L
A field oxide film (I6) is formed by the well-known LOGO5 technique except for a part of (15). A first t-pole (17) is formed on the field oxide film (16) by selectively etching the first layer polysilicon forming the gate of the MOS transistor. A silicon oxide film (18) is provided by a CVD method to cover this first electrode (17), and a silicon oxide film (18) is further provided.
A second electrode (19) is formed at a position overlapping with the first electrode (17) via selective etching of the second layer polysilicon for wiring. This second''
One pole (19) is the inverting amplifier circuit (4) shown in Figure 2.
The gate is extended and connected to the gate made of the first layer of polysilicon. Further, a silicon oxide film (20) is formed on the second layer electrode (19) by the CVD method, and a third electrode (21) made of aluminum is formed through the silicon oxide film (20). (18) is connected to the first electric scraper (17) through the contact hole formed in (20). This third electrode (21) extends over the silicon oxide film (20) and is connected to each output of the analog gates (1) and (2) shown in FIG. On the other hand, P-
A P+ type contact region (22) is formed in the WE L L (14), and a silicon oxide film (18) (20) is formed.
Power supply type fJii (2
3). @The source electrode (23) is the third electrode (2
1) At the same time, it is made of aluminum and has a ground power supply AV5. is extended and connected to a power supply band (not shown) to which is connected. The ground power supply AvSs is provided completely independently of the ground power supply D Vss of the digital circuit.

第1図の構成によれば、第1電極(17)と第2電極(
19)とで形成されるコンデンサと、第2電極(19)
と第31電極(21)で形成されたコンデンサとが並列
接続されてチョッパ型コンパレータのコンデンサが構成
される。更に、第1電極(17)とP −WELL(1
4)との間にコンデンサが形成されるが、P−WELL
(14)は、アナログの接地電圧A V s sにバイ
アスされている為、デジタルノイズによって電源電圧V
 oo  D V ssが変動しても、コンデンサに蓄
積された電圧への影響はなくなる。
According to the configuration shown in FIG. 1, the first electrode (17) and the second electrode (
19) and a second electrode (19).
and a capacitor formed by the 31st electrode (21) are connected in parallel to form a capacitor of a chopper type comparator. Furthermore, the first electrode (17) and P-WELL (1
4) A capacitor is formed between P-WELL and P-WELL.
(14) is biased to the analog ground voltage A V s s , so the power supply voltage V
Fluctuations in oo D V ss have no effect on the voltage stored in the capacitor.

(ト)発明の効果 上述の発明によれば、デジタルノイズがアナログ回路の
コンデンサに与える影響がなくなり、コンデンサの容量
を必要以上に大きくする必要が無いので、コンデンサの
形成面積の減少となると共に、高速、高精度のチョッパ
型コンパレータ内蔵の半導体集積回路が実現できる。
(G) Effects of the Invention According to the above-described invention, the influence of digital noise on the capacitor of an analog circuit is eliminated, and there is no need to increase the capacitance of the capacitor more than necessary, which reduces the area in which the capacitor is formed. A semiconductor integrated circuit with a built-in high-speed, high-precision chopper-type comparator can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例を示す断面図、第2図はチョッ
パ型コンパレータの回路図、第3図は従来例を示す断面
図である。
FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a circuit diagram of a chopper type comparator, and FIG. 3 is a sectional view showing a conventional example.

Claims (3)

【特許請求の範囲】[Claims] (1)デジタル信号を扱う回路とアナログ信号を扱う回
路が混在する半導体集積回路において、一導電型の半導
体基板と、 該半導体基板に形成された逆導電型の半導体層と、 該半導体層上にフィールド酸化膜を介して設けられ第1
層ポリシリコンで形成された第1電極と、 該第1電極上に絶縁膜を介して設けられ第2層のポリシ
リコンで形成されたの第2電極と、を備え、前記第1電
極と第2電極でアナログ電圧を蓄積するコンデンサを構
成し、前記半導体層を前記デジタル信号を扱う回路の電
源と独立した電源でバイアスすることを特徴とする半導
体集積回路。
(1) In a semiconductor integrated circuit in which a circuit that handles digital signals and a circuit that handles analog signals coexist, a semiconductor substrate of one conductivity type, a semiconductor layer of the opposite conductivity type formed on the semiconductor substrate, and a semiconductor layer on the semiconductor layer. The first layer is provided through a field oxide film.
A first electrode formed of a layer of polysilicon, and a second electrode formed of a second layer of polysilicon and provided on the first electrode with an insulating film interposed between the first electrode and the second layer of polysilicon. A semiconductor integrated circuit comprising a capacitor that stores an analog voltage with two electrodes, and wherein the semiconductor layer is biased with a power source independent of a power source of a circuit that handles the digital signal.
(2)前記第2電極は、インバータのゲート電極から延
在された第1層ポリシリコンに接続されることを特徴と
する請求項1記載の半導体集積回路。
(2) The semiconductor integrated circuit according to claim 1, wherein the second electrode is connected to a first layer of polysilicon extending from a gate electrode of the inverter.
(3)前記第2電極上に絶縁膜を介して設けられ、前記
第1電極に接続されると共に、アナログ入力電圧と基準
電圧を選択的に出力するスイッチング素子に延在され接
続される第3電極を備え、該第3電極をコンデンサの一
方の電極とすることを特徴とする請求項1記載の半導体
集積回路。
(3) A third electrode provided on the second electrode via an insulating film, connected to the first electrode, and extending and connected to a switching element that selectively outputs an analog input voltage and a reference voltage. 2. The semiconductor integrated circuit according to claim 1, further comprising an electrode, and the third electrode is one electrode of a capacitor.
JP12732489A 1989-05-19 1989-05-19 Semiconductor integrated circuit Pending JPH02305460A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12732489A JPH02305460A (en) 1989-05-19 1989-05-19 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12732489A JPH02305460A (en) 1989-05-19 1989-05-19 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH02305460A true JPH02305460A (en) 1990-12-19

Family

ID=14957114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12732489A Pending JPH02305460A (en) 1989-05-19 1989-05-19 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH02305460A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5773872A (en) * 1995-10-25 1998-06-30 Nec Corporation Semiconductor device having an integrated differential circuit with an improved common-mode rejection ratio (CMRR)
US6064108A (en) * 1997-09-02 2000-05-16 Hughes Electronics Corporation Integrated interdigitated capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5773872A (en) * 1995-10-25 1998-06-30 Nec Corporation Semiconductor device having an integrated differential circuit with an improved common-mode rejection ratio (CMRR)
US6064108A (en) * 1997-09-02 2000-05-16 Hughes Electronics Corporation Integrated interdigitated capacitor

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