JPH0334250B2 - - Google Patents
Info
- Publication number
- JPH0334250B2 JPH0334250B2 JP15229782A JP15229782A JPH0334250B2 JP H0334250 B2 JPH0334250 B2 JP H0334250B2 JP 15229782 A JP15229782 A JP 15229782A JP 15229782 A JP15229782 A JP 15229782A JP H0334250 B2 JPH0334250 B2 JP H0334250B2
- Authority
- JP
- Japan
- Prior art keywords
- well
- electronic switch
- capacitive element
- conductivity type
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 14
- 239000003990 capacitor Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000005669 field effect Effects 0.000 claims description 2
- 230000000295 complement effect Effects 0.000 claims 1
- 102100034478 Cytokine-dependent hematopoietic cell linker Human genes 0.000 description 14
- 101000710210 Homo sapiens Cytokine-dependent hematopoietic cell linker Proteins 0.000 description 14
- 230000003071 parasitic effect Effects 0.000 description 10
- 239000003595 mist Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 102100021615 Class A basic helix-loop-helix protein 15 Human genes 0.000 description 3
- 101000971300 Homo sapiens Class A basic helix-loop-helix protein 15 Proteins 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
Landscapes
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、単一の半導体基板内へ一体的に作り
込まれた絶縁ゲート形電界効果トランジスタ（以
下MISTと略記する）で構成され、オーデイオ信
号などのアナログ信号の通路を開閉する電子スイ
ツチに関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is composed of an insulated gate field effect transistor (hereinafter abbreviated as MIST) that is integrated into a single semiconductor substrate, and is capable of transmitting audio signals, etc. This invention relates to an electronic switch that opens and closes an analog signal path.
従来例の構成とその問題点
単一の半導体基体内へ一体的に作り込まれた
MISTで構成された従来の電子スイツチは、第１
図で示すように、ｐチヤネルMIST１，２、ｎチ
ヤネルMIST３，４，５ならびにインバータ６を
結線し、端子７をスイツチの開閉を制御する切換
信号の入力端子、端子８をアナログ信号の入力端
子、そして端子９をアナログ信号の出力端子とし
た回路構成となつている。なお、１０は正電圧
（VDD）の印加端子、１１は負電圧（VSS）の印加
端子である。ところで、MIST１，２とMIST３
〜５のチヤネルの導電型は逆であり、MIST３，
４が同一のウエル、例えばｐウエル内に、また、
MIST５がこれとは異るｐウエル内に作り込まれ
ているものとすると、MIST３と４が作り込まれ
たｐウエルと基板との間に存在するpn接合によ
る寄性容量１２が図示する関係で回路内に存在す
るところとなる。Conventional structure and its problems Integrated into a single semiconductor substrate
The conventional electronic switch configured with MIST is
As shown in the figure, p-channel MISTs 1 and 2, n-channel MISTs 3, 4, and 5 and an inverter 6 are connected, terminal 7 is an input terminal for a switching signal that controls the opening and closing of the switch, terminal 8 is an input terminal for an analog signal, and terminal 8 is an input terminal for an analog signal. The circuit configuration is such that the terminal 9 is an analog signal output terminal. Note that 10 is a terminal for applying a positive voltage (V DD ), and 11 is a terminal for applying a negative voltage (V SS ). By the way, MIST1, 2 and MIST3
The conductivity type of channel ~5 is opposite, MIST3,
4 in the same well, e.g. p-well, and
Assuming that MIST5 is built in a different p-well, the parasitic capacitance 12 due to the pn junction existing between the p-well in which MISTs 3 and 4 are built and the substrate is in the relationship shown in the figure. It exists within the circuit.
以上のような回路構成とされた従来の電子スイ
ツチでは、MIST１と３はアナログ信号に対する
通路となり、MIST２と４はオン時にMIST３の
バツクゲートであるｐウエルをアナログ信号の入
力端に接続し、MIST１と３のオン抵抗の入力バ
イアスに対する非直線性打消し効果を高める作用
をしている。またMIST５はオフ時にMIST３の
バツクゲートであるｐウエルを負電圧（VSS）端
子１１に接続し、入出力間のフイードスルーの低
下をはかる作用をしている。ところで、オン時に
はMIST３のバツクゲートであるｐウエルはアナ
ログ信号の入力端子８へ接続されるため、このｐ
ウエルとｎ型基板との間のpn接合が逆バイアス
される。したがつて、pn接合によつてもたらさ
れる寄生容量１２が存在するところとなる。この
容量値はよく知られているように電圧に依存す
る。従つて、入力信号の山と谷とでは容量値が変
わりインピーダンスも変わる。入力信号の周波数
が高くなると、信号源インピーダンスと、この寄
生容量１２のインピーダンスで信号が分圧される
ことになり、入力信号の山と谷とで分圧比が変わ
り信号に歪が発生する。従来の電子スイツチにお
ける歪の入力信号周波数依存性を第３図の曲線Ａ
に示す。この例では信号源インピーダンスが
3.3KΩ、負荷インピーダンスが15KΩである。 In the conventional electronic switch with the above circuit configuration, MIST1 and 3 serve as paths for analog signals, and when MIST2 and 4 are turned on, the p-well, which is the back gate of MIST3, is connected to the input end of the analog signal, and MIST1 and This function enhances the effect of canceling the nonlinearity of the on-resistance of No. 3 on the input bias. Furthermore, when MIST5 is off, the p-well, which is the back gate of MIST3, is connected to the negative voltage (V SS ) terminal 11, thereby reducing the feedthrough between input and output. By the way, when on, the p-well, which is the back gate of MIST3, is connected to the analog signal input terminal 8, so this p-well is connected to the analog signal input terminal 8.
The pn junction between the well and the n-type substrate is reverse biased. Therefore, there is a parasitic capacitance 12 introduced by the pn junction. As is well known, this capacitance value depends on the voltage. Therefore, the capacitance value changes and the impedance changes between the peaks and valleys of the input signal. When the frequency of the input signal increases, the signal is divided by the signal source impedance and the impedance of the parasitic capacitance 12, and the voltage division ratio changes between peaks and valleys of the input signal, causing distortion in the signal. The input signal frequency dependence of distortion in a conventional electronic switch is shown by curve A in Figure 3.
Shown below. In this example, the source impedance is
3.3KΩ, load impedance is 15KΩ.
以上説明したように、従来の電子スイツチで
は、回路を単一の半導体基板内へ作り込むにあた
り、避けることのできないウエルの作り込みでも
たらされる寄生容量による歪発生を防ぐことはで
きなかつた。 As explained above, in conventional electronic switches, it has not been possible to prevent distortion due to parasitic capacitance caused by the inevitable formation of wells when circuits are built into a single semiconductor substrate.
発明の目的
本発明は、従来の電子スイツチにおいて問題と
なる歪を抑圧し、歪特性を改善した電子スイツチ
の提供を目的とするものである。OBJECTS OF THE INVENTION An object of the present invention is to provide an electronic switch that suppresses distortion that is problematic in conventional electronic switches and improves distortion characteristics.
発明の構成
本発明の電子スイツチは、ｐチヤネルMISTと
ｎチヤネルMISTで構成されるとともに、いずれ
か一方の導電チヤネル形のMISTを作り込む一導
電型のウエルが、スイツチオン時に信号通路に接
続される基本構成を具備し、さらに前記ウエルと
これの作り込まれる基板との間に形成されるpn
接合容量の電圧依存性を打ち消す接続関係で電圧
依存性をもつ可変容量素子を前記ウエルと基準電
位点との間に接続した構成を特徴とするものであ
り、この可変容量素子によつて、特に信号周波数
が高周波であるときに顕著になる歪を抑圧するよ
うにしている。Structure of the Invention The electronic switch of the present invention is composed of a p-channel MIST and an n-channel MIST, and the one-conductivity type well into which one of the conductive channel-type MISTs is built is connected to the signal path when the switch is turned on. It has a basic structure and is further formed between the well and the substrate on which it is formed.
It is characterized by a configuration in which a voltage-dependent variable capacitance element is connected between the well and a reference potential point in a connection relationship that cancels out the voltage dependence of the junction capacitance. Distortion that becomes noticeable when the signal frequency is high is suppressed.
実施例の説明
本発明の電子スイツチについて、回路構成例を
示す第２図ならびに、可変容量素子の構造例を示
す第４図を参照して以下に詳しく説明する。DESCRIPTION OF EMBODIMENTS The electronic switch of the present invention will be described in detail below with reference to FIG. 2 showing an example of a circuit configuration and FIG. 4 showing an example of a structure of a variable capacitance element.
第２図は、本発明の電子スイツチの一実施例を
示す図であり、第１図で示した従来の電子スイツ
チとは、容量素子１３が存在している点でのみ相
違し、他の構成は、従来の電子スイツチの構成と
同じである。ところで、容量素子１３は、寄性容
量１２と同様pn接合容量として付加されている
が、MIST３のバツクゲートに接続される側の導
電型は、寄性容量１２を付与するウエルの導電型
とは逆の導電型である。次に、本発明の電子スイ
ツチの動作を説明する。ウエルの導電型がｐ型で
あるとすると、寄生容量１２はMIST３のバツク
ゲート側がｐ型、正電圧（VDD）端子１０の側が
ｎ型であるから、アナログ入力３の電位が正方向
に高くなると、寄生容量１２の両端の電位差は小
さくなり、その容量は増加する。一方、容量素子
１３の両端の電位差は、このとき小さくなるた
め、その容量は減少し、寄性容量１２の容量の増
加を打消すように作用する。このため、信号源イ
ンピーダンスと、これらの容量による分圧比の入
力電圧レベルによる依存性は小さくなり、従つて
歪の発生が減少する。この容量素子１３の容量値
を最適化することにより大きな打消し効果が実現
できる。 FIG. 2 is a diagram showing an embodiment of the electronic switch of the present invention, which differs from the conventional electronic switch shown in FIG. 1 only in the presence of a capacitive element 13, and other configurations. is the same as the configuration of a conventional electronic switch. By the way, the capacitive element 13 is added as a pn junction capacitor like the parasitic capacitor 12, but the conductivity type of the side connected to the back gate of the MIST 3 is opposite to that of the well that provides the parasitic capacitor 12. conductivity type. Next, the operation of the electronic switch of the present invention will be explained. Assuming that the conductivity type of the well is p-type, the parasitic capacitance 12 is p-type on the back gate side of MIST 3 and n-type on the positive voltage (V DD ) terminal 10 side, so when the potential of analog input 3 increases in the positive direction, , the potential difference across the parasitic capacitance 12 becomes smaller and its capacitance increases. On the other hand, since the potential difference between both ends of the capacitive element 13 becomes small at this time, its capacitance decreases and acts to cancel out the increase in the capacitance of the parasitic capacitor 12. Therefore, the dependence of the signal source impedance and the voltage division ratio by these capacitances on the input voltage level is reduced, and therefore the occurrence of distortion is reduced. By optimizing the capacitance value of this capacitive element 13, a large canceling effect can be achieved.
以上の構成とされた本発明の電子スイツチにお
ける歪の入力信号周波数依存性を第３図の曲線Ｂ
に示す。従来の電子スイツチの曲線Ａと較べて大
きな打消し効果のあることが明らかである。 The input signal frequency dependence of distortion in the electronic switch of the present invention having the above configuration is expressed by curve B in FIG.
Shown below. It is clear that there is a greater canceling effect compared to curve A of the conventional electronic switch.
第４図は第２図の容量素子１３の具体的な形成
例を示す図であり、図示するようにMIST５のド
レイン拡散を拡げた構成となつている。すなわち
ｎ型シリコン基板１４に作られたMIST５の形成
用ｐウエル１５の中にMIST５を形成するための
n+型ドレイン領域１６とn+型ソース領域１７を
形成しているが、n+型ドレイン領域１６とｐウ
エル１５との間に形成されるpn接合で容量素子
１３を形成している。なお、図中１８は酸化膜、
１９はMIST５のゲート電極、２０はMIST５の
ドレイン電極とpn接合容量素子１３のカソード
電極を兼ねる電極、２１はMIST５のソース電極
とバツクゲート電極を兼ねる電極、そして２２は
p+型のガードバンド領域である。このように、
MIST５が歪抑圧用の容量素子１３を兼ねてお
り、このMIST５を第２図で示したように回路接
続することによつて、MIST２のバツクゲートと
負電圧（VSS）端子との間には容量素子１３が接
続されることになる。 FIG. 4 is a diagram showing a specific example of the formation of the capacitive element 13 shown in FIG. 2, which has a structure in which the drain diffusion of the MIST 5 is expanded as shown. That is, for forming MIST5 in the p-well 15 for forming MIST5 made in the n-type silicon substrate 14.
An n + type drain region 16 and an n + type source region 17 are formed, and a pn junction formed between the n + type drain region 16 and the p well 15 forms the capacitive element 13. In addition, 18 in the figure is an oxide film,
19 is the gate electrode of MIST5, 20 is the electrode that serves as the drain electrode of MIST5 and the cathode electrode of the pn junction capacitor 13, 21 is the electrode that serves as the source electrode and back gate electrode of MIST5, and 22 is the electrode that serves as the source electrode and back gate electrode of MIST5.
This is a p + type guard band region. in this way,
MIST5 also serves as a capacitive element 13 for distortion suppression, and by connecting this MIST5 in the circuit as shown in Figure 2, a capacitance is created between the back gate of MIST2 and the negative voltage (V SS ) terminal. Element 13 will be connected.
発明の効果
本発明の電子スイツチは、容量素子の付加によ
つて歪をもたらすことのないアナログ信号通路の
開閉を可能とするものであり、オーデイオ用機器
の性能を高める効果を奏する。また、歪特性が高
い信号周波数域まで改善されるため、電子スイツ
チの使用範囲を拡大する効果も奏する。Effects of the Invention The electronic switch of the present invention makes it possible to open and close an analog signal path without causing distortion due to the addition of a capacitive element, and has the effect of improving the performance of audio equipment. Furthermore, since the distortion characteristics are improved to a high signal frequency range, the range of use of the electronic switch can be expanded.
なお、以上説明した実施例では、ｎ型基板にｐ
ウエルを形成したCMOS構造で回路を実現して
いるが、これとは逆に、ｐ型基板内にｎ型ウエル
を形成したCMOS構造として回路を実現する場
合にも本発明を適用して、上記と同等の効果をう
ることができる。また、容量素子１３をMISTの
１つと一体的に形成した実施例の構造によると、
基板面積の利用率を高める効果が奏されるが、こ
の効果を特に重視する必要のないときには、容量
素子１３を独立した回路要素として作り込んでも
よい。さらに、pn接合容量にこだわることなく、
MIS形可変容量素子として容量素子１３を付加し
てもよい。 In addition, in the embodiment described above, the p-type substrate is
Although the circuit is realized using a CMOS structure in which a well is formed, the present invention can also be applied to realize a circuit as a CMOS structure in which an n-type well is formed in a p-type substrate. You can get the same effect. Furthermore, according to the structure of the embodiment in which the capacitive element 13 is integrally formed with one of the MISTs,
Although the effect of increasing the utilization rate of the substrate area is achieved, when this effect does not need to be particularly important, the capacitive element 13 may be built as an independent circuit element. Furthermore, without worrying about pn junction capacitance,
A capacitive element 13 may be added as an MIS type variable capacitive element.
第１図は、従来の電子スイツチの回路構成図、
第２図は、本発明にかかる電子スイツチの回路構
成図、第３図は、従来の電子スイツチ回路と本発
明の電子スイツチの歪特性を比較して示す図、第
４図は、歪抑圧用の容量素子の構成例図である。
１，２……ｐチヤネルMIST、３〜５……ｎチ
ヤネルMIST、６……インバータ、７……切換信
号入力端子、８……アナログ信号入力端子、９…
…アナログ信号出力端子、１０……正電圧
（VDD）端子、１１……負電圧（VSS）端子、１２
……寄性容量、１３……歪抑圧用の容量素子、１
４……ｎ型シリコン基板、１５……ｐ型ウエル、
１６……n+型ドレイン領域、１７……n+型ソー
ス領域、１８……酸化膜、１９……ゲート電極、
２０……ドレイン電極（容量素子電極）、２１…
…ソース電極（バツクゲート電極）、２２……ｐ
型ガードバンド領域。
Figure 1 is a circuit diagram of a conventional electronic switch.
Fig. 2 is a circuit diagram of the electronic switch according to the present invention, Fig. 3 is a diagram comparing the distortion characteristics of the conventional electronic switch circuit and the electronic switch of the present invention, and Fig. 4 is a diagram showing the distortion characteristics of the electronic switch of the present invention. FIG. 3 is a configuration example diagram of a capacitive element. 1, 2...p channel MIST, 3-5...n channel MIST, 6...inverter, 7...switching signal input terminal, 8...analog signal input terminal, 9...
... Analog signal output terminal, 10 ... Positive voltage (V DD ) terminal, 11 ... Negative voltage (V SS ) terminal, 12
... Parasitic capacitance, 13 ... Capacitive element for distortion suppression, 1
4...n-type silicon substrate, 15...p-type well,
16...n + type drain region, 17...n + type source region, 18...oxide film, 19...gate electrode,
20... drain electrode (capacitive element electrode), 21...
...Source electrode (back gate electrode), 22...p
Type guard band area.
Claims (1)
出力端子との間に並列接続され、ゲートに逆位相
関係で切換信号が印加される相補極性の絶縁ゲー
ト形電界効果トランジスタの一方が一導電型の半
導体基体内へ、他方が、同半導体基体内に形成し
た逆導電型のウエル内へそれぞれ作り込まれ、ス
イツチオン時に前記ウエルが信号通路に接続され
る構成を具備するとともに、前記ウエルと基準電
位点との間に、前記ウエルと半導体基板間に形成
されるpn接合容量の電圧依存性を打ち消す接続
関係で電圧依存性をもつ容量素子を接続したこと
を特徴とする電子スイツチ。 ２ 容量素子がpn接合容量で形成されているこ
とを特徴とする特許請求の範囲第１項に記載の電
子スイツチ。 ３ 容量素子が金属−絶縁体−半導体構造の容量
で形成されていることを特徴とする特許請求の範
囲第１項に記載の電子スイツチ。 ４ 容量素子が、異るウエルとこの中へ作り込ま
れた逆導電型の領域間のpn接合容量で形成され
ていることを特徴とする特許請求の範囲第１項に
記載の電子スイツチ。[Claims] 1. One side of a complementary polarity insulated gate field effect transistor in which the drain and source circuits are connected in parallel between a signal input terminal and a signal output terminal, and a switching signal is applied to the gate in an opposite phase relationship. One conductivity type is formed in a semiconductor substrate, and the other conductivity type is formed in an opposite conductivity type well formed in the same semiconductor substrate, and the well is connected to a signal path at the time of switch-on. An electronic switch characterized in that a capacitive element having voltage dependence is connected between a well and a reference potential point in a connection relationship that cancels the voltage dependence of a pn junction capacitance formed between the well and a semiconductor substrate. 2. The electronic switch according to claim 1, wherein the capacitive element is formed of a pn junction capacitor. 3. The electronic switch according to claim 1, wherein the capacitive element is formed of a capacitor having a metal-insulator-semiconductor structure. 4. The electronic switch according to claim 1, wherein the capacitive element is formed by a pn junction capacitance between different wells and regions of opposite conductivity type formed therein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15229782A JPS5941928A (en) | 1982-08-31 | 1982-08-31 | Electronic switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15229782A JPS5941928A (en) | 1982-08-31 | 1982-08-31 | Electronic switch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5941928A JPS5941928A (en) | 1984-03-08 |
| JPH0334250B2 true JPH0334250B2 (en) | 1991-05-22 |
Family
ID=15537441
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15229782A Granted JPS5941928A (en) | 1982-08-31 | 1982-08-31 | Electronic switch |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5941928A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2753308B2 (en) * | 1989-02-16 | 1998-05-20 | チタン工業株式会社 | Potassium hexatitanate fiber and method for producing the same |
| US6086844A (en) | 1996-12-26 | 2000-07-11 | Sumitomo Chemical Company, Ltd. | Titania fiber, method for producing the fiber and method for using the fiber |
-
1982
- 1982-08-31 JP JP15229782A patent/JPS5941928A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5941928A (en) | 1984-03-08 |
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