JPS5941928A - Electronic switch - Google Patents

Electronic switch

Info

Publication number
JPS5941928A
JPS5941928A JP15229782A JP15229782A JPS5941928A JP S5941928 A JPS5941928 A JP S5941928A JP 15229782 A JP15229782 A JP 15229782A JP 15229782 A JP15229782 A JP 15229782A JP S5941928 A JPS5941928 A JP S5941928A
Authority
JP
Japan
Prior art keywords
well
electronic switch
mists
type
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15229782A
Other languages
Japanese (ja)
Other versions
JPH0334250B2 (en
Inventor
Takeshi Kimura
武司 木村
Minoru Ito
稔 伊藤
Tatsuro Nagai
永井 辰郎
Toshikazu Fukuya
福家 利和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP15229782A priority Critical patent/JPS5941928A/en
Publication of JPS5941928A publication Critical patent/JPS5941928A/en
Publication of JPH0334250B2 publication Critical patent/JPH0334250B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors

Landscapes

  • Electronic Switches (AREA)

Abstract

PURPOSE:To improve a distortion characteristic and to extend the use range of switch, by constituting a circuit so that a well is connected to a signal path when the switch is turned on, and connecting a capacity element, which cancels the voltage dependence of p-n junction capacitance between the well and a substrate, between the well and a reference potential point. CONSTITUTION:An electronic switch circuit is provided with a circuit consisting of p type insulated gate FETs (MISTs) 1 and 2 and n type MISTs 3 and 4, and analog signal input and output terminals 8 and 9 and a switching signal input terminal 7 are connected to MISTs 1, 2, 3, and 4. MISTs 1 and 2 are formed in a p type semidonductor base material, and MISTs 3 and 4 are formed in an n type well formed in this base material. The circuit is so constituted that the well is connected to the signal path when the switch is turned on, and a disotortion suppressing capacity element 13 which cancels the voltage dependence of an pn parasitic capacitance 12 formed between the well and the semiconductor substrate and has the voltage dependence in the connection relation is connected between the well and a reference potential 11, thus improving the distortion characteristic.

Description

【発明の詳細な説明】 産業上の利用分野 不発明に、単一の半導体基板内へ一体的に作り込まnた
絶縁ゲート形電界効果トランジスタ(以下MISTと略
記する)で構成さn1オ一デイオ信号などのアナログ信
号の通路を開閉する電子スイッチに関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application Inventively, an insulated gate field effect transistor (hereinafter abbreviated as MIST) formed integrally within a single semiconductor substrate. It relates to electronic switches that open and close passages for analog signals such as signals.

従来例の構成とその問題点 単一の半導体基体内へ一体的に作り込ま几たMISTで
構成さnた従来の電子スイッチに、第1図で示すように
、pチャネルMIST1,2、nチャネルM :[S 
T 3+  4+  5ならびにインバータ6を結線し
、端子7をスイッチのh閉を制舞丁る切換信号の入力端
子、端子8をアナログ信号の入力端子、そして端子9を
アナログ信号の出力端子とした回路構成となっている。
Conventional configuration and its problems As shown in Figure 1, a conventional electronic switch consisting of MISTs integrated into a single semiconductor substrate has p-channel MISTs 1 and 2, and n-channel MISTs. M: [S
A circuit in which T3+4+5 and inverter 6 are connected, terminal 7 is an input terminal for a switching signal that prevents the switch from closing, terminal 8 is an input terminal for an analog signal, and terminal 9 is an output terminal for an analog signal. The structure is as follows.

なお、10ば正%JE (VDD ) (7) 印加端
子、11ば負電圧(Was )の印加端子である。とこ
ろで、MISTl、2とMIST3〜5のチャネルの導
電型は逆であり、MIST3.4が同一・のウェル、例
えばpウェル内に、また、MIST5がこnとは異るp
ウェル内に作り込inでいるものとすると、MIST3
と4が作り込1nたpウェルと基板との間に存在するp
n接合による容性容量12が図示する関係で回路内に存
在するところとなる。
Note that 10 is a positive %JE (VDD) (7) application terminal, and 11 is a negative voltage (Was) application terminal. By the way, the conductivity types of the channels of MIST1, 2 and MIST3-5 are opposite, and MIST3.4 is placed in the same well, for example, a p-well, and MIST5 is placed in a different p-well.
Assuming that it is built in the well, MIST3
and 4 are formed between the p-well and the substrate.
A capacitance 12 due to the n-junction is present in the circuit in the relationship shown.

以上のような回路構成とさnた従来の電子スイッチでに
、MISTlと3にアナログ信号に対する通路となり、
MIST2と4はオン時にMIST3のバックゲートで
あるpウェルをアナログ信号の入力端に接続し、MI 
ST1と3のオン抵抗の入力バイアスに対する非直線性
打消し効果を高める作用をしている。またMIST5は
オフ時にMIST3のバックゲートであるpウェルを負
電圧(Vss )端子11に接続し、入出力間のフィー
ドスルーの低下をほかる作用をしている。ところで、オ
ン時にはMIST3のバックゲートであるpウェルにア
ナログ信号の入力端子8へ接続さnるため、このpウェ
ルとn型基板との間のpn接合が逆バイアスさnる。し
たがって、pn接合によってもたらさnる寄生容量12
が存在するところとなる。この容量値によく知ら扛てい
るように電圧に依存する。従って、入力信号の山と谷と
でに容量値が変わりインピーダンスも変わる。入力信号
の周波数が高くなると、信号源インピーダンスと、この
寄生容量12のインピーダンスでi号が分圧さnること
になり、入力信号の山と谷とで分圧比が変わり信号に歪
が発生する。従来の電子スイッチにおける歪の入力信号
周波数依存性を第3図の曲線人に示す。この例でに信号
源インピーダンスが3,3にΩ、負荷インピーダンスが
15にΩである。
With the above circuit configuration and conventional electronic switch, MIST1 and 3 become a path for analog signals,
When MIST2 and 4 are on, the p-well, which is the back gate of MIST3, is connected to the analog signal input terminal, and the MIST
It functions to enhance the effect of canceling out the nonlinearity of the on-resistances of ST1 and ST3 with respect to the input bias. Furthermore, when MIST5 is off, the p-well, which is the back gate of MIST3, is connected to the negative voltage (Vss) terminal 11, which serves to reduce the decrease in feedthrough between input and output. By the way, since the p-well, which is the back gate of the MIST 3, is connected to the analog signal input terminal 8 when it is on, the p-n junction between the p-well and the n-type substrate is reverse biased. Therefore, the parasitic capacitance 12 caused by the pn junction
is where it exists. As is well known, this capacitance value depends on the voltage. Therefore, the capacitance value changes depending on the peaks and valleys of the input signal, and the impedance also changes. When the frequency of the input signal increases, the voltage of i is divided by the signal source impedance and the impedance of this parasitic capacitance 12, and the voltage division ratio changes between peaks and valleys of the input signal, causing distortion in the signal. . The input signal frequency dependence of distortion in a conventional electronic switch is shown by the curved line in FIG. In this example, the signal source impedance is 3.3Ω and the load impedance is 15Ω.

以上説明したように、従来の電子スイッチでは、回路を
単一の半導体基板内へ作り込むにあたり、避けることの
でキナいウェルの作り込みでもたらさnる容性容量によ
る歪発生を防ぐことばできな刀1つた〇 発明の目的 本発明に、従来の電子スイッチにおいて問題となる歪を
抑圧し、歪特性を改善した電子スイッチの提供を目的と
するものである。
As explained above, in conventional electronic switches, it is impossible to prevent distortion caused by capacitance caused by the fabrication of small wells when the circuit is fabricated on a single semiconductor substrate. 1. OBJECTS OF THE INVENTION It is an object of the present invention to provide an electronic switch that suppresses distortion that is a problem in conventional electronic switches and improves distortion characteristics.

発明の構成 不発明の電子スイッチに、pチャネルMISTとnチャ
ネルMISTで構成さnるとともに、いずnか一方の導
電チャネル形のMISTを作り込む一導電型のウェルが
、スイッチオン時に信号通路に接続さ几る基本構成を具
備し、さらに前記ウェルとこnの作り込1nる基板との
間に形成さnるpn接合容量の電圧依存性を打ち消す接
続関係で電圧依存性をもつ可変容量素子を前記ウェルと
基準電位点との間に接続した構成を特徴とするものであ
り、この可変容量素子によって、特に信号周波数が高周
波であるときに顕著になる歪を抑圧する工うにしている
Structure of the Invention The electronic switch of the present invention is composed of a p-channel MIST and an n-channel MIST, and a well of one conductivity type in which one of the conduction channel type MISTs is formed serves as a signal path when the switch is turned on. A variable capacitance element having a basic configuration connected to the well and having a voltage dependence due to a connection relationship that cancels the voltage dependence of the pn junction capacitance formed between the well and the substrate. is connected between the well and a reference potential point, and this variable capacitance element is used to suppress distortion that becomes noticeable especially when the signal frequency is high.

実施例の説明 不発明の電子スイッチについて、回路講成例を示す第2
図ならびに、可変容量素子の構造例を示す第4図を参照
して以下に詳しく説明する。
DESCRIPTION OF EMBODIMENTS A second example of a circuit course regarding an uninvented electronic switch is shown below.
A detailed explanation will be given below with reference to the drawings and FIG. 4 showing an example of the structure of a variable capacitance element.

第2図に、本発明の電子スイッチの一実施例を示す図で
あり、第1図で示した従来の電子スイッチとは、容量素
子13が存在している点でのみ相違し、他の構成は、従
来の電子スイッチの構成と同じである。ところヤ、容量
素子13は、容性容量12と同様pn接合容量として付
加さnているが、MIS・T3のバツクゲ−1・に接続
さnる側の導電型は、容性容量12を付与するウェルの
導電型とは逆の導電型である。次に、不発明の電子スイ
ッチの動作を説明する。ウェルの導電型がp型であると
すると、寄生容量12はMIST3のノくツクゲート側
がp型、正電圧(Vnn )端子10の側がn型である
から、アナログ人力3の電位が正方向に高くなると、容
性容量12の両端の電位差に小さくなり、その容量は増
加する。一方、容量素子13の両端の電位差に、このと
き小さくなるため、その容量に減少し、寄性容量12の
容量の増加を打消すように作用する。このため、信号源
インピーダンスと、こnらの容量による分圧比の入力電
圧レベルによる依存性ば小さくなり、従って歪の発生が
減少する。この容量素子13の容量値全最適化すること
にエリ大きな打消し効果が実現できる。
FIG. 2 is a diagram showing an embodiment of the electronic switch of the present invention, which differs from the conventional electronic switch shown in FIG. 1 only in the presence of a capacitive element 13, and other configurations. is the same as the configuration of a conventional electronic switch. However, the capacitive element 13 is added as a pn junction capacitor like the capacitive capacitor 12, but the conductivity type on the side connected to the back gate 1 of the MIS T3 gives the capacitive capacitor 12. The conductivity type of the well is opposite to that of the well. Next, the operation of the inventive electronic switch will be explained. Assuming that the conductivity type of the well is p-type, the parasitic capacitance 12 is p-type on the open gate side of MIST 3 and n-type on the positive voltage (Vnn) terminal 10 side, so the potential of analog human power 3 increases in the positive direction. Then, the potential difference between both ends of the capacitive capacitor 12 becomes small, and its capacitance increases. On the other hand, since the potential difference between both ends of the capacitive element 13 becomes small at this time, its capacitance decreases and acts to cancel out the increase in the capacitance of the parasitic capacitor 12. Therefore, the dependence of the signal source impedance and the voltage division ratio by these capacitances on the input voltage level is reduced, and therefore the occurrence of distortion is reduced. By fully optimizing the capacitance value of the capacitive element 13, a large canceling effect can be achieved.

以上の構成とさ几た本発明の電子スイッチにおける歪の
入力信号周波数依存性を第3図の曲線Bに示す。従来の
電子スイッチの曲線Aと較べて大キナ打消し効果のある
ことが明らかである。
Curve B in FIG. 3 shows the input signal frequency dependence of distortion in the electronic switch of the present invention constructed as described above. It is clear that there is a large kina canceling effect compared to curve A of the conventional electronic switch.

第4図は第2図の容量素子13の具体的な形成例を示す
図であり、図示する工うにMIST5のドレイン拡散を
拡げた構成となっている。すなわちn型シリコン基板1
4に作ら扛たMI ST5の形成用pウェル16の中に
MIST6を形成する  。
FIG. 4 is a diagram showing a specific example of the formation of the capacitive element 13 shown in FIG. 2, and has a structure in which the drain diffusion of the MIST 5 is expanded in the illustrated structure. That is, n-type silicon substrate 1
MIST 6 is formed in the p-well 16 for forming MIST 5 prepared in step 4.

ための−型ドレイン領域16と1型ソース領域17全形
成しているが、このn+型トドレイン領域16pウェル
16との間に形成さnるpn接合で容量素子13全形成
している。なお、図中18に酸化膜、191Ml5T5
(7)ゲート電極、20[1JIsT5のドレイン電極
とpn接合芥容量子13のカソード電極を兼ねる電極、
21iqMIST5のソース電極とバックゲート電極を
兼ねる電極、そして22ta、f型のガートバンド領域
である。このように、MIST5が歪抑圧用の容量素子
13を兼ねており、このMIST5を第2図で示しだ工
9に回路接続することによって、MIST2のバンクゲ
ートと負電圧(Vss )端子との間には容量素子13
が接続さnることになる。
A - type drain region 16 and a 1 type source region 17 are all formed for this purpose, and a capacitive element 13 is formed entirely by a pn junction formed between the n+ type drain region 16 and the p well 16. In addition, in the figure, 18 is an oxide film, 191Ml5T5
(7) a gate electrode, an electrode that also serves as the drain electrode of 20[1JIsT5 and the cathode electrode of the pn junction capacitor 13;
21iq is an electrode serving as the source electrode and back gate electrode of MIST5, and 22ta is an f-type guard band region. In this way, the MIST 5 also serves as the capacitive element 13 for distortion suppression, and by connecting the MIST 5 to the circuit 9 shown in FIG. 2, the connection between the bank gate of the MIST 2 and the negative voltage (Vss) terminal has a capacitive element 13
will be connected.

発明の効果 本発明の電子スイッチは、容量素子の伺加によって歪を
もたらすことのないアナログ信号通路の開閉を可能とす
るものであり、オーディオ用機器の性能を高める効果金
臭する。また、歪特性が高い信号周波数域まで改善さn
るため、電子スイッチの使用範囲を拡大する効果も奏す
る。
ADVANTAGEOUS EFFECTS OF THE INVENTION The electronic switch of the present invention enables the opening and closing of an analog signal path without causing distortion due to the addition of a capacitive element, and is highly effective in improving the performance of audio equipment. In addition, the distortion characteristics are improved up to the signal frequency range with high
This also has the effect of expanding the range of use of electronic switches.

なお、以上説明した実施例では、n型基板にpウェルを
形成した0MO3構造で回路を実現しているが、こnと
に逆に、p型基板内にn型ウェル全形成した0MO8構
造として回路を実現する場合にも本発明を適用して、上
記と同等の効果をうろことができる。また、容量素子1
3をMISTの1つと一体的に形成した実施例の構造に
よると、基板面積の利用率を高める効果が奏さnるが、
この効果を特に重視する必要のないときにば、容量素子
13を独立した回路要素として作り込んでもよい。さら
に、pn接合容量にこだわることなく、MIS形可変可
変容量素子て容量素子13を付加してもよい。
In the example described above, the circuit is realized with an 0MO3 structure in which a p-well is formed in an n-type substrate, but on the contrary, it is realized as an 0MO8 structure in which an n-type well is entirely formed in a p-type substrate. The present invention can also be applied to the case of realizing a circuit, and the same effects as those described above can be obtained. In addition, capacitive element 1
According to the structure of the embodiment in which MIST 3 is integrally formed with one of the MISTs, the effect of increasing the utilization rate of the substrate area is achieved.
If this effect does not need to be particularly important, the capacitive element 13 may be built as an independent circuit element. Furthermore, the capacitive element 13 may be added as an MIS type variable capacitive element without being particular about the pn junction capacitance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図に、従来の電子スイッチの回路構成図、第2図は
、不発明にかかる電子スイッチの回路構成図、第3図に
、従来の電子スイッチ回路と不発明の電子スイッチの歪
特性を比較して示す図、第4図に、歪抑圧用の容量素子
の構成例図である。 1.2・・・・・・pチャネルMIST、3〜6・・・
・・・nチャネルMIST16・・・・・・インバータ
、7・・・・・・切換信号入力端子、8・・・・・・ア
ナログ信号入力端子、9・・・・・・アナログ信号出力
端子、1o・・・・・・正電圧(VDD )端子、11
・・・・・・負電圧(Vss )端子、12・・・・・
・寄性容景、13・・・・・・歪抑圧用の容量素子、1
4・°°°°°n型シリコン基板、15・・・・・・p
型ウェル、16・・・・・・1型ドレイン領域、17・
・・・・・−型ソース領域、18・・・・・・酸化膜、
19・・・・・・ゲート電極、2o・・・・・・ドレイ
ン電極(容量素子電極)、21・・・・・・ソース電極
(バックゲート電極)、22・・・・・・p++ガート
バンド領域。 代理人の氏名 弁理士 中 尾 敏 男 はが1名第1
図 第2図
Fig. 1 is a circuit diagram of a conventional electronic switch, Fig. 2 is a circuit diagram of an electronic switch according to the invention, and Fig. 3 shows the distortion characteristics of the conventional electronic switch circuit and the electronic switch of the invention. A comparative diagram, FIG. 4, is a diagram illustrating a configuration example of a capacitive element for suppressing distortion. 1.2...p channel MIST, 3-6...
... n-channel MIST16 ... inverter, 7 ... switching signal input terminal, 8 ... analog signal input terminal, 9 ... analog signal output terminal, 1o...Positive voltage (VDD) terminal, 11
...Negative voltage (Vss) terminal, 12...
・Parasitic appearance, 13...Capacitive element for distortion suppression, 1
4.°°°°°n-type silicon substrate, 15...p
Type well, 16...1 type drain region, 17.
....-type source region, 18... ... oxide film,
19...Gate electrode, 2o...Drain electrode (capacitive element electrode), 21...Source electrode (back gate electrode), 22...p++ guard band region. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure 2

Claims (1)

【特許請求の範囲】 (1)  ドレイン、ソース回路が信号入力端子と信号
出力端子との間に並列接続さnl ゲートに逆位相関係
で切換信号が印加さnる相補極性の絶縁ゲート形電界効
果トランジスタの一方が一導電型の半導体基体内へ、他
方が、同半導体基体内に形成した逆導電型のウェル内へ
そnぞf作り込まn1スイツチオン時に前記ウェルが信
号通路に接続さnる構成を具備するとともに、前記ウェ
ルと基準電位点との間に、前記ウェルと半導体基板間に
形成さnるpn接合容量の電圧依存性を打ち消す接続関
係で電圧依存性をもつ容量素子を接続したことを特徴と
する電子スイッチ。 (鎚芥量素子がpn接合容量で形成さnていることを特
徴とする特許請求の範囲第1項に記載の電子スイッチ。 (3)容量素子が金属−絶縁体一半導体構造の容量で形
成さtていることを特徴とする特許請求の範囲第1項に
記載の電子スイッチ。 (4)容量素子が、異るウェルとこの中へ作p込まnた
逆導電型の領域間のpn接合容量で形成さnていること
を特徴とする特許請求の範囲第1項に記載の電子スイッ
チ。
[Claims] (1) Insulated gate type field effect with complementary polarity, in which the drain and source circuits are connected in parallel between the signal input terminal and the signal output terminal, and switching signals are applied to the gates in an opposite phase relationship. One of the transistors is formed in a semiconductor substrate of one conductivity type, and the other is formed in a well of an opposite conductivity type formed in the same semiconductor substrate, and the well is connected to a signal path when the switch is turned on. and a voltage-dependent capacitive element is connected between the well and the reference potential point in a connection relationship that cancels the voltage dependence of a pn junction capacitance formed between the well and the semiconductor substrate. Features an electronic switch. (The electronic switch according to claim 1, wherein the capacitive element is formed of a pn junction capacitor. (3) The capacitive element is formed of a capacitor of a metal-insulator-semiconductor structure. The electronic switch according to claim 1, characterized in that: (4) a pn junction between different wells and regions of opposite conductivity type in which capacitive elements are formed; An electronic switch according to claim 1, characterized in that it is formed of a capacitor.
JP15229782A 1982-08-31 1982-08-31 Electronic switch Granted JPS5941928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15229782A JPS5941928A (en) 1982-08-31 1982-08-31 Electronic switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15229782A JPS5941928A (en) 1982-08-31 1982-08-31 Electronic switch

Publications (2)

Publication Number Publication Date
JPS5941928A true JPS5941928A (en) 1984-03-08
JPH0334250B2 JPH0334250B2 (en) 1991-05-22

Family

ID=15537441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15229782A Granted JPS5941928A (en) 1982-08-31 1982-08-31 Electronic switch

Country Status (1)

Country Link
JP (1) JPS5941928A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02221460A (en) * 1989-02-16 1990-09-04 Titan Kogyo Kk Potassium hexatitanate fiber and production thereof
US6086844A (en) * 1996-12-26 2000-07-11 Sumitomo Chemical Company, Ltd. Titania fiber, method for producing the fiber and method for using the fiber

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02221460A (en) * 1989-02-16 1990-09-04 Titan Kogyo Kk Potassium hexatitanate fiber and production thereof
US6086844A (en) * 1996-12-26 2000-07-11 Sumitomo Chemical Company, Ltd. Titania fiber, method for producing the fiber and method for using the fiber
US6191067B1 (en) 1996-12-26 2001-02-20 Sumitomo Chemical, Ltd. Titania fiber, method for producing the fiber and method for using the fiber
US6409961B1 (en) 1996-12-26 2002-06-25 Sumitomo Chemical Co., Ltd. Titania fiber, method for producing the fiber and method for using the fiber

Also Published As

Publication number Publication date
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