JPH01175410A - Semiconductor analog switch - Google Patents

Abstract

PURPOSE:To cancel charges due to story capacity and to reduce an error voltage by forming a P channel transistor(TR) and an N channel TR in the same shape. CONSTITUTION:The P channel type MOS TR Q1 and N channel type MOS TR Q2 are equalized in areas and shape among sources and drains 72 and 73, and 82 and 83, in gate width and gate length between gates 71 and 82, in overlap quantity among the gates, sources, drains, and gate oxide film thickness, etc. When a clock signal phi is at 'H', the difference between a reference voltage and the threshold voltage of an inverting amplifier is sampled by the capacitor CS and when the phi goes down to 'L', an input voltage is applied to the input terminal of the CS to generate the difference between the reference voltage and input voltage at the output terminal of the CS and the difference is amplified by the inverting amplifier to perform comparing operation. At this time, the difference is set to the threshold voltage, so the error voltage due to an analog switch which biases the input and output of the inverting amplifier exert a large influence on the offset voltage of a comparator.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a semiconductor analog switch constituted by a CMOS transmission gate.

<Prior Art> In a semiconductor analog switch composed of MOS transistors, when the switch is turned off, an error occurs in the terminal voltage due to a change in the stray capacitance of the MOS transistor constituting the analog switch during its switching operation. Generates voltage.

FIG. 3 shows an example in which an analog switch using an NMOS transistor is used in a sample and hold circuit. In the circuit shown in FIG. 3, the MOS transistor Q3
When the signal of the gate 9 of is in the conductive state at °°H'', there is a stray capacitance C8d between the gate and drain.When the gate signal becomes "L" and is in the non-conductive state, Cgd becomes "o". ”, and the charge generated by this change in stray capacitance generates an error voltage at the output terminal (2).In order to reduce this, conventionally, as shown in Figure 4, the MO
MO8FE is a signal with the opposite phase of the gate signal that turns on and off S transistor Q4, and has the same capacitance value Ct as C8d.
TQs were connected so that the change in stray capacitance C3d when the gate signal changed from "H" to "L" was canceled out by the capacitance Ct induced by the gate signal having the opposite phase.

The same can be said of the transmission gate of the CMO8, and FIG. 5 shows an example in which an analog switch using a CMOS transistor is used in the sample and hold circuit. In conventional CMOS transmission gates, the PchFET and Nc
The driving capabilities of hFETs are matched, and as a result, both FEs
The shape of the T, especially the gate width, was different.

Also, as in the case of NMO8, there is a stray capacitance Cngd of NchFET and a stray capacitance Cpgd of PchFET,
An error voltage is generated due to a change in the amount of charge due to a change in stray capacitance that occurs when the CMO8 transmission gate becomes non-conductive due to a gate signal. Also NM
As with the OS example, conventionally the 6th circuit was used to suppress this.
The method shown in the figure was used. If you think about it in detail, C.
In the case of the MO8 trans/pump gate, the charge generated by the stray capacitance is canceled out because the Nch FET and PchFET have opposite charges when considering the drain side of the FET, and the charge of the difference between Cngd and Cpgd is the capacitance C. The error voltage is distributed by the junction capacitance C2 between the drain region and the substrate, and generates an error voltage. In order to reduce this, conventionally an NchFETO example (
MO8FETQ+o for compensation as in Fig. 4).

Qu was added.

Problems to be solved by the present invention: As described above, in order to use the conventional semiconductor analog switch, it is necessary to add a compensating MO8FET as shown in FIG.
This increases the number of elements and area. In addition, the increase in the number of elements makes them more susceptible to process effects, and the capacitance Ct
The probability that an error will occur in matching C3d and C3d also increases, making it difficult to achieve the desired design effect. Furthermore, there were other problems such as an increase in changing stray capacitance, and large noise and spike voltages during switching.

The present invention was created in view of the above points, and the solution →
Tomurugisuyori, especially regarding the analog switch configured by the CMO8 transmission gate, M.
An object of the present invention is to provide a semiconductor analog switch that easily reduces error voltage due to stray capacitance that is structurally parasitic to an OS transistor.

Means to Solve All Problems> In order to achieve the above object, the present invention provides a
The drain of the chMO8FET and the source of the NchMO8FET are connected, the other terminal is connected to the source of the Pch MOSFET Nc, the drain of the hMOSFE T, and the gates of the valleys are connected to the transmission gate of the CMO8, which is switched by signals having opposite phases to each other. In the analog switch composed of PchMO8FEi
” Regarding the shape of Nch MOSFET, the area shape of the source/drain, gate width, and gate length.

The transistors are formed with the same amount of overlap between the gate, the source, and the drain, and the thickness of the gate oxide film.

Effect> By forming the NchMO8FET and PchMO8FET in the same shape as described above, the stray capacitance caused by the structure of the MOSFET is reduced to that of the PchMO8FET.
is equal to NchMO8FET. In addition, the transme)'/, 7 gate of CMO8 is PchMO8FET
and NchMO8'FET are controlled by mutually opposite gate signals, ! Since the substrate voltages of each transistor are also opposite, the charges induced by stray capacitance always have the same amount of opposite charges on the source and drain sides, and they cancel each other out. 0'', it is possible to eliminate the accompanying error. Also, since no extra elements are added, the number of elements and the area do not increase, and deviations due to the process can be minimized.
The difference in drive capability between Pch FET and Pch FET causes nonlinearity of on-resistance, but when used in circuits where errors in terminal voltage are a problem, such as the sample-and-hold circuit shown in the example and the A/F converter, stray capacitance The larger problem is the fluctuation in terminal voltage due to The nonlinearity of the on-resistance is determined by each FET.
It can be made smaller by designing the on-resistance to be larger. In this case, the size of the FET becomes larger, but the element area is smaller than adding a compensation element, and by adding an additional element, Noise spikes generated during switching can be reduced by a circuit that suppresses stray capacitance,
This has the effect of suppressing the error voltage caused by this. This makes it possible to easily realize a semiconductor analog switch with few errors.

<Embodiment 2 Hereinafter, an embodiment of the present invention will be described in detail with reference to all the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which 1 is an input terminal, 2 is an output terminal, 3 is a switching gate signal input terminal, and 4 is a signal applied to the terminal 3. An input terminal for an anti-phase switching gate signal, Ql is a P-channel MOS transistor, and Q2 is a transistor Q according to the present invention.

This is an N-channel type MO8+- transistor formed in the same shape as the one shown in FIG. 7, and its pattern is shown in FIG.

In FIG. 7, 71 is a gate constituting a P-channel MOS transistor Q+', 72 and 73 are source and drain contacts of the same transistor, 74 is a P-channel diffusion region, 75 is an n-well, and 81 is an N-channel MOS transistor Q+'. A gate forming the type MOS transistor Q2, 8
2. 83 is the source and drain contacts of the same transistor, 84 is the N-channel diffusion region, 91 is the input side metal wiring, and 92 is the output side metal wiring. As shown in FIG. The area shape, gate width, gate length, and amount of overlap between the gate, source, and drain of each type MOS transistor Q2.

The gate oxide films are formed to have the same thickness (not shown).

Figure 2 shows the circuit configuration when the semiconductor analog switch of the present invention is used in an A/D converter comparator9.
In the figure, 5 is a reference voltage terminal, 6 is an input voltage terminal,
7 is a comparison output terminal. In the circuit configuration shown in FIG. 2, when the output signal φ is "H", the reference voltage and
The difference between the threshold voltage of the inverting amplifier and the threshold voltage is sampled by the capacitor C8, and when φ becomes °L'', the input voltage is applied to the input terminal of C, and the difference between the reference voltage and the input voltage is applied to the output terminal of C8. is generated and is amplified by the inverting amplifier to perform a comparison operation.At this time, the error voltage caused by the analog switch that biases the input and output of the inverting amplifier has a large effect on the offset voltage of the comparator because it is set to the threshold voltage. Here, by using the analog switch of the present invention, a comparator with a small offset voltage can be easily realized.

<Effects of the Invention> As described above, according to the present invention, by making the shapes of the P-channel transistor and the N-channel transistor the same, charges due to stray capacitance are canceled out, and the error voltage can be reduced. All you need to do is make the shapes of both transistors the same, and there is no need to add any other special elements, and the number of elements can be reduced.

There is no need to increase the area. It's ox, P Channel Nenope N
Even if there are differences in the channels, they can be made in the same shape and are less affected by the process. Therefore, according to the present invention, a CMOS analog switch with a small error voltage can be easily realized, and the effect is excellent.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the circuit configuration of a semiconductor analog switch according to an embodiment of the present invention, FIG. 2 is a diagram showing the circuit configuration when the present invention is used in an A/D converter comparator, and FIGS. 3 to 6
The figures each show a conventional circuit configuration, and FIG. 7 shows an example of a transistor pattern in the present invention. 1. Input terminal, 2. Output terminal, 3. Switching gate signal terminal, 4.. Signal terminal with opposite phase to 3, 5. Reference voltage terminal, 6. Input voltage terminal, 7. Comparison output terminal, 8.
Input terminal, 9 - Gate signal terminal, 10 Input terminal, 1 spike signal terminal, 12... Gate signal terminal with opposite phase to 11, 14.17 - Input terminal, 15.18 - Gate signal terminal, 16, 1915 .18 and opposite phase gate signal terminal, 71.81 gate, 72, 73, 82.83・source, drain contact, 74...P channel diffusion region, 75・n well, 84...N channel diffusion region, 91 Input end metal wiring, 92...Output side metal wiring L
Ql ・P channel MOS transistor, Q2Q
+ N-channel MOS transistor of the same shape as
Q3 ・N channel MOS transistor, Q4 ・N
Channel MOS transistor, Q5 N-channel MOS transistor with the same stray capacitance as Q4, Q6
．． Q8...P channel MOS transistor, Q71
Q9...N channel MO8+- transistor, Qlo-
A P-channel MOS transistor with the same stray capacitance as Qg, and an N-channel MOS transistor with the same stray capacitance as Qll...Q9. Agent: Patent attorney Takeshi Sugiyama (and 1 other person) Figure 2 Figure 7

Claims (1)

[Claims] 1. The source of the first P-channel MOS transistor and the drain of the first N-channel MOS transistor are connected to one terminal, and the drain of the first P-channel MOS transistor is connected to the other terminal. and the source of the first N-channel MOS transistor, and apply signals opposite in phase to the gates of each transistor.
In an analog switch consisting of a transmission gate, a P-channel MOS transistor and an N-channel MOS
The transistor is characterized in that the transistor is formed to have the same area shape of the source and drain, gate width, gate length, amount of overlap between the gate and the source and drain, and the thickness of the gate oxide film. Semiconductor analog switch.