KR960006107B1 - Low output capacitance, double-diffused field effect transistor - Google Patents

Abstract

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Description

Low Power-Capacitance Double Diffusion Field Effect Transistor

1 is an enlarged cross-sectional view in the main part of a DMOSFET embodiment according to the present invention;

2 is a circuit diagram corresponding to the DMOSFET of FIG.

3 is an enlarged cross-sectional view in the main part of another DMOSFET embodiment according to the present invention;

4 is a circuit diagram corresponding to the DMOSFET of FIG.

FIG. 5 is a circuit diagram showing a working phase of a solid state relay in which the DMOSFET of FIG. 3 is adopted as a power semiconductor device.

(Background of invention)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to power semiconductor devices having a low output capacity, and more particularly to a double-diffused metal oxide semiconductor field effect transistor ("DMOSFET").

The kind of DMOSFET mentioned can be effectively used in devices requiring high breakdown voltage, high speed switching and high noise resistance, such as power semiconductor devices such as solid state relays.

(Explanation of related technology)

In general, DMOSFETs exhibit high breakdown voltage, fast switching, and high noise resistance, and their structure provides high current density but lower ON-resistance than non-DMOS-type FETs. Moreover, DMOSFETs are so-called unipolar devices that have no off voltage, and therefore have the advantage of delivering signals without any distortion, and the use of DMOSFETs as power semiconductor devices in solid state relays has attracted interest.

On the other hand, when the conventional DMOSFET is used as a power semiconductor device in a solid state relay, there is a problem in that the output capacitance C _OSS becomes large. Where the output capacitance (C _OSS ) is the sum of the capacitance (C _GD ) between the gate and the drain and the capacitance ( _GS ) between the drain and the source, that is, C _OSS = C _GD + C _DS ′, in particular, the high frequency signal is turned on by the DMOSFET. There is a risk that the signal should leak through the output capacitance C _OSS if it is intended to be controlled / OFF.

For example, US Patent Nos. 3, 461, 360 to F. Barson et al. Disclose a basic arrangement of DMOSFETs, where one cup-shaped conductive band is provided surrounded by another conductive band. The cup-shaped conductive zone is formed along the hole made in the insulating film provided on the semiconductor substrate surface. See also R.J. A general DMOSFET is provided by forming a drain or source electrode on the bottom surface of the substrate in addition to the electrode formed on the top surface of the substrate as in US Patent No. 3, 484, 365 to Niebuis.

In another U. S. Patent No. 4, 455, 565 by AM Goodman et al., A shielding electrode is formed on an insulating film in a drain band on an upper surface having a source electrode of a semiconductor substrate, and a gate electrode is formed on the insulating film, but only on the channel region. Is formed at the position of. Substantially the same DMOSFET having a gate electrode on the insulating film only over the channel region is disclosed in US Pat. No. 4,466,175 to D. J. Coe.

According to Goodman and Coe's DMOSFETs, the arrangement is designed to reduce the gate-to-drain capacitance (C _GD ), resulting in lower output capacitance (C _OSS ).

However, in the DMOSFET by Goodman and Coe, the gate electrode should be applied, and the precision of this action in the gate electrode has been a problem despite the decrease of the capacitance (C _GD ) between the gate and the drain.

In addition, according to US Patent No. 4, 903, 636 by S. Akiyama et al., An apparatus in which the insulating film is made thicker in a portion located above the drain band on the upper surface of the semiconductor substrate can be made to reduce the capacity between the gate and the drain. Is disclosed. However, in such an arrangement, when the gate voltage is applied, an accumulation layer can hardly be formed in the drain band under the gate electrode, and the ON resistance is increased. US Patent No. 4, 009, 483 to LE CIark also discloses a DMOSFET which improves relatively high breakdown voltage characteristics by forming a guard ring band in a circumferential shape around a main PN junction. In this case, a depletion layer extending from the main PN junction is also made to extend toward the guard ring so that the depletion layer can be formed as smoothly as possible in its slope, and the field strength inside the DMOSFET can be reduced. The provision of such a guard ring is effective in ensuring that the DMOSFET has a high breakdown voltage, while the source electrode is electrically connected to the guard ring and the capacitance between the guard ring and the drain is the drain-to-source capacitance (C _DS ). There is a problem that the output capacity should be increased.

(Summary of invention)

Therefore, the main object of the present invention is to solve the above problems, to transmit the output signal without any distortion, to lower the output capacity (C _OSS ) without increasing the ON-resistance, the high frequency signal leakage in the OFF state of the device It is to provide a low-output, double-diffusion field effect transistor (DMOSFET) that can be prevented.

According to the present invention, the object is that the drain electrode connected to the drain terminal is provided on one of two main surfaces of the semiconductor substrate of the first conductive type, and the well regions of the second conductive type. And source regions of the first conductivity type are formed by the double diffusion means in the remaining main surfaces of the semiconductor substrate, and the channel regions are located between the first conductivity type band and the source region of the semiconductor substrate within the surface of the well region. The electrode connected to the gate terminal is provided with an insulating film disposed therebetween on the channel region, the source electrode connected to the source terminal with respect to the guard ring region of the second conductivity type, and is provided out of the well region including the channel region. Low-power-type, characterized in that a guard ring of the second conductivity type is provided and the gate electrode is connected to the gate terminal at least via the capacitive component means. 2 is realized by the spreading of the field effect transistor (DMOSFET)

Other objects and advantages of the present invention will become apparent as the description of the present invention proceeds in detail with reference to the preferred embodiments shown in the accompanying drawings.

(Example)

In general, for example, when a DMOSFET is adopted as a power semiconductor device in a solid state relay, the gate (G) and drain (D) and the capacitor (C _GD ) or the drain (D) and the source (S) may be used to lower the output capacitance (C _OSS ). It is desired to lower the capacity (C _DS ) between. Therefore, reducing the surface area of the DMOSFET can lower the output capacitance (C _OSS ), but it is undesirable to increase the ON-resistance. According to the present invention, the low output capacitance of the DMOSFET can be realized by means for connecting at least the capacitive component means to the gate electrode connected to the gate terminal without increasing the ON resistance.

Referring to the drawings, a low output capacitance DMOSFET according to the present invention will be described with reference to FIG. 1, where the first conductive type (here n-type semiconductor band 2) and the second conductive type (here channel region) are shown in FIG.

P-type semiconductor region 3 formed in one surface of n-type semiconductor zone 2 to form (CH), and a first conductive type (here p-type semiconductor region (to form a source region) An embodiment of a DMOSFET having a semiconductor substrate 1 composed of n-type semiconductor regions formed in the surface region of 3) is shown.

Between the n-type semiconductor zone 2 of the semiconductor substrate 1 and the n-type semiconductor region 4 for forming the source region, over the channel region CH, 3 of the p-type semiconductor region, the insulating film 7 and Together there is provided a gate electrode 6 located therebetween. In this case, not only the n-type semiconductor region 4 for forming the source region but also the p-type semiconductor region 3 for forming the channel are formed by the double diffusion means performed as the gate electrode 6 made as a mask. Is formed. Further, on the outer side of the p-type semiconductor region 3, a p-type semiconductor region 8 was formed for the purpose of improving breakdown voltage characteristics. In addition, a source electrode 10 is provided on one surface of the n-type semiconductor substrate 2 of the semiconductor substrate 1, while a drain electrode 11 is provided on another surface of the semiconductor zone 2. The gate terminal G, the source terminal S, and the drain terminal D are connected to these gate electrodes 6, the source electrode 10, and the drain electrode 11, respectively. When connecting the gate electrodes 6 to the gate terminal G, the output capacitance can be lowered by reversely connecting the diodes 13 and 13a in parallel therebetween. In more detail with reference to the equivalent circuit of FIG. 2, the output capacitance C _OSS1 in this circuit is represented by the following equation.

C _OSS1 = C _DS + C _P + {C _GD ㆍ (C _GS + C _D )} / {C _GD + C _GS + C _D }

Since the capacitance C _D of the diodes 13 and 13a is extremely small,

C _OSS1 C _DS + C _P + (C _GD ㆍ C _GS ) / (C _GD + C _GS )

Will be,

Here, the output capacitance (C _OSS ) of the conventional DMOSFET is

C _OSS = C _DS + C _P + C _GD

That car is

C _OSS -C _OSS1 = C _GD {1-C _GS / (C _GD + C _GS )}> 0

It can be seen that the output capacity is smaller than that of the conventional DMOSFET.

3 shows another embodiment of the DMOSFET according to the present invention, wherein the same components as in the embodiment of FIG. 1 are denoted by the same member numbers as in FIG. On the other hand, in this embodiment, the contact electrode 9 is formed on the p-type semiconductor region 8 formed outside the p-type channel-forming semiconductor region 3 in order to improve the breakdown voltage characteristic, so that the source electrode 10 And a reverse parallel connection of another diode (14, 14a) is connected across the contact electrode (9) and the source electrode (10).

In addition, referring to the equivalent circuit of FIG. 4, the operation for lowering the output capacitance in this embodiment will be described in more detail. In the equivalent circuit, the output capacitance C _OSS2 is

C _OSS2 = C _DS + (C _D · C _P ) / (C _D + C _P ) + [{C _GD · (C _CS + C _D )} / {C _GD + C _GS + C _D }

Since the output capacity of the diode connections 13, 13a and 14, 14a is extremely small,

C _OSS2 C _GS + (C _{GDC GS} ) / (C _GD + C _GS )

Compared with the output capacity (C _OSS ) of the conventional DMOSFET

C _OSS -C _OSS2 = C _P + C _GD [1- {C _GS / (C _GD + C _GS )}]> 0

It can be seen that the output capacity of this embodiment is smaller than that of the conventional DMOSFET.

In the DMOSFETs of FIGS. 1 and 3, the antiparallel connection of diodes 13 and 13a or diodes 13, 13a and 14, 14a acts as a capacitive component and is output in series with the parasitic capacitance component of the DMOSFET. The capacity will be reduced. It is effective to use a diode of anti-parallel connection as a capacitive component here. That is, it is located between the gate electrodes and their common gate terminals to provide the gate electrode with a voltage applied to the gate terminal that is higher than the threshold voltage of the DMOSFET and to obtain the function of turning the DMOSFET ON. A capacitive component means is required. Likewise, by maintaining the brake voltage, the capacitive component means located between the contact electrode and the source electrode is also required for the source terminal to provide a voltage at which the voltage applied to the source terminal is higher than the predetermined voltage. Considering these requirements, by using the diode's normal direction as a capacitive component, the diode moved in the normal direction acts as a condenser, for example, up to about 0.6V or more, but at higher voltages, it acts as a conductor only to achieve the desired operation. Can be. In the antiparallel connection of the diodes, the discharge and pull of the desired charge is carried out through one of the diodes.

In other words, the gate electrode is usually formed of adopted polysilicon. Therefore, the foregoing diode can be provided to the semiconductor substrate for the portion other than the polysilicon film, which is the gate electrode used in a simple manner. Particularly when the diode is formed of the adopted polysilicon, the diode has an extremely small junction area and consequently the diode capacitance C _D becomes extremely small, so that polysilicon is adopted in the present invention to find its usefulness.

FIG. 5 shows a solid state relay (SSR) in which the DMOSFET of FIG. 3 is adopted as a power semiconductor device, from which the light emitting element 21 and the light emitting element 21 generate an optical signal in accordance with the received input signal. The photovoltaic device array which generates photovoltaic power upon receiving the emitted optical signal, and the power DMOSFETs 23 and 23a and the power DMOSFET 23 which are driven from the first impedance state to the second impedance state when the photovoltaic power is applied to the gate terminal. And a control circuit 24 constituting the release means for the gate charge. In this case, the power DMOSFETs 23, 23a are connected in series with their sources S made in common so as to be a voltage blocking arrangement on both sides. Therefore, in the solid state relay SSR of FIG. 5, by using the DMOSFET according to the present invention, the output capacity of the relay SSR can be effectively lowered and the high frequency cut-off capability can be improved, and the relay can control the high frequency signal. Can be effectively improved.

In general, it will be well understood from the foregoing description that the DMOSFET according to the present invention effectively allows reduction of output capacity without causing disadvantages such as distortion in breakdown voltage characteristics, increase in ON resistance, and the like.

While the invention has been well described by way of example, it should be understood that the invention is not limited to these embodiments but includes all modifications, modifications and equivalent arrangements that are possible within the scope of the appended claims.

Claims (10)

A first conductive semiconductor substrate 1 having two main surfaces; A drain electrode 11 provided on one of the main surfaces of the semiconductor substrate 1 and connected to the drain terminal D; Source regions 4 of the first conductivity type and well regions 3 of the second conductivity type each formed by double diffusion on the other one of the main surfaces of the semiconductor substrate 1; A channel region (CH) defined in the surface region of the well region (3) to be between the first conductive semiconductor band (2) of the semiconductor substrate (1) and the source region (4); A gate electrode 6 provided over the channel region CH with an insulating film 7 therebetween; And the second conductive type guarding region 8 located in the first conductive semiconductor band 2 so as to be outside the well region 3 including the channel region CH. The region 4 is provided with a source electrode 10 connected thereon to the source terminal S, the gate electrode 6 having at least the capacitive component means. A low output-capacitance double diffusion type field effect transistor, which is connected to the gate terminal G through (13). A transistor according to claim 1, characterized in that the guard ring region (8) is connected to the source electrode (S) via another capacitive component means (14). The transistor according to claim 1, wherein said capacitive component means (13) comprises a diode. 4. Transistor according to claim 3, characterized in that the diodes are provided in pairs (13, 13a) interconnected in an anti-parallel relationship. 4. Transistor according to claim 3, characterized in that the diode (13) is formed of polysilicon. 3. Transistor according to claim 2, wherein each of said capacitive component means (13) and another of said capacitive component means (14) comprise a diode. 7. Transistor according to claim 6, wherein the diodes of the respective capacitive component means are provided in pairs (13, 13a; 14, 14a) interconnected in an anti-parallel relationship. 7. Transistor according to claim 6, wherein the diode (l3, 14) is formed of polysilicon. A light emitting means 21 for generating an optical signal upon receiving an input signal, a photovoltaic means for generating photovoltaic power when receiving the optical signal emitted from the light emitting means 21, and the photovoltaic means 22 A power DMOSFET 23 connected to and having a gate terminal G, and means for driving the power DMOSFET from a first impedance state to a second impedance state according to the photovoltaic force applied to the gate terminal G. ); The power DMOSFET 23 is a first conductive semiconductor substrate 1 having two main surfaces, a drain electrode provided on one surface of the main surface of the semiconductor substrate 1 and connected to the drain terminal D. (11), a well region 3 of the second conductivity type and a source region 4 of the first conductivity type, respectively formed by double diffusion on the remaining surface of the main surface of the semiconductor substrate 1, In the surface region of the well region 3, the channel region CH and the insulating layer 7 defined between the first conductive semiconductor band 2 of the semiconductor substrate 1 and the source region 4 are interposed therebetween. A gate electrode 6 respectively provided over the channel region, and the third electrode positioned to be outside the well region 3 including the channel region CH in the first conductive semiconductor band 2. A two-conducting guard ring region 8 is provided, and the source region 4 is provided with a source electrode 10 connected thereon to a source terminal S, and the gate electrode 6 has a first capacitance. It is connected to the gate terminal G through the component means 13, and the guard ring region 8 has a second capacitive component means 14. Solid state relay, characterized in that connected to the source region through. 10. A relay as claimed in claim 9, wherein the plurality of power DMOSFETs (23, 23a) are provided to be common when connected in series with the source terminal (S).