CN110739345A - Self-biased split gate trench type power MOSFET device - Google Patents

Self-biased split gate trench type power MOSFET device Download PDF

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Publication number
CN110739345A
CN110739345A CN201910813746.7A CN201910813746A CN110739345A CN 110739345 A CN110739345 A CN 110739345A CN 201910813746 A CN201910813746 A CN 201910813746A CN 110739345 A CN110739345 A CN 110739345A
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conductive type
gate
region
split
conductivity type
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CN110739345B (en
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孔谋夫
陈罕之
刘聪
陈星弼
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LESHAN SHARE ELECTRONIC CO Ltd
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Abstract

The invention relates to the field of power semiconductor devices, in particular to a split-gate trench type MOS device, specifically a self-biased split-gate trench type power MOSFET device; compared with the traditional split gate groove type MOS device, the self-bias voltage structure is introduced on the basis of the traditional split gate groove type MOS device, and the self-bias voltage is provided for the split gate by utilizing the gate control signal. In this specification, the implementation of the split gate self-bias voltage is divided into two ways, namely, adding an external circuit and adding a structure capable of providing a bias voltage, in which the bias voltage of the former is derived from a gate driving circuit, and the latter has an advantage of reducing driving power consumption compared with the former.

Description

Self-biased split gate trench type power MOSFET device
Technical Field
The invention relates to the field of power semiconductor devices, in particular to a split-gate trench type MOS device, and specifically relates to a self-biased split-gate trench type power MOSFET device.
Background
The introduction of Split gate (Split gate) enables the capacitance C between the gate and the drain of the trench type power MOS deviceGDThe switching loss is obviously reduced, the working frequency of the device is effectively increased, but in the structure of the traditional split-gate trench type MOS device, a split gate is usually connected with a source electrode S, and increases the specific on-resistance of the device to a certain extent, as shown in fig. 1. in order to reduce the specific on-resistance of the split-gate trench type MOS device, high potentials relative to the source electrode S can be applied to the split gate SG in the design process of the split-gate trench type MOS device, so that an accumulation layer is formed on the side wall of an oxide layer of the split gate, and the specific on-resistance of the device is reduced, as shown in fig. 2, but the device is changed from the original three ends into four-end devices, which is not favorable for compatibility with the conventional device, and simultaneously provides bias for the split gate SG, needs additional power supply, increases the complexity and cost of application.
Based on this, the present invention provides a self-biased split-gate trench-type power MOSFET device.
Disclosure of Invention
The invention aims to provide a self-bias split gate trench type power MOSFET device which is used for generating stable self-bias voltage through an external circuit structure by utilizing a control signal of a gate; the invention adopts a self-biasing method to generate the split gate SG bias voltage, which not only can improve the frequency characteristic and the switching loss of the device, but also can introduce the accumulation layer for conduction, increase the conduction capability and reduce the specific on-resistance of the device.
In order to achieve the purpose, the invention adopts the technical scheme that:
a self-biased split-gate trench-type power MOSFET device, comprising:
an th conductive type substrate 1, a drain 7 located below the th conductive type substrate 1, a th conductive type drift region 2 located above the th conductive type substrate 1, a second conductive type base region 3 located above the th conductive type drift region 2, a second conductive type heavily doped region 4 and a th conductive type heavily doped region 5 formed in the second conductive type base region 3 and adjacent to each other, a source 10 covering the second conductive type heavily doped region 4 and the th conductive type heavily doped region 5, an oxidation region 6 adjacent to the th conductive type drift region 2, the second conductive type heavily doped base region 3 and the th conductive type heavily doped region 5, a control gate 9 and a split gate 8 located in the oxidation region 6;
the device is characterized by further comprising a capacitor C1 and a diode D1, wherein the source 10 is connected with the split gate 8 after being connected with the capacitor C1, and the control gate 9 is connected with the split gate 8 after being connected with the diode D1.
A self-biased split-gate trench-type power MOSFET device, comprising:
an th conductive type substrate 1, a drain 7 located below the th conductive type substrate 1, a th conductive type drift region 2 located above the 0 th conductive type substrate 1, a second conductive type base region 3 located above the th conductive type drift region 2, a second conductive type heavily doped region 4 formed in the second conductive type base region 3, a source 10 bridged over the th conductive type drift region 2 and the th conductive type heavily doped region 5 of the second conductive type base region 3, wherein the th conductive type heavily doped region 5 is adjacent to the second conductive type heavily doped region 4 and covers the second conductive type heavily doped region 4 and the th conductive type heavily doped region 5, an oxidation region 6 adjacent to both the th conductive type drift region 2 and the th conductive type heavily doped region 5, a control gate 9 located in the oxidation region 6 and a split gate 8;
the device is characterized by further comprising a capacitor C1 and a diode D1, wherein the source 10 is connected with the split gate 8 after being connected with the capacitor C1, and the control gate 9 is connected with the split gate 8 after being connected with the diode D1.
, in the two self-biased split-gate trench power MOSFET devices, when the conductivity type is N-type and the second conductivity type is P-type, the cathode of the capacitor C1 is connected to the source 10, the anode of the diode D1 is connected to the control gate 9, the split gate 8 is connected to the anode of the capacitor C1 and the cathode of the diode D1, when the conductivity type is P-type and the second conductivity type is N-type, the anode of the capacitor C1 is connected to the source 10, the cathode of the diode D1 is connected to the control gate 9, and the split gate 8 is connected to the cathode of the capacitor C1 and the anode of the diode D1.
, in the two self-biased split-gate trench power MOSFET devices, the split gate 8 is a rectangular split gate, an unfilled rectangular split gate or a trapezoidal split gate.
Further , in the two self-biased split-gate trench power MOSFET devices, the device further includes a second conductive type doped region 11 located in the conductive type drift region 2 and contacting the second conductive type base region 3 but not contacting the oxide region 6.
A device for providing bias voltage for a split gate comprises a conductivity type substrate 12, a drain 18 located below the conductivity type substrate 12, a conductivity type drift region 13 located above the conductivity type substrate 12, a second conductivity type base region 14 and a second conductivity type lightly doped region 15 which are adjacent and located above the conductivity type drift region 13, a second conductivity type heavily doped region 15 and a conductivity type heavily doped region 16 which are adjacent and formed in the second conductivity type base region 14, a source 20 covering the second conductivity type heavily doped region 15 and the conductivity type heavily doped region 16, a conductivity type heavily doped region 17 formed in the second conductivity type lightly doped region 15, and an electrode 19 covering the conductivity type heavily doped region 17, wherein the source 20 is connected with a capacitor C1 and then connected with the split gate, and the electrode 19 is connected with a diode D1 and then connected with the split gate.
, in the device, when the conductivity type is N-type and the second conductivity type is P-type, the source 20 is connected to the cathode of the capacitor C1, the electrode 19 is connected to the anode of the diode D1, the cathode of the diode D1 and the anode of the capacitor C1 are connected to the split gate, and when the conductivity type is P-type and the second conductivity type is N-type, the source 20 is connected to the anode of the capacitor C1, the electrode 19 is connected to the cathode of the diode D1, and the anode of the diode D1 and the cathode of the capacitor C1 are connected to the split gate.
, the device for providing bias voltage for the split gate further includes an oxide layer 22 covering the lightly doped region 15 of the second conductivity type, a portion of the base region 14 of the second conductivity type, and a portion of the heavily doped region 17 of the conductivity type, wherein the oxide layer 22 is isolated from the source 20 and the electrode 19, and a gate 21 is disposed above the oxide layer 22.
Compared with the prior art, the invention has the beneficial effects that:
the self-bias split-gate groove type power MOSFET device provided by the invention adopts a self-bias method to generate split-gate bias voltage, so that the frequency characteristic and the switching loss of the device can be improved, and the specific on-resistance of the device can be reduced by introducing the accumulation layer conductive channel.
Drawings
Fig. 1 is a schematic diagram of a conventional split-gate deep trench MOSFET structure.
Fig. 2 is a schematic structural diagram of a self-biased split-gate trench-type power MOS device.
3-8 are schematic structural diagrams of 6 different configurations of self-biased split-gate trench MOS devices; fig. 3 is a split gate inversion layer MOSFET with a self-bias structure, fig. 4 is a truncated rectangular split gate inversion layer MOSFET with a self-bias structure, fig. 5 is a trapezoidal split gate inversion layer MOSFET with a self-bias structure, fig. 6 is a split gate accumulation layer MOSFET with a self-bias structure, fig. 7 is a truncated rectangular split gate accumulation layer MOSFET with a self-bias structure, and fig. 8 is a trapezoidal split gate accumulation layer MOSFET with a self-bias structure.
Fig. 9 is a MOSFET of a self-biased split-gate inversion layer structure incorporating a super junction structure.
Figure 10 is a schematic diagram of a device structure for providing embodiments of bias voltages for split gates.
Figure 11 is a schematic diagram of a device structure for providing embodiments of bias voltages for split gates.
Detailed Description
The invention is further illustrated in detail in connection with the figures and examples.
Example 1
The present embodiment provides self-biased split-gate trench MOSFET devices, as shown in fig. 3, including:
an th conductive type substrate 1, a drain 7 located below the th conductive type substrate 1, a th conductive type drift region 2 located above the th conductive type substrate 1, a second conductive type base region 3 located above the th conductive type drift region 2, a second conductive type heavily doped region 4 and a th conductive type heavily doped region 5 which are adjacent to each other and a source 10 covered above the second conductive type heavily doped region 4 and the th conductive type heavily doped region 5 are formed in the second conductive type base region 3;
an oxide region 6 adjacent to the th conductive type drift region 2, the second conductive type base region 3 and the th conductive type heavily doped region 5, a control gate 9 and a split gate 8 in the oxide region 6;
the negative plate of the capacitor C1 is connected with the source electrode 10, the positive electrode of the diode D1 is connected with the control grid 9, and the split grid 8 is connected with the positive plate of the capacitor C1 and the negative electrode of the diode D1.
In this embodiment, the th conductive type is an N-type, the second conductive type is a P-type, and the split gate 8 is a rectangular split gate, it should be noted that the split gate 8 may also be a rectangular split gate with a broken corner, as shown in fig. 4, and the split gate 8 may also be a trapezoidal split gate, as shown in fig. 5.
Example 2
The present embodiment provides self-biased split-gate trench MOSFET devices, as shown in fig. 6, including:
an th conductive type substrate 1, a drain 7 located below the th conductive type substrate 1, a th conductive type drift region 2 located above the th conductive type substrate 1, a second conductive type base region 3 located above the th conductive type drift region 2, a second conductive type heavily doped region 4 formed in the second conductive type base region 3, a th conductive type heavily doped region 5 bridging the th conductive type drift region 2 and the second conductive type base region 3, wherein the th conductive type heavily doped region 5 is adjacent to the second conductive type heavily doped region 4, and a source 10 covering the second conductive type heavily doped region 4 and the th conductive type heavily doped region 5;
an oxide region 6 adjacent to both the th conductive type drift region 2 and the th conductive type heavily doped region 5, a control gate 9 and a split gate 8 in the oxide region 6;
the negative plate of the capacitor C1 is connected with the source electrode 10, the positive electrode of the diode D1 is connected with the control grid 9, and the split grid 8 is connected with the positive plate of the capacitor C1 and the negative electrode of the diode D1.
In this embodiment, the th conductive type is an N-type, the second conductive type is a P-type, and the split gate 8 is a rectangular split gate, it should be noted that the split gate 8 may also be a rectangular split gate with a broken corner, as shown in fig. 7, and the split gate 8 may also be a trapezoidal split gate, as shown in fig. 8.
In terms of operation principle, in the device structure shown in fig. 3 to 8 (embodiment 1 and embodiment 2), since the power device normally operates in the on-off state, when the control signal of the gate G is at a high level with respect to the source S, the diode D1 is turned on, the control signal charges the capacitor C1 through the diode D1, the potential at the right end (SG end) of the capacitor C1 is higher than the source potential, when the control signal of the gate G is at a low level (0V or negative potential) with respect to the source S, the diode D1 is reversely biased, the charge at both ends of the capacitor is not discharged, and when the control signal of the gate G is at a high level with respect to the source S at the time , the capacitor continues to be charged, and in this way, the capacitor is charged after several cycles by the voltage V at both ends of the capacitorSG＝VGS-VD1(wherein VSGNamely the potential of the split gate electrode and the voltage at two ends of the capacitor; vGSFor controlling the high level potential, V, in the signal for the gate sourceD1Conduction voltage drop for a diode); so that the voltage V across the capacitorSGMay be the self-bias voltage of the split gate SG; subsequently, the charge on the capacitor C1 is dissipated very little during the switching of the device each cycle, but is replenished each cycle, so that the voltage V across the capacitor is increasedSGThe micro-fluctuation exists, but the larger the value of the capacitor C1 is, the smaller the fluctuation is, so a designer can select whether to connect the capacitor C1 externally or integrate the capacitor C1 into the chip according to specific conditions, certainly, the diode D1 worth mentioning can be completely integrated into the chip because only a small chip area is occupied (certainly, the external connection can also be selected);
for the inversion layer conduction channel adopted by the device in fig. 3-5 (embodiment 1), when the control signal of the gate G is at a high level relative to the source S, an inversion layer conduction channel is formed on the side wall of the p-type region 3 close to the oxide layer 6, and after the self-bias voltage is obtained on the split gate based on the above principle, a large amount of accumulation layer electrons are generated on the side of the conductive type doped region 2 close to the oxide layer 6, so that the current capability of the device is increased, and the specific on-resistance of the device is reduced, for the accumulation layer conduction channel adopted by the device in fig. 6-8 (embodiment 2), when the control signal of the gate G is at a high level relative to the source S, and after the self-bias voltage is obtained on the split gate based on the above principle, the accumulation layer conduction channel is generated in the narrow and long region of the conductive type doped region 2 close to the side of the oxide layer 6, and compared with the structure shown in fig. 3-5, because the mobility of the accumulation layer electrons is higher than that of the inversion layer channel, the inversion layer conduction channel is higher, so that the on-resistance of the device is reduced by the step.
Example 3
The embodiment provides self-biased split-gate trench MOSFET devices, as shown in fig. 9, which are different from embodiment 1 in that the device further includes a second conductivity type doped region 11 located in the th conductivity type drift region 2, and in contact with the second conductivity type base region 3, and not in contact with the oxide region 6, the second conductivity type doped region 11 is configured to introduce a super junction structure, and the specific on-state current of the device is further reduced through a charge compensation principle , so that the figure of merit of the device is improved.
Similarly, as in the devices of fig. 4 to 8, the second conductive type doped region 11 may also be disposed at the same position to reduce the specific on-resistance of the device, and will not be described herein again.
Example 4
The device for providing bias voltage for a split gate is provided, as shown in fig. 10, the device includes a conductive type substrate 12, a drain 18 located below the 0 conductive type substrate 12, a conductive type drift region 13 located above the conductive type substrate 12, a second conductive type base region 14 and a second conductive type lightly doped region 15 located adjacent to each other above the conductive type drift region 13, a second conductive type heavily doped region 15 and a conductive type heavily doped region 16 formed in the second conductive type base region 14, a source 20 covering the second conductive type heavily doped region 15 and the conductive type heavily doped region 16, a conductive type heavily doped region 17 formed in the conductive type lightly doped region 13, and an electrode 19 covering the conductive type heavily doped region 17, wherein the source 20 is connected to a cathode of a capacitor C1, the electrode 19 is connected to an anode of a diode D1, and a cathode of the diode D1 and an anode of the capacitor C1 are connected to a split gate.
In this embodiment, the th conduction type is N-type, the second conduction type is P-type, and it should be noted that when the device in this embodiment is used in connection with a self-biased split-gate trench MOSFET device, the sources of the two devices are connected and the drains are connected.
In addition, the device for providing the bias voltage for the split-gate can further comprise an oxide layer 22 covering the second conductive type lightly doped region 14, a part of the second conductive type base region 13 and a part of the th conductive type heavily doped region 17, the oxide layer 22 is isolated from the source 20 and the electrode 19, a gate 21 is arranged above the oxide layer 22, as shown in fig. 11, and when the device is connected with a self-bias split-gate trench type MOSFET device for use, the gate 21 is connected with a control gate of the self-bias split-gate trench type MOSFET device.
In this embodiment, the two device structures have similar effects to the circuit formed by the diode D1 and the capacitor C1 in fig. 3 to 8, that is, a stable bias voltage is provided for the split gate. In the structures shown in fig. 10 to 11, when the device is in a voltage-withstanding state, i.e., when the D electrode is at a high voltage relative to the S electrode, the electrode H can obtain a positive potential relative to the electrode S (the potential can be adjusted to an appropriate value by adjusting the distance between the 14P and 17N +, and the doping depth of the N1 region), so that the capacitor C1 can be charged by the forward conduction of the diode D1; when the potential of the D electrode is close to that of the S electrode, almost no potential difference exists between the electrodes H and S, and at this time, the diode D1 is turned off in the reverse direction, and the charges stored in the capacitor C1 are not lost. Similarly, over a number of cycles, the capacitor is filled with the voltage V across the capacitorSG＝VHS-VD1(wherein VSGNamely the potential of the split gate electrode and the voltage at two ends of the capacitor; vHSIs the potential difference of the H electrode with respect to the source electrode S, VD1Conduction voltage drop for a diode); so that the voltage V across the capacitorSGAnd may be a self-bias voltage of the split gate SG. Subsequently, the charge on the capacitor C1 is dissipated very little during the switching of the device each cycle, but is replenished each cycle, so that the voltage V across the capacitor is increasedSGThere will be small fluctuations, but the larger the value of the capacitor C1, the smaller this fluctuation, so the designer can choose to either externally connect or integrate the capacitor C1 into the chip, depending on the specific situation, of course, it is worth to mention that the diode D1 can be fully integrated into the chip, because it takes up very little chip area (of course, external connection can also be chosen).
In addition, in all device structures in embodiments 1 to 4 of the present invention, when the th conductive type is P-type and the second conductive type is N-type, it is only necessary to interchange the connection manner of the anode and the cathode of the diode D1 and the capacitor C1, as in embodiment 1, that is, the anode of the capacitor C1 is connected to the source 10, the cathode of the diode D1 is connected to the control gate 9, and the split gate 8 is connected to the cathode of the capacitor C1 and the anode of the diode D1.
While the above is a description of specific embodiments of the invention, any of the features disclosed in this specification may be replaced by alternative features serving equivalent or similar purposes, and all of the disclosed features or steps in any method or process may be combined in any manner, except for the mutually exclusive features and/or steps, unless expressly stated otherwise.

Claims (8)

1. A self-biased split-gate trench-type power MOSFET device, comprising:
an th conductive type substrate 1, a drain 7 located below the th conductive type substrate 1, a th conductive type drift region 2 located above the th conductive type substrate 1, a second conductive type base region 3 located above the th conductive type drift region 2, a second conductive type heavily doped region 4 and a th conductive type heavily doped region 5 formed in the second conductive type base region 3 and adjacent to each other, a source 10 covering the second conductive type heavily doped region 4 and the th conductive type heavily doped region 5, an oxidation region 6 adjacent to the th conductive type drift region 2, the second conductive type heavily doped base region 3 and the th conductive type heavily doped region 5, a control gate 9 and a split gate 8 located in the oxidation region 6;
the device is characterized by further comprising a capacitor C1 and a diode D1, wherein the source 10 is connected with the split gate 8 after being connected with the capacitor C1, and the control gate 9 is connected with the split gate 8 after being connected with the diode D1.
2. A self-biased split-gate trench-type power MOSFET device, comprising:
an th conductive type substrate 1, a drain 7 located below the th conductive type substrate 1, a th conductive type drift region 2 located above the 0 th conductive type substrate 1, a second conductive type base region 3 located above the th conductive type drift region 2, a second conductive type heavily doped region 4 formed in the second conductive type base region 3, a source 10 bridged over the th conductive type drift region 2 and the th conductive type heavily doped region 5 of the second conductive type base region 3, wherein the th conductive type heavily doped region 5 is adjacent to the second conductive type heavily doped region 4 and covers the second conductive type heavily doped region 4 and the th conductive type heavily doped region 5, an oxidation region 6 adjacent to both the th conductive type drift region 2 and the th conductive type heavily doped region 5, a control gate 9 located in the oxidation region 6 and a split gate 8;
the device is characterized by further comprising a capacitor C1 and a diode D1, wherein the source 10 is connected with the split gate 8 after being connected with the capacitor C1, and the control gate 9 is connected with the split gate 8 after being connected with the diode D1.
3. A self-biased split-gate trench power MOSFET as claimed in claim 1 or 2 wherein when the th conductivity type is N-type and the second conductivity type is P-type, the cathode of the capacitor C1 is connected to the source 10, the anode of the diode D1 is connected to the control gate 9, the split gate 8 is connected to the anode of the capacitor C1 and the cathode of the diode D1, and when the th conductivity type is P-type and the second conductivity type is N-type, the anode of the capacitor C1 is connected to the source 10, the cathode of the diode D1 is connected to the control gate 9, and the split gate 8 is connected to the cathode of the capacitor C1 and the anode of the diode D1.
4. A self-biasing split-gate trench power MOSFET device as claimed in claim 1 or 2 wherein said split gate 8 is a rectangular split gate, a truncated rectangular split gate or a trapezoidal split gate.
5. A self-biasing split-gate trench power MOSFET device as claimed in claim 1 or 2 further comprising a second conductivity type doped region 11 in the th conductivity type drift region 2 and in contact with the second conductivity type base region 3 and not in contact with the oxide region 6.
6, A device for providing bias voltage for a split gate, which comprises a conductivity type substrate 12, a drain 18 positioned below a conductivity type substrate 12, a conductivity type drift region 13 positioned above a conductivity type substrate 12, a second conductivity type base region 14 and a second conductivity type lightly doped region 15 which are adjacent and positioned above a conductivity type drift region 13, a second conductivity type heavily doped region 15 and a conductivity type heavily doped region 16 which are adjacent and formed in the second conductivity type base region 14, a source 20 covering the second conductivity type heavily doped region 15 and the conductivity type heavily doped region 16, a conductivity type heavily doped region 17 formed in the second conductivity type lightly doped region 15 and an electrode 19 covering the conductivity type heavily doped region 17, wherein the source 20 is connected with a capacitor C1 and then connected with the split gate, and the electrode 19 is connected with a diode D1 and then connected with the split gate.
7. The device for providing a bias voltage to a split gate of claim 6, wherein said source 20 is connected to the cathode of a capacitor C1, said electrode 19 is connected to the anode of a diode D1, the cathode of a diode D1, the anode of a capacitor C1 and the split gate when the th conductivity type is N-type and the second conductivity type is P-type, and said source 20 is connected to the anode of a capacitor C1, said electrode 19 is connected to the cathode of a diode D1, the anode of a diode D1 and the cathode of a capacitor C1 are connected to the split gate when the th conductivity type is P-type and the second conductivity type is N-type.
8. The device for providing a bias voltage to a split-gate as claimed in claim 6, further comprising an oxide layer 22 overlying the lightly doped region 15 of the second conductivity type, a portion of the base region 14 of the second conductivity type, and a portion of the heavily doped region 17 of the th conductivity type, wherein the oxide layer 22 is isolated from both the source 20 and the electrode 19, and a gate 21 is disposed over the oxide layer 22.
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