JPH01260842A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To decrease the capacitance value of a parasitic capacitor of a signal wiring, by providing a p-n junction in a semiconductor substrate beneath the signal wiring. CONSTITUTION:A p-type island 5 is provided in the surface region of an n-type semiconductor substrate 1 beneath a signal wiring 3 through an insulating film 2. The p-type island 5 incorporates p-type low-concentration impurities. A p-n junction is provided with the island 5 and n-type silicon substrate 1. In this constitution, a parasitic capacitor C1 between the signal wiring 3 and the p-type island 5 is connected in series with a capacitor C2 formed with the p-n junction between the p-type island 5 and the n-type semiconductor substrate 1. The capacitor C2 is a junction capacitor which is formed with a depletion region at the p-n junction part. The value of the junction capacitance depends on a junction area 52 and a thickness d2 of the depletion layer. Since the p-n junction capacitor C2 is connected with the parasitic capacitor C1 in series, a capacitance C of the signal wiring 3 becomes the synthesized capacitance of the capacitors C1 and C2. Since the capacitance value C of the signal wiring 3 is decreased, the speed of an electric signal which is transmitted through the signal wiring 3 becomes high, and high-speed semiconductor memories and the like can be sufficiently handled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit in which the parasitic capacitance of signal wiring is reduced.

[Conventional technology]

FIG. 9(a) is a sectional view showing a signal wiring section in a conventional semiconductor integrated circuit, and FIG. 9(b) is an equivalent circuit diagram thereof.

In the figure, 1 is a silicon substrate exhibiting n-type conductivity, and an integrated circuit is formed on this silicon substrate 1. The signal wiring 3 is formed of an aluminum wiring layer on one main surface of the silicon substrate 1 with the silicon oxide film 2 interposed therebetween. In order to protect the signal wiring 3, a passivation PA4 made of a nitride film is formed to cover the signal wiring 3. In addition,
The n-type silicon substrate 1 is connected to a power supply Vco (not shown).

In a semiconductor integrated circuit in which the signal wiring 3 as shown in FIG. 9(a) is formed, the silicon oxide film 2 between the signal wiring 3 and the silicon substrate 1 is ) A parasitic capacitor C1 having a capacitance value expressed by the following equation is formed.

SL: Area of the signal wiring 3 dl: Thickness of the silicon oxide film 2 between the signal wiring 3 and the silicon substrate 1 C0: Vacuum relative dielectric constant ε ° Relative dielectric constant V of the silicon oxide film 2 [What the invention seeks to solve] Issue] Conventional semiconductor integrated circuits are configured as described above.
The signal wiring is a parasitic capacitor C with a capacitance value shown in equation (1).
1.

If this capacitance value is large, a problem arises in that the speed of electrical signals transmitted through the signal wiring becomes slow. This problem becomes more serious as the performance (switching characteristics) of active elements such as field-effect transistors used internally improves as semiconductor memories become more highly integrated. There was a problem that the delay time of memory etc. was determined.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor integrated circuit in which the parasitic capacitance of signal wiring is reduced.

[Means for Solving the Problems] A semiconductor integrated circuit according to the present invention includes a signal wiring formed on one main surface of a semiconductor substrate via an insulating film, and a region of one main surface of the semiconductor substrate below the signal wiring. A pn junction is provided in the semiconductor substrate, and a region on the one principal surface side of the semiconductor substrate where the pn junction is formed is placed in a floating state, or a resistor having a high resistance value is provided so as to apply a reverse bias to the pn junction. The voltage is set.

(Function) Since the pn junction in this invention is provided under the insulating film under the signal wiring, the capacitance due to the pn junction is connected in series with the parasitic capacitance formed through the insulating film.

〔Example〕

FIG. 1(a) is a sectional view showing a signal wiring section of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 1(b) is an equivalent circuit diagram thereof. As shown in FIG. 1(a), unlike the conventional method, a p-type island 5 is provided in the surface region of the n-type semiconductor substrate 1 under the signal wiring 3 via an insulator 1142. p
The type island 5 contains a p-type impurity at a low concentration and forms a pn junction with the n-type silicon substrate 1.

With this configuration, as shown in FIG. 1(b), the parasitic capacitor C between the signal wiring 3 and the p-type island 5 is reduced.
, a capacitor C2 formed by a pn junction between the p-type island 5 and the n-type semiconductor substrate 1 is connected in series.

Capacitor C2 is a junction capacitance formed by a depletion layer at the pn junction portion. This junction capacitance value depends on the junction area S2 and the thickness d2 of the depletion layer, and is expressed by the following equation (2).

ε゛Relative dielectric constant of silicon r2゜ Further, the thickness d2 of the depletion layer is expressed by the following equation (3).

...(3) q: Charge distance N: N-type impurity concentration N: N-type impurity concentration φ: Built-in potential of pn junction ■R: Reverse bias voltage Therefore, the capacitance value of capacitor C2 is expressed by the following equation (4). It will be done.

...(4) Capacitor C2 due to this pn junction is parasitic capacitor C
1 in series, the capacitance C of the signal line 3 is expressed by the following equation (5), which is a composite expression of capacitors C and C2.

C1+02 As a result, the capacitance value C of the signal line 3 is reduced, and the speed of the electrical signal transmitted through the signal line 113 becomes faster, making it possible to sufficiently cope with high-speed operation semiconductor memories and the like.

FIG. 2(a) is a sectional view showing a signal wiring section of a semiconductor integrated circuit according to another embodiment of the present invention, and FIG. 2(b) is an equivalent circuit diagram thereof. As shown in FIG. 2(a), an n-type diffusion layer 6 is further formed within the p-type island 5 under the signal wiring 3 with an insulating film 2 interposed therebetween.

With this configuration, as shown in FIG. In addition to the junction capacitor C2, a pn junction capacitor C3 formed by the n-type diffusion layer 6 and the n-type island 5 is connected in series.
Compared to the embodiment shown in (b), the capacitance value of the signal wiring 3 can be further suppressed.

FIGS. 3(a) and 3(b) are equivalent circuit diagrams showing other embodiments of the present invention. As shown in (a) of the same figure, p
A region of the n-junction capacitor C2 on one main surface side of the n-type silicon substrate 1 (n-type island 5 in FIG. 1(a)) is grounded via a resistor R1 having a high resistance value. For this reason,
A reverse bias V (=■o.) is applied to the capacitor C2, and from equation (4), the capacitance ffi value of the capacitor C2 is φ8/(φ8+■R )
decreases by the ratio of Also, the resistance value of resistor R1 is changed to the value of capacitor C.
By making C□ sufficiently larger than the impedance of 2 (m:f is the frequency of the input signal), current can be prevented from flowing through the resistor R1. In addition, FIG. 3(b) has an impedance set sufficiently larger than the impedance of the capacitor C2 instead of the resistor R1, and the gate is supplied with the power supply ■cc.
An example using a channel transistor NT1 is shown.

With this configuration, it is possible to further reduce the volume value of the signal wiring 3 by reducing the capacitance value of the pacitor C2 compared to the embodiments shown in FIGS. 1(a) and 1(b). can.

FIGS. 4(a) and 4(b) are equivalent circuit diagrams showing other embodiments of the present invention. As shown in (a) of the same figure, p
A region on one main surface side of capacitor C2 (second
The n-type island 5) in FIG. 2(a) is grounded via a high-resistance resistor R2, and the region on one main surface side of the capacitor C3 (n-type diffusion layer 6 in FIG. 2(a)) formed by a pn junction is It is connected to the power supply Vcc via a resistor R3 having a high resistance value. Therefore, the capacitors C2 and c3 have a reverse bias vR, respectively.
(-■..) is given, and the capacitance values of the capacitors C2 and C3 decrease as in the embodiment shown in FIGS. 3(a) and (1). In addition, in FIG. 4(b), the power supply V is connected to the gate instead of the resistors R2 and R3. 0 is applied to the high impedance n-channel transistor NT2. An example using a high impedance p-channel transistor PTI whose gate is grounded is shown.

With this configuration, compared to the embodiments shown in FIGS. 2(a) and 2(b), the capacitance values of the capacitors C2 and C3 are reduced, thereby further reducing the capacitance value due to the signal wiring 3. be able to.

In these examples, the signal wiring 3 was formed on the n-type silicon substrate 1 via the silicon oxide film 2, but as shown in FIGS. 5 to 8, the signal wiring 3 was formed on the p-type silicon substrate. The present invention can also be applied to the case where signal wiring is formed via a silicon oxide film. 5 to 8, 11 is a p-type semiconductor substrate, 12 is a silicon oxide film, 13 is a signal wiring, 14 is a passivation film, 1
5 is an n-type island, 16 is a p-type diffusion layer, C11 is a parasitic capacitor via the silicon oxide film 12, C
12 is a pn of the p-type semiconductor substrate 11 and the n-type island 15;
A capacitor formed by a junction, C13 is a capacitor formed by a pn junction between the n-type island 15 and the n-type diffusion layer 16, and a resistor R1
1 to R13 are resistors with high resistance values, PTII, PT1
2 is a high impedance n-channel transistor whose gate is grounded, and NT11 has its gate connected to the power supply V. A high impedance n-channel transistor connected to zero.

In addition, in the above embodiments, aluminum was used as an example of the signal wiring material, but the material is not limited to polysilicon, polysilicon,
A high melting point metal material such as molybdenum side may also be used.

〔Effect of the invention〕

As described above, according to the present invention, since a pn junction is provided in the semiconductor substrate under the signal wiring, it is possible to reduce the capacitance value of the parasitic capacitance in the signal wiring.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are cross-sectional views showing a signal wiring portion of a semiconductor integrated circuit according to an embodiment of the present invention. Equivalent circuit diagrams, FIGS. 2(a) and 2(b) are cross-sectional views showing the signal wiring portion of a semiconductor integrated circuit according to another embodiment of the present invention. FIGS. 3(a) and 3(b) are equivalent circuit diagrams. ) is an equivalent circuit diagram showing a signal wiring section of a semiconductor integrated circuit according to another embodiment of the present invention, and FIGS. 4(a) and 4(b) are signal wiring diagrams of a semiconductor integrated circuit according to another embodiment of the present invention. FIGS. 5(a) and 5(b) are cross-sectional views showing the signal wiring portion of a semiconductor integrated circuit according to another embodiment of the present invention. FIG. , (b) is a sectional view 9 equivalent circuit diagram showing the signal wiring section of a semiconductor integrated circuit which is another embodiment of the present invention, and FIGS. 7(a) and (b) are other embodiments of the present invention. 8(a) and 8(b) are equivalent circuit diagrams showing a signal wiring section of a certain semiconductor integrated circuit, and FIG. 9 is an equivalent circuit diagram showing a signal wiring section of a semiconductor integrated circuit according to another embodiment of the present invention. (a) and (b) are sectional views 2 and 2 equivalent circuit diagrams each showing a signal wiring section of a conventional semiconductor integrated circuit. In the figure, 1 is an n-type silicon substrate, 2 is a silicon oxide film, 3 is a signal wiring, 5 is a p-type island, 6 is an n-type diffusion layer, R1-R3 are high resistance resistors, NT1. NT2 is a high impedance n-channel transistor, and PTl is a high impedance n-channel transistor. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a semiconductor integrated circuit in which signal wiring is formed on one main surface of a semiconductor substrate via an insulating film, a pn junction is provided in the semiconductor substrate under the signal wiring, and a pn junction is provided in the semiconductor substrate on the one main surface of the semiconductor substrate. A semiconductor integrated circuit characterized in that a region forming the pn junction is placed in a floating state, or a voltage is set via a resistor having a high resistance value so that a reverse bias is applied to the pn junction.