JPS60136249A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60136249A JPS60136249A JP58243533A JP24353383A JPS60136249A JP S60136249 A JPS60136249 A JP S60136249A JP 58243533 A JP58243533 A JP 58243533A JP 24353383 A JP24353383 A JP 24353383A JP S60136249 A JPS60136249 A JP S60136249A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- potential
- collector
- vertical
- vertical transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000003071 parasitic effect Effects 0.000 abstract description 20
- 230000003321 amplification Effects 0.000 abstract description 8
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 4
- 230000002411 adverse Effects 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000002542 deteriorative effect Effects 0.000 description 2
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0825—Combination of vertical direct transistors of the same conductivity type having different characteristics,(e.g. Darlington transistors)
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は高周波特性の向上を図った半導体装置に関する
。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device with improved high frequency characteristics.
バイポーラトランジスタにあっては、電子と正孔の易動
度の大小等によシ、一般に同一寸法の素子にあってはＰ
ＮＰ型のトランジスタに比して、ＮＰＮ型トランジスタ
の方が優れた高周波特性を示す。この為、ＰＮＰ型トラ
ンジスタとＮＰＮ型トランジスタが混在する回路にあっ
ては、主としてＰＮＰＮＰＮトランジスタ周波特性によ
り回路全体の高周波特性が支配される。In bipolar transistors, depending on the mobility of electrons and holes, P
NPN transistors exhibit better high frequency characteristics than NP transistors. Therefore, in a circuit in which PNP type transistors and NPN type transistors coexist, the high frequency characteristics of the entire circuit are mainly dominated by the frequency characteristics of the PNPNPN transistors.
この為、従来より専ら、高周波特性の優れたＮＰＮ型の
トランジスタのみを用いて回路を構成することが試みら
れているが、設計自由度が失われ、また回路構成が複雑
化する等の不具合があった。そこで最近では、ラテラル
ＰＮＰ型トランジスタに比して優れた高周波特性を示す
バーチカルＰＮＰ ）ランジスタを用い、その寄生容量
等による高周波特性劣化要素をできる限り避けて、ＮＰ
１’Ｊ ｌ−ランノスタと共に所望の回路を構成するこ
とが行われている。For this reason, attempts have been made to construct circuits exclusively using NPN transistors with excellent high frequency characteristics, but this has resulted in problems such as loss of design freedom and complication of circuit configuration. there were. Therefore, in recent years, vertical PNP (vertical PNP) transistors, which have superior high frequency characteristics compared to lateral PNP transistors, have been used, and by avoiding as much as possible the deterioration of high frequency characteristics due to parasitic capacitance,
1'J l-Lannostar is used to construct a desired circuit.
ところで、この種のバーチカルＰＮＰ トランジスタは
、例えば第１図に示すようにＰ型半導体基板１上にＮｕ
半導体層（Ｎ−ウェル）２を素子間分離層として形成し
、このＮ−ウェル２によって素子間分離された領域に２
層３、Ｎ層４およびＰ＋層５、耐層６、Ｐ＋層７を形成
して構成される。同、ここで上日己ｐｕｓおよび２層５
はコレクタ、ＮＩ藝４および耐層６はペース、Ｐ＋層７
はエミッタとしてそれぞれ機能する０しかして、このよ
うな構造のＰＮＰ ）ランジスタ（半導体装置）Ｋあっ
ては、通常、素子間分離用のＮ−ウェル２を回路中の正
の最大電位点に接続してその機能を働かせるようにして
いる。By the way, this type of vertical PNP transistor is constructed by forming Nu
A semiconductor layer (N-well) 2 is formed as an element isolation layer, and 2 layers are formed in a region separated between elements by this N-well 2.
It is constructed by forming a layer 3, an N layer 4, a P+ layer 5, a resistance layer 6, and a P+ layer 7. Same, here Kaminichi pus and 2 layers 5
is the collector, NI technology 4 and resistance layer 6 are the pace, P+ layer 7
However, in a PNP transistor (semiconductor device) K with such a structure, the N-well 2 for isolation between elements is usually connected to the maximum positive potential point in the circuit. I'm trying to make that function work.
この為、上記Ｎ−ウェル２とＰ型半導体基板１との間、
およびＮ−ウェル２とバーチカルトランジスタ８のコレ
クタである２層３との間にそれぞれ寄生ダイオード９，
１Ｏが形成され、その等価回路が第２図に示すようにな
る。この結果、上記各寄生ダイオード９．ＩＯが有する
静電容量成分が、前記バーチカルトランジスタ８のコレ
クタと回路の接地点との間に対する寄生容量として働き
、その高周波特性劣化の要因となっていた。Therefore, between the N-well 2 and the P-type semiconductor substrate 1,
A parasitic diode 9,
1O is formed, and its equivalent circuit is shown in FIG. As a result, each of the parasitic diodes 9. The capacitance component of the IO acts as a parasitic capacitance between the collector of the vertical transistor 8 and the ground point of the circuit, and is a factor in deteriorating its high frequency characteristics.
本発明はこのような事情を考慮してなされたもので、そ
の目的とするところは、バーチカルトランジスタの素子
間分離用として形成される逆導電性半導体層に起因する
寄生容量による悪影響を抑えて高周波特性の向」二を図
った半導体装置を提供する仁とにある。The present invention has been made in consideration of these circumstances, and its purpose is to suppress the adverse effects of parasitic capacitance caused by the reverse conductive semiconductor layer formed for isolation between elements of vertical transistors, and to improve high frequency performance. We are committed to providing semiconductor devices with improved characteristics.
本発明は一導電性半導体基板上に形成されたバーチカル
トランジスタを素子間分離する逆導電性半導体層の電位
を、上記バーチカルトランジスタのコレクタ電位と略同
電位に保つようにしたものである。In the present invention, the potential of a reverse conductive semiconductor layer that separates vertical transistors formed on a single conductive semiconductor substrate is maintained at approximately the same potential as the collector potential of the vertical transistor.
かくして本発明によれば、逆導電性半導体層の電位がバ
ーチカルトランジスタのコレクタ電位と略同電位なので
、その半導体層間に形成される寄生ダイオードにおける
電荷移動を殆んど無くすことができ、見掛上、上記寄生
ダイオードおよびそこに生じる寄生容量を無くして、そ
の高周波特性の向上を図ることが可能となる。Thus, according to the present invention, since the potential of the reverse conductive semiconductor layer is approximately the same potential as the collector potential of the vertical transistor, charge transfer in the parasitic diode formed between the semiconductor layers can be almost eliminated, and the apparent By eliminating the parasitic diode and the parasitic capacitance generated therein, it is possible to improve its high frequency characteristics.
その上、寄生ダイオードの非線形特性による歪要因も抑
えることが可能となる等の実用上多大なる効果が奏せら
れる。Furthermore, it is possible to suppress distortion factors due to the nonlinear characteristics of parasitic diodes, which provides great practical effects.
以下、図面を参照して本発明の実施例につき説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第３図は実施例装置の基本的な構成を示す等価回路で、
第４図はその具体的な構成例を示す図である。尚、従来
装置と同一部分例は同一符号を伺して示しである。FIG. 3 is an equivalent circuit showing the basic configuration of the embodiment device.
FIG. 4 is a diagram showing a specific example of the configuration. Incidentally, parts that are the same as those of the conventional device are indicated by the same reference numerals.
本装置は、基本的にはバーチカルトランジスタ８のコレ
クタ電位を入力とする増幅度が１（’０ｄＢ）の増幅器
１１を設け、その出力電圧をＮ−ウェル２に印加して、
その電位を上記コレクタ電位と略同電位に保つようにし
たものである。This device basically includes an amplifier 11 with an amplification factor of 1 ('0 dB) that receives the collector potential of the vertical transistor 8 as input, and applies its output voltage to the N-well 2.
The potential is kept at approximately the same potential as the collector potential.
この増幅器１１は、例えば前０己バーチカルトランジス
タ８を形成してなる半導体基板１上にサブストレートＰ
ＮＰトランジスタ１２を形成し、該トランジスタ１２を
エミッタ・ホロア回路として用いることによ多構成され
る。上記サブストレートＰＮＰトランジメタ１２は、そ
の基板１にＰ＋層１３を形成してコレクタとし、１だ該
基板１上に８層１４、耐層１５を形成してペースとし、
更に上記Ｎ層１４上にＶ層１６を形成し、これをエミッ
タとすること等によって形成される。そして、このトラ
ンジスタ１２のペースを前記バーチカルトランジスタ８
のコレクタに電気的接続し、またエミッタを前記Ｎ−ウ
ェル２に接続し、コレクタ・エミッタ間に所定の電圧を
印加することによシ、エミッタ・ホロア回路として機能
させる。This amplifier 11 is constructed by disposing a substrate P on a semiconductor substrate 1 on which vertical transistors 8 are formed, for example.
It is constructed by forming an NP transistor 12 and using the transistor 12 as an emitter-follower circuit. The substrate PNP transistor 12 has a P+ layer 13 formed on the substrate 1 as a collector, and 8 layers 14 and a resistive layer 15 formed on the substrate 1 as a paste,
Further, a V layer 16 is formed on the N layer 14, and this is used as an emitter. Then, the pace of this transistor 12 is set to the vertical transistor 8.
By electrically connecting the collector to the N-well 2, and connecting the emitter to the N-well 2, and applying a predetermined voltage between the collector and the emitter, it functions as an emitter-follower circuit.
かくしてこのように構成された装置によれば、増幅器１
ノの増幅度が１（ＯｄＢ）に設定された場合、Ｎ−ウェ
ル２の電位は常にバーチカルトランジスタ８のコレクタ
電位に等しくなる。この為、Ｎ−ウェル２と２層３との
間に形成される寄生ダイオード１Ｏの両端電位差は常に
Ｏ（零）となシ、見掛上、ダイオード１Ｏが在存しない
ものと等価となる。従って、ダイオード１Ｑの寄生容量
がバーチカルトランジスタ８に悪影響を及はし、その高
周波特性が劣化することがなく な る。According to the device configured in this manner, the amplifier 1
When the amplification degree of N is set to 1 (OdB), the potential of the N-well 2 is always equal to the collector potential of the vertical transistor 8. Therefore, the potential difference across the parasitic diode 1O formed between the N-well 2 and the second layer 3 is always O (zero), and is apparently equivalent to the case where the diode 1O does not exist. Therefore, the parasitic capacitance of the diode 1Q does not adversely affect the vertical transistor 8 and its high frequency characteristics are prevented from deteriorating.
また仮に、上記増幅器１１の増幅度が０．９であった場
合には、Ｎ−ウェル２の電位はバーチカルトランジスタ
８のコレクタ電位の９０％の値に保たれることになる。Furthermore, if the amplification degree of the amplifier 11 is 0.9, the potential of the N-well 2 will be maintained at 90% of the collector potential of the vertical transistor 8.
このときには、寄生ダイオードＩＯの両端電位差は、上
ｄピコレクタ電位の１０％の電位に抑えられることにな
シ、その結果、寄生ダイオード１０の見掛上の接合容量
（寄生容量）は、増幅器１１が存在しない場合に比して
、約１／１０に低減されることになる＠従って、Ｎ−ウ
ェル２の電位を、バーチカルトランジスタ８のコレクタ
電位と略同電位にするだけで、従来に比して高周波特性
の向上を図ることが可能となる。At this time, the potential difference across the parasitic diode IO is suppressed to 10% of the upper d pico collector potential, and as a result, the apparent junction capacitance (parasitic capacitance) of the parasitic diode 10 is It will be reduced to about 1/10 compared to the case where it does not exist @ Therefore, by simply making the potential of the N-well 2 approximately the same as the collector potential of the vertical transistor 8, the potential will be reduced compared to the conventional case. It becomes possible to improve high frequency characteristics.
このように、増幅器１１の増幅度をμ（〉０）に設定し
たとき、寄生ダイオード１０の容量を等測的に（１−μ
）倍に抑えることができ、上記増幅度μを１に漸近させ
ることによって、上記寄生ダイオード１Ｏによる容量成
分を、実際上無視できる程度に小さくシ、バーチカルト
ランジスタ８の高周波特性の向上を図ることが可能とな
る。In this way, when the amplification degree of the amplifier 11 is set to μ (>0), the capacitance of the parasitic diode 10 is isometrically expressed as (1 − μ
), and by bringing the amplification degree μ asymptotic to 1, the capacitance component due to the parasitic diode 1O can be reduced to a practically negligible level, and the high frequency characteristics of the vertical transistor 8 can be improved. It becomes possible.
また寄生ダイオード１Ｏの接合、容量は一般に非線形に
変化し、これが為に従来装置にあっては、バーチカルト
ランジスタ８のコレクタ電位の変化によって歪が発生し
ていた。然し乍ら、本装置によれば、上述したように接
合容量自体を打消すので、歪発生の問題が生じることが
ない。これ故、バーチカルトランジスタ８を用いて構成
される回路の歪率、ダイナミックレンジに関する特性に
関しても極めて有利である。Further, the junction and capacitance of the parasitic diode 1O generally change nonlinearly, and for this reason, in the conventional device, distortion occurs due to a change in the collector potential of the vertical transistor 8. However, according to the present device, since the junction capacitance itself is canceled as described above, the problem of distortion does not occur. Therefore, the circuit configured using the vertical transistor 8 is extremely advantageous in terms of distortion rate and dynamic range characteristics.
陶、増幅器１１の増幅度μに関しては、七の値が１以上
又は負にならない限シ、ダイオード１Ｏが常に逆バイア
ス状態に保たれるので、素子間分離について、その機能
に支障を招くことがない。Regarding the amplification degree μ of the amplifier 11, as long as the value of 7 is not greater than 1 or negative, the diode 1O is always kept in a reverse bias state, so there is no possibility of interfering with the function of the isolation between elements. do not have.
第５図（−） 、 （ｂ）は、本装置を用いて構成され
た定電流源回路の構成例をそれぞれ示すものであシ、先
の実施例装置部分には、同一符号を付して示しである。Figures 5(-) and 5(b) respectively show configuration examples of constant current source circuits constructed using this device. This is an indication.
これらの回路例に示されるように、バーチカルトランジ
スタ８を以って構成される電流制御用トランジスタの高
周波特性を改善することにより、負荷ＲＬに安定な定電
流を供給することが可能となシ、その実用的利点は絶大
である。As shown in these circuit examples, by improving the high frequency characteristics of the current control transistor configured with the vertical transistor 8, it is possible to supply a stable constant current to the load RL. Its practical advantages are enormous.
陶、本発明は上記実施例にのみ限定されるものではない
。ここではバーチカルＰＮＰ ）ランジスタを例に説明
したが、これと逆導電型のバーチカルＮＰＮ型トランジ
スタについても、その逆性方向が逆になるだけで同様に
実施可能なことは云うまでもない。この場合、高周波特
性に優れたバーチカルＮＰＮ トランジスタの高周波特
性を更に向上させることができる。また増幅器１ノとし
ては、トランジスタ１段のエミッタ・ホロア回路に代え
て、増幅度が１に設定された他の回路を用いるようにし
てもよい。またこの増幅器１ノをバーチカルトランジス
タ８を°形成した半導体基板上以外に形成することも勿
論可能である。要するに本発明はその要旨を逸脱しない
範囲で種々変形して実施することができる。However, the present invention is not limited to the above embodiments. Although a vertical PNP transistor has been explained here as an example, it goes without saying that the same implementation is possible with a vertical NPN transistor of the opposite conductivity type, just by reversing the direction of its reversibility. In this case, the high frequency characteristics of the vertical NPN transistor, which has excellent high frequency characteristics, can be further improved. Further, as the amplifier 1, another circuit whose amplification degree is set to 1 may be used instead of the emitter follower circuit with one stage of transistors. Furthermore, it is of course possible to form the amplifier 1 on a substrate other than the semiconductor substrate on which the vertical transistor 8 is formed. In short, the present invention can be implemented with various modifications without departing from the gist thereof.
第１図はバーチカルトランジスタの構造を示す図、第２
図はバーチカルトランジスタの電気的な等価回路を示す
図、第３図は本発明に係る装置の基本構成図、第４図は
実施例装置の構造を示す図、第５図（、） 、、 （ｂ
）は本発明の応用回路例を示す図である。
１・・・半導体基板、２・・・）コーラエル、０・バー
チカルトランジスタ、１Ｏ・・・寄生ダイオード、１１
・・・増幅器、１２・・・サブストレートトランジスタ
。Figure 1 shows the structure of a vertical transistor, Figure 2 shows the structure of a vertical transistor.
The figure shows an electrical equivalent circuit of a vertical transistor, FIG. 3 is a basic configuration diagram of a device according to the present invention, FIG. 4 is a diagram showing the structure of an embodiment device, and FIG. 5 (, ), ( b
) is a diagram showing an example of an applied circuit of the present invention. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 2...) Coral El, 0. Vertical transistor, 1O... Parasitic diode, 11
...Amplifier, 12...Substrate transistor.
Claims (1)
シ素子間分離して形成されたバーチカルトランジスタと
、このバーチカルトランジスタを素子間分離する上記逆
導電性半導体層の電位を前記バーチカルトランジスタの
コレクタ電位と略同電位に保つ手段とを具備したことを
特徴とする半導体装置。 （２）逆導電性半導体層の電位をバーチカルトランジス
タのコレクタ電位と略同電位に保つ手段は、該コレクタ
電位を入力とするエミッタ・ホロア回路からなるもので
ある特許請求の範囲第１項記載の半導体装置。 （３） エミッタ・ホロア回路は、素子間分離してバー
チカルトランジスタを形成した一導電性半導体基板上に
形成された、サブストレートトランジスタにより構成さ
れるものである特許請求の範囲第２項記載の半導体装置
。[Claims] (1) A vertical transistor formed on a conductive semiconductor substrate with elements separated by a reverse conductive semiconductor layer, and the reverse conductive semiconductor layer separating the vertical transistors between elements. A semiconductor device comprising means for maintaining the potential of the semiconductor layer at approximately the same potential as the collector potential of the vertical transistor. (2) Maintaining the potential of the opposite conductive semiconductor layer at approximately the same potential as the collector potential of the vertical transistor. The semiconductor device according to claim 1, wherein the means comprises an emitter follower circuit that receives the collector potential as an input. (3) The emitter follower circuit is formed by separating elements to form a vertical transistor. 3. The semiconductor device according to claim 2, which comprises a substrate transistor formed on a conductive semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58243533A JPS60136249A (en) | 1983-12-23 | 1983-12-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58243533A JPS60136249A (en) | 1983-12-23 | 1983-12-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60136249A true JPS60136249A (en) | 1985-07-19 |
| JPH0556019B2 JPH0556019B2 (en) | 1993-08-18 |
Family
ID=17105304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58243533A Granted JPS60136249A (en) | 1983-12-23 | 1983-12-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60136249A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62126704A (en) * | 1985-11-20 | 1987-06-09 | エスジ−エス マイクロエレツトロニカ ソチエタ ペル アツイオニ | Apparatus for minimize parasitic junction capacitor of insulated collector vertical pnp transistor |
| JPS62206911A (en) * | 1986-02-28 | 1987-09-11 | エス ジ− エス ミクロエレトロニカ エス ピ− エ− | Wide-band amplifier |
-
1983
- 1983-12-23 JP JP58243533A patent/JPS60136249A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62126704A (en) * | 1985-11-20 | 1987-06-09 | エスジ−エス マイクロエレツトロニカ ソチエタ ペル アツイオニ | Apparatus for minimize parasitic junction capacitor of insulated collector vertical pnp transistor |
| JPH073933B2 (en) * | 1985-11-20 | 1995-01-18 | エスジ−エス マイクロエレツトロニカ ソチエタ ペル アツイオニ | Device for minimizing parasitic junction capacitance of insulated collector vertical PNP transistor |
| JPS62206911A (en) * | 1986-02-28 | 1987-09-11 | エス ジ− エス ミクロエレトロニカ エス ピ− エ− | Wide-band amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0556019B2 (en) | 1993-08-18 |
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