JPH01225350A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPH01225350A JPH01225350A JP5213088A JP5213088A JPH01225350A JP H01225350 A JPH01225350 A JP H01225350A JP 5213088 A JP5213088 A JP 5213088A JP 5213088 A JP5213088 A JP 5213088A JP H01225350 A JPH01225350 A JP H01225350A
- Authority
- JP
- Japan
- Prior art keywords
- crystal defect
- groove
- defect layer
- layer
- argon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000013078 crystal Substances 0.000 claims abstract description 24
- 230000007547 defect Effects 0.000 claims abstract description 23
- 238000002513 implantation Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 17
- 229910052710 silicon Inorganic materials 0.000 abstract description 17
- 239000010703 silicon Substances 0.000 abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 14
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 13
- 229910001385 heavy metal Inorganic materials 0.000 abstract description 12
- 229910052786 argon Inorganic materials 0.000 abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 10
- 150000002500 ions Chemical class 0.000 abstract description 9
- -1 argon ions Chemical class 0.000 abstract description 7
- 238000005530 etching Methods 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 7
- 239000000377 silicon dioxide Substances 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 abstract description 2
- 238000005247 gettering Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000005488 sandblasting Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置の製造方法に関し、特に重
金属イオンを除去したリーク電流の少ないトレンチキャ
パシタのの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for manufacturing a trench capacitor from which heavy metal ions are removed and leakage current is small.
従来、この種の半導体集積回路装置の製造方法ではサン
ドブラスト法、或はエキシマレーザ−照射等によってシ
リコン基板裏面に予め結晶欠陥層を形成する。次に前記
シリコン基板にホトレジストで溝エツチングの為のパタ
ーンを形成し、続いてRIE (Reactive I
on Erching)を利用して前記シリコン基板を
エツチングし溝を形成する。Conventionally, in the manufacturing method of this type of semiconductor integrated circuit device, a crystal defect layer is previously formed on the back surface of a silicon substrate by sandblasting, excimer laser irradiation, or the like. Next, a pattern for trench etching is formed on the silicon substrate using photoresist, followed by RIE (Reactive I).
The silicon substrate is etched to form a groove.
次に前記ホトレジストを除去した後高温の酸素雰囲気中
で前記シリコン基板表面及び前記溝内壁にSiO□膜を
形成する。次いで前記シリコン基板表面全域に前記溝を
充填し、かつ表面が平坦になる様にリンドープ多結晶シ
リコン膜を形成する。Next, after removing the photoresist, a SiO□ film is formed on the surface of the silicon substrate and the inner wall of the trench in a high temperature oxygen atmosphere. Next, a phosphorus-doped polycrystalline silicon film is formed so that the trench is filled over the entire surface of the silicon substrate and the surface is flat.
次にホトレジストをマスクにしてキャパシタ形成部以外
の前記リンドープ多結晶シリコン膜を選択的にエツチン
グ除去する。以上の工程を経ることによってトレンチキ
ャパシタを形成し、その後、熱処理を行なうことで溝エ
ツチング時に溝内壁からシリコン基板中に入り込んだ重
金属イオンを前記シリコン基板裏面の結晶欠陥層でゲッ
タリングするものであった。Next, using a photoresist as a mask, the phosphorus-doped polycrystalline silicon film other than the capacitor forming portion is selectively etched away. A trench capacitor is formed through the above steps, and then heat treatment is performed to getter the heavy metal ions that entered the silicon substrate from the inner wall of the trench during trench etching in the crystal defect layer on the back surface of the silicon substrate. Ta.
ところが上述した従来の半導体集積回路装置の製造方法
では、重金属イオンなゲッタリングする結晶欠陥層を半
導体集積回路装置の製造工程中、最も初期にサンドブラ
スト及びエキシマレーザ−照射による機械歪で形成して
いる為、トレンチキャパシタを形成する工程以前のNウ
ェルやフィールド酸化膜を形成する熱処理時に結晶欠陥
が回復してしまい、トレンチキャパシタを形成する時に
はゲッタリングの効果が無くなってしまうという欠点が
有った。さらに結晶欠陥層がシリコン基板裏面に形成さ
れている為に、トレンチキャパシタの形成領域から遠く
ゲッタリングの効果が十分に得られないという欠点も有
った。従ってトレンチキャパシタ付近のゲッタリングし
きれなかった残留重金属イオンによってキャパシタに蓄
積された電荷がリークし、MOSダイナミック’RAM
のホールドタイムが悪化するという問題点があった。However, in the conventional method for manufacturing semiconductor integrated circuit devices described above, a crystal defect layer that getters heavy metal ions is formed at the earliest stage of the manufacturing process of semiconductor integrated circuit devices by mechanical strain using sandblasting and excimer laser irradiation. Therefore, crystal defects are recovered during the heat treatment for forming the N-well or field oxide film before the step of forming the trench capacitor, and the gettering effect is lost when forming the trench capacitor. Furthermore, since the crystal defect layer is formed on the back surface of the silicon substrate, there is also the drawback that a sufficient gettering effect cannot be obtained far from the formation region of the trench capacitor. Therefore, the charge accumulated in the capacitor leaks due to the residual heavy metal ions that could not be gettered near the trench capacitor, and the MOS dynamic RAM
There was a problem in that the hold time of the device worsened.
〔発明の従来技術に対する相違点〕
上述した従来の半導体集積回路装置の製造方法に対し本
発明は、トレンチキャパシタの溝を形成した直後に溝内
壁に結晶欠陥層を形成し、その結晶欠陥層で半導体基板
中の重金属をゲッタリングした後に結晶欠陥層を除去す
ることによりリーク電流の少ないトレンチキャパシタを
形成出来るという相違点を有する。[Differences between the invention and the prior art] In contrast to the above-described conventional method of manufacturing a semiconductor integrated circuit device, the present invention forms a crystal defect layer on the inner wall of the trench immediately after forming the groove of a trench capacitor, and the crystal defect layer The difference is that a trench capacitor with low leakage current can be formed by removing the crystal defect layer after gettering heavy metals in the semiconductor substrate.
本発明の半導体集積回路装置の製造方法は、半導体基板
に表面から内部に向かう溝を形成する工程と、前記溝の
内壁に不活性元素をイオン注入し、溝内壁の半導体基板
に不活性元素注入層を形成する工程と、前記半導体基板
を熱処理し注入された不活性元素を核に半導体基板中に
結晶欠陥層を形成する工程と、前記溝内壁の結晶欠陥層
を酸化しきる工程とを含んで構成される。The method for manufacturing a semiconductor integrated circuit device of the present invention includes the steps of forming a groove in a semiconductor substrate from the surface toward the inside, implanting ions of an inert element into the inner wall of the groove, and implanting the inert element into the semiconductor substrate on the inner wall of the groove. a step of heat-treating the semiconductor substrate to form a crystal defect layer in the semiconductor substrate using the implanted inert element as a core, and a step of completely oxidizing the crystal defect layer on the inner wall of the groove. configured.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
まず第1図に示すようにP型比抵抗4〜5Ω・口の<1
00>結晶方向を有するシリコン基板1に表面から内部
に向けてホトレジスト2をマスクして選択的にエツチン
グし、深さ2〜3μmの溝3を形成する。溝のエツチン
グはRI E (React 1veIon Etch
ing)を用いて異方的に行なう0次に第2図に示すよ
うに前記ホトレジスト2をマスクにして前記溝3の内壁
にアルゴンイオン5を注入し、シリコン基板lにアルゴ
ン注入層6を形成する。First, as shown in Figure 1, the P type resistivity is 4~5Ω/<1
A trench 3 having a depth of 2 to 3 μm is formed by masking and selectively etching a photoresist 2 from the surface to the inside of a silicon substrate 1 having a crystal orientation of 00>. Groove etching is done using RIE (React 1veIon Etch).
Next, as shown in FIG. 2, argon ions 5 are implanted into the inner wall of the groove 3 using the photoresist 2 as a mask to form an argon implantation layer 6 on the silicon substrate 1. do.
この時アルゴンイオン5は斜め回転イオン注入法を用い
、10〜30KeVのエネルギーでシリコン基板1に対
して5〜30度の角度で注入量はIX 10”’〜I
X 1014an″″2で注入するのが望ましい。また
アルゴンイオン5をマスキングするホトレジストは第1
図で説明した溝のエツチングに使用したものを流用する
0次に第3図に示すようにホトレジストを除去した後9
50〜1100℃の窒素雰囲気中で10〜30分間熱処
理を加え、アルゴン注入層6のアルゴンイオンを核にし
て結晶欠陥層7を形成する。更に800〜900℃の窒
素雰囲気中で1〜3時間熱処理を加える事によってシリ
コン基板中の重金属イオン4が結晶欠陥層7にゲッタリ
ングされる。次に第4図に示すように溝3の内壁を含む
シリコン基板1の表面を酸化し300〜500人の二酸
化シリコン膜8を形成する。この時二酸化シリコン膜は
結晶欠陥層にゲッタリングされた重金属イオンを取り込
む、また、この二酸化シリコン膜の膜厚は第3図の結晶
欠陥層7を完全に酸化しきる様に設定しなければならな
い。次に第5図に示すように二酸化膜8を除去した後、
第6図に示すように溝3の内壁を含むシリコン基板1の
表面に厚さ100〜150人の二酸化シリコンまたは二
酸化シリコンと窒化シリコンから成る容量絶縁膜9を形
成する。更にトレンチキャパシタの電極となるリンドー
プ多結晶シリコン膜10を形成し、前記溝3を充填する
。At this time, the argon ions 5 are implanted using an oblique rotational ion implantation method, with an energy of 10 to 30 KeV, at an angle of 5 to 30 degrees with respect to the silicon substrate 1, and the amount of implantation is IX 10"' to I
It is preferable to inject at 1014an''2. Also, the photoresist masking the argon ions 5 is the first one.
After removing the photoresist as shown in Figure 3, we reused the material used for etching the grooves explained in Figure
A heat treatment is applied for 10 to 30 minutes in a nitrogen atmosphere at 50 to 1100° C. to form a crystal defect layer 7 using argon ions in the argon injection layer 6 as nuclei. Further, by applying heat treatment for 1 to 3 hours in a nitrogen atmosphere at 800 to 900° C., heavy metal ions 4 in the silicon substrate are gettered to the crystal defect layer 7. Next, as shown in FIG. 4, the surface of the silicon substrate 1 including the inner wall of the groove 3 is oxidized to form a silicon dioxide film 8 of 300 to 500 layers. At this time, the silicon dioxide film takes in the heavy metal ions gettered into the crystal defect layer, and the thickness of this silicon dioxide film must be set so as to completely oxidize the crystal defect layer 7 shown in FIG. 3. Next, as shown in FIG. 5, after removing the dioxide film 8,
As shown in FIG. 6, a capacitive insulating film 9 made of silicon dioxide or silicon dioxide and silicon nitride is formed to a thickness of 100 to 150 nm on the surface of the silicon substrate 1 including the inner wall of the groove 3. Further, a phosphorus-doped polycrystalline silicon film 10, which will become an electrode of a trench capacitor, is formed to fill the trench 3.
次に通常のホトエツチング法を用いて選択的に前記リン
ドープ多結晶シリコン膜lOを除去し、トレンチキャパ
シタAを形成する(第7図)。Next, the phosphorus-doped polycrystalline silicon film IO is selectively removed using a conventional photoetching method to form a trench capacitor A (FIG. 7).
以上説明したように本発明は、結晶欠陥層なトレンチキ
ャパシタ形成中に溝内壁に形成し、重金属なゲッタリン
グした後除去することにより、トレンチキャパシタ形成
領域のシリコン基板に残留する重金属を効果的に取り除
ける。また溝エツチング時にプラズマによって受けたダ
メージ層をも除去できリーグ電流の少ないトレンチキャ
パシタを形成できる効果がある。As explained above, the present invention effectively removes heavy metals remaining on the silicon substrate in the trench capacitor formation region by forming a crystal defect layer on the inner wall of the trench during formation of the trench capacitor and removing it after gettering the heavy metal. It can be removed. Furthermore, the damaged layer caused by plasma during trench etching can also be removed, making it possible to form a trench capacitor with a small league current.
第1図から第7図は本発明の実施例を工程順に示す断面
図である。
l・・・・・・シリコン基板、2・・・・・・ホトレジ
スト、3・・・・・・溝、4・・・・・・重金属イオン
、5・・・・・・アルゴンイオン、6・・・・・・アル
ゴン注入層、7・・・・・・結晶欠陥層、8・・・・・
・二酸化シリコン膜、9・・・・・・容量絶縁膜、10
・・・・・・リンドープ多結晶シリコン膜、A・・・・
・・トレンチキャパシタ。
代理人 弁理士 内 原 音
¥f2図1 to 7 are cross-sectional views showing an embodiment of the present invention in the order of steps. 1...Silicon substrate, 2...Photoresist, 3...Groove, 4...Heavy metal ion, 5...Argon ion, 6... ... Argon injection layer, 7 ... Crystal defect layer, 8 ...
・Silicon dioxide film, 9...Capacitive insulating film, 10
...Phosphorus-doped polycrystalline silicon film, A...
...Trench capacitor. Agent Patent Attorney Uchihara Oto¥f2 diagram
Claims (1)
と、前記溝の内壁に不活性元素をイオン注入し、溝内壁
の半導体基板に不活性元素注入層を形成する工程と、前
記半導体基板を熱処理し前記不活性元素注入層の不活性
元素を核に半導体基板中に結晶欠陥層を形成する工程と
、前記溝内壁の結晶欠陥層を酸化しきる工程とを含むこ
とを特徴とする半導体集積回路装置の製造方法。a step of forming a groove in the semiconductor substrate from the surface toward the inside; a step of ion-implanting an inert element into the inner wall of the groove to form an inert element implantation layer in the semiconductor substrate on the inner wall of the groove; and heat treating the semiconductor substrate. A semiconductor integrated circuit device comprising the steps of forming a crystal defect layer in a semiconductor substrate using the inert element of the inert element injection layer as a core, and completely oxidizing the crystal defect layer on the inner wall of the groove. manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5213088A JPH01225350A (en) | 1988-03-04 | 1988-03-04 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5213088A JPH01225350A (en) | 1988-03-04 | 1988-03-04 | Manufacture of semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01225350A true JPH01225350A (en) | 1989-09-08 |
Family
ID=12906286
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5213088A Pending JPH01225350A (en) | 1988-03-04 | 1988-03-04 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01225350A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7226846B2 (en) * | 2004-01-07 | 2007-06-05 | Oki Electric Industry Co., Ltd. | Method of dry etching semiconductor substrate to reduce crystal defects in a trench |
JP2015032720A (en) * | 2013-08-05 | 2015-02-16 | 新日本無線株式会社 | Semiconductor device manufacturing method |
-
1988
- 1988-03-04 JP JP5213088A patent/JPH01225350A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7226846B2 (en) * | 2004-01-07 | 2007-06-05 | Oki Electric Industry Co., Ltd. | Method of dry etching semiconductor substrate to reduce crystal defects in a trench |
JP2015032720A (en) * | 2013-08-05 | 2015-02-16 | 新日本無線株式会社 | Semiconductor device manufacturing method |
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