JPH01213741A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To considerably reduce the number of times of synchronous communication between CPUs and to improve the parallel processing capability by storing a series of commands as a new command group and successively executing this command group. CONSTITUTION:A master CPU 1 writes a command for output contents to a shared memory 2 at the time of output to a display device 4. A slave CPU 3 reads out the command written in the shared memory 2 and performs the processing in accordance with a program in a ROM 5. The master CPU 1 transfers segment execution commands to the shared memory 2 to terminate the processing. Meanwhile, the slave CPU 3 receives segment execution commands by synchronous communication with the master MPU 1 and executes the first command and successively executes commands till the end of a segment. The picture on the display device 4 is switched with only one synchronous communication.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention is designed to transfer a command from a master CPU to a slave CPU, and execute processing corresponding to the sent command in the slave CPU. Regarding multiprocessor systems.

(Prior Art) An example of a conventional multi-processor system is shown in FIG.

In the figure, 11 is a master CPU, 12 is a shared memory, 13 is a slave CPU, and 14 is a ROM.

This system allows the master CPU to perform complex processing such as input/output timing control using the slave CPU 13.
This is used to reduce the burden on Il and achieve high-speed processing. That is, a command is transferred from the master CPU II to the slave CPU 13 via the shared memory 12, and the slave CPU 13 analyzes the command using a program in the ROM 14 and executes processing corresponding to the command.

(Problems to be Solved by the Invention) However, in the conventional system described above, when various commands are executed one after another, synchronization between the master CPU 11 and the slave CPU 13 must be achieved many times. FIG. 4 shows the data processing procedure (flowchart) at this time.

For this reason, the mask CPU II often stops waiting for the slave CPU 13 to complete its processing, resulting in a problem that the overall processing speed decreases.

(Means for Solving the Problem) The present invention provides a multiprocessor system in which a command is transferred from a master CPU to a slave CPU, and the slave CPU executes processing corresponding to the sent command. Storage means for storing a series of commands transferred from the master CPU as new commands is provided on the slave CPU side.

(Operation) A series of commands is stored in the storage means as a new command. By sequentially executing a series of commands using the stored commands, the number of communications between the CPUs is reduced.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a schematic block diagram of a multiprocessor system of the present invention.

In the figure, 1 is the master CPU, 2 is the shared memory, and 3 is the master CPU.
4 is a display device such as a CRT display, 5 is a ROM, and 6 is a segment command memory.

The segment command memory 6 stores a group of - series of commands as new commands among the commands transferred one after another from the master CPU 1.

For example, a group of commands for one screen to be output to the display device 4 may be stored as new commands in the segment command memory 6 (such a series of commands is stored in the master CP).
This can be specified from the UI side, and multiple such memories are prepared.

Next, the operation of the multiprocessor system having the above configuration will be explained.

When the master CPUI outputs to the display device 4, it first writes a command corresponding to the output content into the shared memory 2. The slave CPU 3 reads the command written in the shared memory 2, and executes the process corresponding to this command from the ROM.
Execute according to the program stored in 5. At this time, if the command written to the shared memory 2 is a segment execution command that executes a series of commands stored in the segment command memory 6, the slave CPU 3 executes the series of commands from the segment command memory 6. The commands are read and processes corresponding to this series of commands are sequentially executed according to the program stored in the ROM 5.

FIG. 2 shows the data processing procedure at this time. That is,
The master CPU 1 transfers the segment execution command to the shared memory 2 and ends the process (step ■). On the other hand, the slave CPU 3 performs synchronous communication with the master CPU 1 to receive the segment execution command (step (2)), and in step (2) first executes the first command of the series of commands.

Then, in step (2), it is determined whether the segment has ended, and if it has not ended, the process returns to step (2) and executes the second command. The series of steps ① and ② is executed in sequence, and the final command is executed and the process ends. In this way, in the multiprocessor system of the present invention, one screen of the display device 4 can be switched by only one synchronous communication, and after the synchronous communication, the master cput can perform other processing. , it is possible to increase parallel processing capacity.

(Effects of the Invention) As explained above, according to the multiprocessor system of the present invention, the number of synchronous communications between CPUs can be significantly reduced. Moreover, this improves the parallel processing ability between the CPUs and enables high-speed processing.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a multiprocessor system of the present invention, FIG. 2 is a flowchart of the same system, and FIG. 3 is a schematic block diagram of a conventional multiprocessor system.
FIG. 4 is a flowchart of the system. 1... Master CPU 2... Shared memory 3...
・Slave CPU 4...Display device 5...ROM
6... Segment Command Memory Patent Applicant Sekisui Chemical Co., Ltd. Representative Hiroshi 1) Kaoru No. 7 WJ Figure 2 (Master CPU) Fukirep CPU) Figure 3

Claims (1)

[Claims] 1) In a multiprocessor system configured to transfer a command from a master CPU to a slave CPU, and execute processing corresponding to the sent command in the slave CPU, A multiprocessor system, characterized in that a storage means for storing a series of commands as new commands is provided on the slave CPU side.