JPH01226250A - Data communication system - Google Patents

Abstract

PURPOSE:To speed up the processing and transfer of a packet and to simplify a procedure by using a two-port RAM where a half flag is provided in an output FIFO in a packet dispatcher. CONSTITUTION:The output FIFO 12 uses the two-port RAM where the half flag(HF) is provided, and a certain packet is detected to be not empty (EF) in an input FIFO11 and that half the packet becomes empty is detected in the half flag from the output FIFO12, whereby a continuous processing can be executed with respect to the subsequent packet. Input information is inputted to the input FIFO11 in the packet dispatcher 10, a prescribed read processing is executed, processed information is transmitted to the output FIFO12, and the packet processing and transfer are continuously executed by the detection of the half flag. For smoothly executing the continuous action, input status registers(ISR) 131-13n showing the units of the number of input data to be stored from a control part 6 are provided in graphic processing units 21-2n which supply the outputs of the output FIFO12 in parallel.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to an improvement of a data communication system having a packet dispatcher that outputs input information as a predetermined amount of packets, and speeds up the processing and transfer time of packets in the packet dispatcher. For this purpose, the packet dispatcher has an input FIF that has a flag indicating whether the memory capacity is empty or full, and that reads input information and performs predetermined processing.
O, and an output FIFO having a half flag indicating half of the external capacity of both the flags and transferring the processed input information to a predetermined processing unit, the input FIFO
Detects that O is not empty, reads the input information from the FIFO, performs the specified processing, and sends it to the output FIFO. Once the half flag is detected and confirmed, it is continuously transferred to the processing unit as long as the output FIFO is not full. Configure it to do so.

[Industrial application field]

The present invention relates to an improvement in a data communication system having a packet dispatcher that outputs input information as a predetermined amount of packets.

[Conventional technology]

Conventionally, when performing processing such as coordinate transformation or clipping of a graphic, input information consisting of graphic processing commands and graphic data is transferred as a packet to a plurality of graphic processing units connected in parallel using a packet dispatcher.

FIG. 4 shows a configuration considered in the prior art when a FIFO is used for transferring conventional data packets, although it has not been put to practical use as a packet dispatcher.

For example, a command when converting the coordinates of a figure, each unit of X, Y coordinate data is input into the input PIFO 4 in the unit 1, outputs Mt, and the predetermined p is controlled by the control unit B. The processed information is sent to the output PIFO 5, sequentially written in a predetermined number of units to the graphic processing units 21 to 2n under the control of the control unit 6, and the output information is output from the output control unit 3 connected in parallel. is taken out.

[Problem to be solved by the invention]

In the above configuration, if a conventional shift register is used to provide an output FIFO function for processing and transferring data as a packet, only about 64 words can be stored at most.

Furthermore, this FIFO starts the next packet after the previous packet ends. In other words, the previous packet was transferred with a flag indicating full, and the next packet was transferred after the flag indicating empty was detected, so the transfer took a long time. .

The inventor of the present invention found that by using a 2-baud RAM for this FIFO, the capacity can be increased to approximately 512/1024 words, and also that a half flag indicating half of the capacity, which is provided for another purpose, can be used. The present invention focuses on the fact that this detection enables continuous processing, which will be described later.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data communication system that speeds up packet processing and transfer time in packet dispatch.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a data communication method having a packet dispatcher that outputs input information consisting of processing instructions and data such as graphics as a predetermined amount of packets. It has an input FIFO that has a flag indicating whether it is full and that reads input information and performs a predetermined process, and a half flag that indicates half of the eccentricity of both flags, and reads the input information and performs a predetermined process. It detects that the input FIFO is not empty, reads the input information from the FIFO, performs predetermined processing, and sends it to the output FIFO, and when a half flag is detected and confirmed, output Data is continuously transferred to the processing unit within a range that does not exceed the FIFO's full capacity.

[For production]

As shown in the principle explanatory diagram of FIG. 1, the difference from the conventional technology shown in FIG. 4 is that the output FIFO 12 is a 2-baud R
This is because AM was used. After detecting that the input FIFO 11 is not empty (EF) for a certain packet,
By detecting with a half flag (HF) that the output FIFO 12 is halfway full, it becomes possible to continuously process the next packet.

As mentioned above, in the case of 2 baud) RAM FIFO, 51
Even half of 2 words uses 256 words, and the capacity is several times the register FIFO.When instructions and data are stored in one FIFO, the data procedure is similar to that of the register FIFO, as shown in the flowchart below. It also has the advantage of being simplified.

〔Example〕

FIG. 2 is an explanatory diagram of the configuration of an embodiment of the present invention.

In the figure, input information consisting of processing instructions and data such as graphics is input to the input FIFO in the packet dispatcher 10.
11 and performs predetermined reading processing. The processed information is then sent to the output FIFO 12 described in FIG. 1, and packet processing and transfer are continuously performed by half flag (HF) detection.

In order to perform this continuous operation smoothly, the output FIFO12
Graphic processing unit 21 * 21e that supplies the output of
..., an input status register (■5R) 13 indicating the number of units of input data to be stored by the control unit 6 for 2%.
1* 1321..., 13% is provided.

Now, assuming that the number of input data to the graphic processing unit is constant,
The data are sent to the graphic processing units 21 to 2n in the order in which they are input. Therefore, the data is temporarily stored in the output FIFO 12 and transferred. In this case, when the control section 6 has prepared the number of input data units to the graphic processing unit 2 in the output FIFO 12, it writes the number of input data into the corresponding l5R12. The graphic processing unit 2 reads the ISR, and if it is in a ready state, inputs the same number of data from the output FIFO, and when the input is completed, the graphic processing unit 2 resets the ISR.

In this way, packet data is sequentially packed.

The main part of the present invention is the output FIFO 12 for preparing data to be transferred to the graphic processing unit 2. In other words, in order to continuously process and transfer packet data,
A 2-baud RAM with a half flag is used, and a durable packet is sent when half of the memory capacity is empty.

FIG. 6 is a flowchart showing the operation of the output FIFO, which is the essential part of the present invention.

In the same figure, when reading the empty flag (EF)-e of the output FIFO 12 and confirming that it is not empty,
Reads commands from input FIFO 11, interprets commands,
Process. Next, the 8-7 flag (HF) of the output FIFO 12 is read, and after confirming that more than half of it is empty, an instruction is written to the output FIFO 12. Since the above instructions are processing instructions for graphics, etc., the read and write procedures for a plurality of related data are sequentially performed and transferred in the following order. In this case, as shown by the number of cycles in the procedure on the side, the half flag (HP) reading procedure can be omitted, so the procedure is shorter than in the case of using the shift register in the prior art shown in Fig. 4. saving power) becomes possible. .

= 2°, 5°, 2ELHK 1*t4. 2, 7° with a half 7 ring provided in the output FIFO in the dispattier
By using the punt RAM, it is possible to speed up punt processing and transfer, and to simplify the procedure.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an explanatory diagram of the configuration of an embodiment of the invention, Fig. 3 is a flowchart showing the operation of the main parts of the embodiment, and Fig. 4 is an explanatory diagram of the prior art. C, in the figure, 21-2n
is a graphic processing unit, 3 is an output control section, 6 is a control section, 1
0 is the packet dispatcher, 11 is the input FIFO 1
12 indicates an output FIF0°15, and 13s indicates an input status register Cl5R).

Claims (1)

[Claims] In a data communication system having a packet dispatcher that outputs input information consisting of processing instructions and data such as graphics as a predetermined amount of packets, the packet dispatcher has a memory capacity that is empty or full. an input FIFO that reads input information and performs predetermined processing; and a half flag that indicates half of the external capacity of both flags, and transfers the processed input information to a predetermined processing unit. It detects that the input FIFO is not empty, reads input information from the FIFO, performs predetermined processing, and sends it to the output FIFO, and when a half flag is detected and confirmed, the output FIFO is determined to be full. A data communication method characterized in that data is continuously transferred to a processing unit within a range that does not exceed the limit.