JPH04205873A - Fifo memory device - Google Patents

Abstract

PURPOSE:To eliminate a futile memory area by controlling the number of outputted flags by means of the amount of the data written in a memory when the writing speed in the memory is different from the reading-out speed from the memory. CONSTITUTION:In the case of data transfer where the writing data transferring speed is different from the read-out data transferring speed, the number of outputted flags is controlled by the amount of the data stored in a memory and the data transfer is controlled by using the flags. Namely, flag sections 3 and 12 always compare the amount of the data stored in the memory with the amounts of data stored in registers 4 and 13 and, when the actual amount of data becomes equal to the values of the registers 4 and 13, output the flags. When the amounts of data written in the registers 4 and 13 are changed from each other and the registers 4 and 13 are selected, the amount of the data stored in the memory can be optimized. Therefore, the area of a futile memory area which is generated when the number of outputted flags is fixed can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to a FIFO which has a function of outputting a flag according to the amount of data stored in a memory and which controls flag output.
The present invention relates to a memory device (first-in, first-out memory device).

2. Prior Art A conventional FIFO memory device compares the amount of data stored in the memory of the FIFO memory device with a constant value in a flag section that receives the output from a section that calculates the amount of data stored in the memory. controls the flag output.

FIG. 4 shows an example of a conventional FIFO memory device W. FI
The amount of data input to the FO memory device 1 is calculated by the data amount calculating section 2 by inputting the values of the write point and the read point. The output 5 of the data amount calculation section 2 represents the value of the data amount, and is input to the flag section 3. The flag unit 3 outputs a flag output when the data amount 5 exceeds a certain value.

Problems to be Solved by the Invention In a conventional FIFO memory device that has a function of outputting a flag depending on the amount of data stored in the memory, the amount of data for outputting the flag is fixed.

When controlling data transfer in which the data transfer rate for writing to the FIFO memory device and the data transfer rate for reading from the PIFO memory device are different using a flag output according to the amount of data stored in the memory of the FIFO memory device, for example, write Let us consider the case where the read speed is low and reading is fast due to DMA transfer. FIFO
Memory device! There is low-speed data writing, and a DMA transfer is requested by outputting a flag depending on the amount of data stored in the memory. At this time, since the output of the flag is fixed, the amount of data written in the time from the output of the flag until the start of DMA transfer is limited to the FIFO shown in FIG. As shown in the memory map of the memory device, a small memory area is used and the remaining area is not used, resulting in wasted memory. The memory map in Figure 5 shows how a flag is output to request DMA transfer depending on the amount of data written to the memory, the amount of data written between the request and the start of DMA transfer, and the amount of wasted memory. It shows the area.

In addition, there are multiple different writing speeds, and the above FIF
When connected to an O memory device, it is not possible to output flags corresponding to multiple transfer speeds.
Memory space was wasted for multiple transfer speeds.

The present invention solves the above problem, and aims to provide a FIFO memory device that controls flag output according to the amount of data written to the memory and eliminates wasted memory area.

Means for Solving the Problems In order to solve the above problems, the FIFO memory device of the present invention provides a method for controlling the flag output based on the amount of data written in the memory of the FIFO memory device. A plurality of registers are provided to store the data, and a data amount calculation unit is provided that inputs the values of the write point and read point to the memory, calculates and outputs the amount of data stored in the memory, and the data amount calculation unit A plurality of flag units are provided which take the output of the register as an input and the output of the register as an input, compare the two inputs, and control the flag output.

Effect of the Invention With the above-described configuration, the present invention controls the flag output according to the amount of data stored in the memory during data transfer in which the data transfer rate for writing to the FIFO memory device and the data transfer rate for reading from the FIFO memory device are different. Data transfer is controlled by In other words, the flag section constantly compares the amount of data stored in memory and the amount of data stored in the register, and when the actual amount of data is equal to or larger than the value in the register, a flag is output from the flag section. However, at this time, by changing the amount of data written to multiple registers and selecting this register, the amount of data stored in memory can be set to the optimal value. The wasted memory area can be reduced. Therefore, for multiple transfer rates,
Optimal flag output can be performed with one FIFO memory device.

Example An example of the present invention will be explained below based on the drawings.

FIG. 1 shows a FIFO memory device according to an embodiment of the present invention!
FIG. In FIG. 1, it is assumed that the FIFO memory device W1 is capable of writing, for example, 512 pieces of data. Also, as shown in Figure 3, this FIF
A plurality of devices perform writing 19.20 to the memory device 1 at their respective transfer speeds, and when the amount of data stored in the memory reaches a certain value, a flag 18 is output and a request 21 for DMA transfer is sent to the DMA controller 10. and DMA
The controller 10 is configured to perform a DMA transfer 22 upon receiving a transfer request. For example, it is assumed that there are data transfers when the input rate is 8 Hz and data transfers when the input rate is 10 Hz, which are written to the FIFO memory device 1. It is also assumed that the DMA transfer 22 is performed using the amount of data stored in the memory of the FIFO memory device 1 in order to read data at high speed.

That is, in FIG. 3, if there is a write 19 at 8 Hz, the FIFO memory device 1 will write 8 when the amount of data stored in the memory reaches a certain value.
Output KHz flag 7 and select signal 1 for 8KHz device
6 as flag output 18]) M A
It is input to the controller 10. Also, if there is a write 20 with a speed of Hz in 10, then the FIFO memory device 1
outputs the Hz flag 14 to 10 when the amount of data stored in the memory reaches another certain value;
It is selected by the selection signal 17 of the lZ device and inputted to the DMA controller 10 as a flag output 18. On the other hand, the FIFO memory device 1 outputs a DMA transfer request 21 when outputting the flag 7.14. At this time, DM
The A controller 10 takes a maximum of 10 milliseconds from when the DMA transfer flag output 18 is input to when it starts the DMA transfer 22. In other words, F shown in Figure 2
In the memory map of the IFO memory device, after the flag is output, the FIFO memory device! It is sufficient to set the allowable amount of data written in memory 1 to 10 milliseconds or more until the data overflows. During 10 milliseconds, 80 pieces of data can be stored in a cycle of 8KHz, and 100 pieces can be stored in a cycle of 10KHz, so 80 pieces are subtracted from the total memory size of 512 pieces. 432 values and 5
The value obtained by subtracting 100 from 12 is 412, or the optimal amount of data at the start of DMA transfer. Therefore, this I&suit flag out cuff.

14 (H2 at 7.10 at 8 KHz) from outside the FIFO memory device 1 to the register (13 at 8 at Hz and 4.10 KHz in FIG. 1). Accordingly, it is possible to determine the timing of starting DMA transfer, which can reduce wasted memory area.

Next, the actual operation will be explained using FIG.

For example, 432 is written into register 4 from outside of FIFO memory device 1, and 412, for example, is written into register 13 from outside of FIFO memory device 1.

When the 8KHz device is selected by the selection signal 16, when data is written to the memory of the H2"C" FIFO memory device 1 at 8, the data gradually accumulates and is stored in the memory of the FIFO memory device 1. When the written data amount 5 exceeds the set value 6 of the register 4, that is, 432 pieces, the flag unit 3 outputs a flag 7. In response to a request for DMA transfer using the flag output, the DMA controller 10 starts DMA transfer and reads data from the memory of the FIFO memory device 1 at high speed. Also, 10K)
When the Iz device is selected by the selection signal 17, if the amount of data written to the memory exceeds the set value 11 of the register 13, that is, 412 pieces, the flag 1 is similarly set.
4 is output. DMA after issuing a DMA transfer request
The maximum time it takes for the transfer to start is 10 milliseconds, and the amount of data written by then is up to 8K.
At Hz, there are 80 pieces, and at 10 KHz, there are 100 pieces. Therefore, the wasted memory space is kept to a minimum value for a plurality of devices, and the wasted memory area can be suppressed to a minimum value for a plurality of writing speeds.

Effects of the Invention As described above, according to the present invention, when there are multiple writing speeds to the memory of the FIFO memory device and the writing speeds and the reading speed from the memory of the FIFO memory device are different, the FIFO memory device By controlling the flag output according to the amount of data written in the memory, the wasted memory area that occurs when performing high-speed read or write transfer can be minimized for multiple write speeds.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a FIFO memory device according to an embodiment of the present invention, and FIG. 2 is a memory map illustrating that flag output control in the FIFO memory device can be set at an optimal position for a plurality of devices. Figure 3 shows the FI
A block diagram illustrating an example of DMA transfer using an FO memory device, FIG. 4 is a schematic configuration diagram of a conventional FIFO memory device having a function of controlling flag output, and FIG.
The figure is a memory map illustrating the memory area of the flag fixed method used to determine the timing when data input at low speed is transferred at high speed in the conventional method. 1...FIFO memory device! , 2... Data amount calculation section, 3.12... Flag section, 4.13... Register. Agent Yoshihiro Morimoto Figure 7/Figure 2 Controlling flag output to start DMA transfer Amount of data written during the time until DMA transfer starts Memory map of the FIFO memory device Figure 3/1 /1. -FIFO end L9! #, 17 pieces 7” Tsuji-Riki Figure 4 FIFO memory device Figure 5 Starting DMA transfer ↑ Data amount Memory map of FIFO memory device

Claims (1)

[Claims] 1) A FIFO memory device that has a function of outputting a flag depending on the amount of data stored in the memory, and a plurality of registers that store the amount of data that controls flag output;
means for calculating the amount of data stored in the memory from the write point and the read point to the memory; input and compare the output from the register and the output from the data amount calculation means; and based on the comparison result. A FIFO memory device comprising a plurality of flag units for controlling flag output.