JPH11237972A - Functional memory, data processor utilizing the same and medium for recording compiler of the same processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a functional memory and a data processor with which the load on a CPU is reduced and a high-speed data processing is enabled. SOLUTION: When compiling a program to be processed, arrangement data to be processed are identified on the stage of compiling while being segmented into an arithmetic processing section to be performed by a CPU and an arithmetic processing section requiring a large amount data processings without successive processings by a functional memory 130 and are mapped so as to be stored in the functional memory 130. The functional memory 130 is provided with an arithmetic part 540 which has an arithmetic processing function and which is equipped with product/sum logic circuits 550 and 560 or the like. The arithmetic processing part 540 is provided with plural first-in first-out(FIFO) memories 500-510, and the arrangement data to become a source for executing the arithmetic processing section are written. A means is further provided for detecting finally written arrangement data from the CPU after arithmetic processings at the CPU and operation is performed while synchronizing the operation inside the functional memory 130 and the operation at the CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a functional memory which handles a large amount of data, particularly has a memory function, inputs and outputs data by accessing a memory space, and simultaneously performs arithmetic processing on the data. The present invention relates to a data processing device including:

[0002]

2. Description of the Related Art A conventional data processing apparatus is shown in FIG. 7
00 is a central processing unit (hereinafter, referred to as a central processing unit) that performs data processing.
A CPU (abbreviated as CPU) 710 is a DRAM (Dynamic Random Access Memory), which is a main memory for storing data and programs to be processed by the data processing device.
Reference numeral 720 denotes a data line for exchanging data between the CPU 700 and the memory 710. This data line 720 is connected to the main memory 710
For example, EDO D
RAM (Extended data out DRAM), SDRAM (Synchro
Nous DRAM), RAMBUS-compliant DRAM, etc., and the data input / output protocol changes depending on each memory type. 740 is IO (Input O
utput device, which is an external secondary storage medium such as a hard disk and a data input / output interface between the CPU 700 and the external device.

In such a data processing device, for example,
The program 1 as shown in FIG. 7 is processed, and data is input / output. A large amount of data processing such as image data processing is required.

The program 1 includes a program part that requires sequential processing including a conditional branch including an if statement such as a subprogram (a) and a subprogram (c), and a subprogram (b) There is a part that performs only a large amount of data processing as described above.

[0005]

However, the former sequential processing part is good for the ordinary CPU 700, and the latter large-volume data processing part is a part that can be executed by the ordinary CPU 700. However, if the processing amount is large, the processing is extremely heavy. Since such a large amount of data processing imposes a considerable burden on the CPU, it is not preferable to perform all the processing only by the CPU. In view of this, some recent CPUs have come to cope with the problem by adding a dedicated processing circuit to the original arithmetic circuit in the processor by adding a multimedia instruction set. Since such a processor is expensive, the large-volume data processing portion is separated from the CPU, and a dedicated device such as an external or one-chip digital signal processor (hereinafter abbreviated as DSP) is used. In order to perform processing by such a dedicated device, the development cost of the dedicated device itself is required, and a dedicated protocol for controlling resources related to the CPU, the dedicated device, and a complicated compiler are specially required. Was increasing.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a function memory having a dedicated protocol, an arithmetic function that does not require a complicated compiler, a data processing device using the function memory, and a recording device storing a compiler of the data processing device. The purpose is to provide a medium.

[0007]

In order to solve the above-mentioned problems, a functional memory according to the present invention is a memory having an arithmetic processing function for assisting processing of a CPU, and includes a plurality of FIFOs (First FIFOs) for storing data. in First out.
A memory bank, an instruction control unit, an operation unit that receives data from the plurality of FIFO memory banks and performs an operation, a source bank designating unit that designates a FIFO memory bank that stores data, A final bank designator for designating a FIFO memory bank for storing final reference data which is data required for calculation in the unit and finally received as reference data processed by the CPU; and a FIFO designated by the last bank designator. An operation start determining unit that determines that the last reference data has been written to the memory bank and issues an operation start signal;
A bus interface with an external bus, wherein the instruction control unit writes information into the source bank designation unit and the last bank designation unit according to data received from a CPU, and writes data from the main memory to the FIFO memory bank. The transfer is performed, the issuance of an operation start signal from the operation start determination unit is detected, the data in the FIFO memory bank is transferred to the operation unit, and the operation in the operation unit is performed.

With such a configuration, in processing a large amount of array data such as digital image data, the processing load on the CPU can be reduced by performing the array calculation portion in the functional memory. The CPU can obtain array calculation results by performing input / output processing of array data to the functional memory according to a normal memory input / output protocol.

Next, the functional memory includes an operation start signal holding buffer for temporarily holding an operation start signal of the operation start judging section, and the operation start signal holding buffer stores the operation start judgment signal issued. From the main memory to the FIFO
It is preferable that after the data transfer to the O memory bank is completed until the data transfer is completed, the instruction control unit detects the data.

With this configuration, a large amount of data processing occurs in the functional memory alone, and the DMA (Direct
Memory Access) When the transfer is performed continuously and it takes time to write a plurality of arrays to the functional memory at one time, the operation start signal issuance timing can be adjusted, and the operation processing start timing can be adjusted. Can be.

Next, a data processing apparatus using a functional memory according to the present invention includes a CPU, a main memory, and a functional memory, and the functional memory performs the CP processing in the processing.
U can refer to the processing data, and the CPU can refer to the processing data in the functional memory in the processing.

With such a configuration, the function memory has C
The array calculation can be performed by referring to the processing result in the PU as needed, and the processing can be continued in the CPU by referring to the array calculation result in the functional memory, and the consistency of the processing of the entire apparatus can be maintained. Can be kept.

Next, a compiler used in the data processing device stored in the recording medium according to the present invention analyzes a program to be executed, and processes the program in the CPU including the sequential processing. The present invention is characterized in that an execution program for a CPU and an execution program for a functional memory are generated by separating a part to be processed in the functional memory not included.

With this configuration, the processing program used for the data processing device is automatically generated by compiling a CPU execution program and a function memory execution program that are divided so that the resources of the CPU and the function memory can be optimally used. be able to.

Next, in the compiler used for the data processing device stored in the recording medium, the execution program for the functional memory specifies resources to be used for arithmetic processing and sends the resource to the source bank designation section and the last bank designation section. A process of writing information, a process of receiving data transfer from the CPU and the main memory, a process of performing an operation in the arithmetic unit, and an operation of the arithmetic unit after receiving final reference data from the CPU. A process for calculating the number of data referable cycles until the result can be transferred to the CPU; the CPU execution program includes a process for receiving data transfer from the main memory, a process for performing an operation, and When the function of referring to memory data is included, based on the number of data referable cycles, It is preferable to adjust the execution timing functions memory data reference process and a process to receive the data.

With this configuration, the timing can be adjusted so that the two execution programs can refer to the processing results of the other, and the consistency of the processing of the entire apparatus can be maintained.

[0017]

(First Embodiment) A data processing apparatus according to a first embodiment of the present invention will be described with reference to the drawings. 1 is a schematic block diagram of a data processing device according to the first embodiment, FIG. 2 is a diagram showing details of the functional memory shown in FIG. 1, FIG. 3 shows an address space of the memory, and FIG.
4 is a chart showing a cycle of operation of the CPU and the functional memory shown in FIG.

In the first embodiment, a case will be described as an example in which the data input / output program 1 shown in FIG. 7 described in the related art is executed. In the schematic block diagram of the data processing apparatus according to the first embodiment shown in FIG.
Denotes a CPU; 110, a main memory such as a normal DRAM for storing data and programs to be processed by the CPU 100; 120, a bus; 130, a functional memory;
Is an IO device. Each resource of the data processing device operates in synchronization with a clock, similarly to a general data processing device.

Next, in the address space of the memory of the system shown in FIG. 3, an area 200 is an area of an operating system (hereinafter abbreviated as OS) for controlling this data processing apparatus, an area 202 is an area of a compiler, and an area 2 is
Reference numeral 04 denotes a source program area to be processed by the CPU 100 in the future, and an area 206 denotes a CPU execution program area obtained by compiling the source program in the source program area 204, and an area 512.
Denotes a functional memory execution program area obtained by compiling the source program in the source program area 204, and area 208 denotes an area for storing data used by the source program and CPU execution program. Hereinafter, for convenience, the program stored in each area is referred to by the number of the area.

The bus 120 shown in FIG. 1 is unique to the device used as the main memory 110. For example, EDO DRAM, SDRAM, RAM
Each type of memory is unique to a BUS-compliant DRAM or the like, and a signal line and a protocol to the CPU 100 are different depending on each type of memory. Generally, it is composed of a read / write signal 122, an address signal 124, a data signal 126, and the like.

The function memory 130 shown in FIG.
Based on a control signal or the like from the CPU 20, data is received by a write operation from the CPU 100, a predetermined process is performed on the input data according to a program prepared in advance, and a read operation from the CPU 100 This is a functional memory that sends back the processing result to the CPU. That is, in accordance with an instruction from the CPU 100, a certain process is performed on the received data.
This can be regarded as a resource that performs a functional function of returning to the PU 100.

The IO device 140 shown in FIG. 1 includes a secondary storage medium, for example, a magnetic disk, and inputs and outputs data from the IO device 140 to the main memory 110 or the functional memory 130 when necessary.

Next, the function memory 130 will be described in detail.
In FIG. 2, reference numeral 520 denotes a memory unit. Memory unit 52
0 has a plurality of FIFO (first-in first-out) memory banks (500 to 510) and stores each array data when performing an operation. For example, when processing the program 1 shown in FIG.
And array [b] in the FIFO memory 502 and array [c]
Is stored in the FIFO memory 504. Here, CPU1
In input / output of data from 00 to the functional memory 130, writing and reading of one array data can be performed in one cycle.

Reference numeral 524 denotes an instruction unit. The instruction unit writes an instruction code of an arithmetic operation to be executed in the functional memory 130 into the arithmetic instruction unit 525, and stores an array (in this example, array [d]) which is finally received from data necessary for the arithmetic operation. The information for specifying the FIFO bank memory to be used is written to the last bank specifying unit 526, and the arithmetic unit 540
Then, information for designating the FIFO memory bank where the array is to be transmitted when the data is transmitted is written to the source bank designation unit 527 to control the operation of the functional memory 130. That is, the instruction unit 524 sets the content of the operation performed by the operation unit 540, manages the storage destination of the array data received by the operation unit 540 for the operation, and sets the data necessary for the operation unit 540 to start the operation. Manages the information for determining that the information has been collected. The information of the last bank designation unit 526 is given by interpreting the program by the compiler 202 as described later, and is used to cope with the data dependence of the CPU 100 and the functional memory 130.

A bus interface 630 controls input and output of data to and from the CPU 100 by inputting and outputting data from the data lines of the bus 120. The operation start determination unit 532 of the bus interface 630 receives the information of the data line 120, generates a data access signal 570 in accordance with the address signal 124, and writes or reads data to or from each FIFO memory in the function memory 130, or executes an instruction unit. 524 is instructed. Further, at this time, the calculation start determination unit 532
When each element of the array [d] is written according to the control signal of the data line and the last bank designation unit 526, each FI
The arithmetic unit 540 determines that data processing can be performed on the FO memory, and issues an arithmetic start determination signal 580.

An arithmetic unit 540 receives data from each FIFO memory of the memory unit 520 and processes the data. Here, the multiplier 55 as each element of the arithmetic unit 540
0, 552 and adders 560, 562 are each capable of executing the received data in one cycle. Therefore, two cycles are required when performing a product-sum operation on data input from the memory unit 520, and processing can be performed in one cycle when performing only multiplication.

Hereinafter, a rough processing flow when the data processing apparatus according to the first embodiment executes a program will be described by dividing into respective steps. (Step 0) The CPU 100 reads from the main memory 110
The program 204 and the compiler 202 for compiling the program 204 are loaded via the data line 120, and the CPU execution program 2
06 and a functional memory execution program 512 are generated and stored in the main memory 110. Here, the program 204 to be read is the program 2 shown in FIG. The compiler 202 interprets and separates a portion that has a sequential branch due to a conditional branch and the like and a portion that is not a sequential process without a conditional branch and the like and has a large amount of data processing such as an array calculation, and executes a compilation for the CPU. An execution program 206 and a function memory execution program 512 are generated. CPU
The subprograms (a) and (c) shown in FIG. 8 are compiled to generate an execution program as the functional execution program 206, and the functional memory execution program 512 is a subprogram ( b)
Is compiled to generate an execution program.

A point to keep in mind when generating an execution program by dividing as described above is the dependence of data required for each other's processing. That is, in order to perform an operation on the result d [i] calculated by the CPU 100 in the functional memory 130, at least data of each element d [i] of the array d after the operation is written into the functional memory 130 , It is necessary to perform an operation with reference to this, and the result e [i] calculated in the function memory
In order to perform the processing in U100, it is necessary for CPU 100 to read and refer to at least the data of each element e [i] of array e after the operation in functional memory 130, and perform the processing. Therefore, in the compiler 202, the CPU execution program 206 is compared with the CPU execution program 206 with respect to the subprogram (a) in the loop.
Will be generated. CPU execution program 206
Is programmed to send an array d, which is the processing result of the subprogram (a), to the functional memory 130, and the functional memory execution program 512 uses the final bank to specify the FIFO memory bank destination for storing the array d as final reference data. It is programmed to have in the designation unit 526.

For the subprogram (b), the compiler 202 calculates the number of referenceable cycles in consideration of the execution program for the program for the function memory 130 and the time for writing and reading data in and from the function memory 130. This is to determine the number of waits required for both execution programs to refer to the other processing result.

The compiler 202 creates an executable program that can execute the subprogram (c) for the subprogram (c) in consideration of the number of referenceable cycles. At this time, if the number of referenceable cycles is small, an unnecessary NOP instruction or the like is inserted as a dummy. However, if the number of reference cycles is sufficient, the execution in the function memory 130 and the next Instruction execution can be overlapped.

Before executing the arithmetic processing, the data of the arrays a, f and g are transferred from the IO device to the main memory 110, and the data of the arrays b, c and d operated by the functional memory 130 are stored. For the arrays b and c in the data, data is transferred from the IO device to the function memory 130 in advance. Array d
Is sent after the CPU 100 calculates each element of the array d in order to use the result processed by the CPU 100. The execution program 512 for the functional memory includes
When each element of the array d is sent, the function memory 130
A function is provided for determining that processing can be performed in the.

(Step 1) The CPU 100 executes the OS and starts an operation of loading the CPU execution program 206 into the program 204. First, C
The PU execution program 206 is loaded from the IO device into the main memory 110, and then the functional memory execution program 512 is loaded from the IO device into the instruction section 52 of the functional memory 130.
4 is stored. At this time, the operation instruction section 525 of the function memory
An instruction corresponding to the program (b) for the arithmetic unit 540 is written in the
The information about the array d as the final reference data stored in the memory 500 is stored in the source bank designation unit 527 in the arithmetic unit 5.
FIFO memory 500 storing the operation data to 40,
Information (111000) corresponding to 502 and 504 is written. Further, the array a, the array f, and the array g processed by the CPU 100 are loaded from the IO device 140, and finally, the array b and the array c are stored in the functional memory 130 from the IO device 140.

(Step 2) When the CPU 100 enters the execution state, first, the first element of each array (element number 0)
Is started, and this process is sequentially repeated up to the element number 999, whereby all the processes are executed.

Next, the step (Step 2) will be described in detail. (Step 2-0) Cycle # 0 The CPU 100 reads the array data a from the main memory 110.
Load [0].

(Step 2-1) Cycle # 1 The CPU 100 loads a [0] loaded from the main memory 110.
And "0" are compared.

(Step 2-2) Cycle # 2 The CPU 100 performs a conditional branch according to the comparison result of step 2-1. (Step 2-3) Cycle # 3 The CPU 100 performs a predetermined multiplication.

(Step 2-4) Cycle # 4 The CPU 100 stores the result of step 2-3 in the function memory 1
Write 30. At this time, the functional memory 130 receives the higher-order address signal of the data line of the bus 120 and the read / write signal by the operation start determining unit 532, and
After confirming that the first data of [0] has arrived, an operation start determination signal 580 is generated and sent to each FIFO memory bank.

(Step 2-5) Cycle # 5 The CPU 100 reads the array data f from the main memory 110.
Load [0]. In the function memory 130, each FIFO
The memory receives the operation start determination signal 580 and the signal of the source bank designation unit 527, confirms that the array data d [0], b [0], c [0] from the tag memory 516 are complete, and checks the FIFO. Memory 500, FIFO memory 502,
The data is read from the FIFO memory 504, and d [0] ×
Multiplication is performed by the multiplier 550 of b [0], and the multiplier 552
Outputs the data of c [0] as it is.

(Step 2-6) Cycle # 6 The CPU 100 loads f [0] loaded from the main memory 110.
And "20" are calculated. In the adder 560 of the function memory 130, the result d obtained by multiplication by the multiplier 550 is obtained.
[0] × b [0] is added to c [0] from the multiplier 552, and the result is stored in the FIFO memory 504 as e [0].

(Step 2-7) Cycle # 7 The CPU 100 performs a conditional branch according to the comparison result of step 2-6. The functional memory 130 has not performed any data processing since the arithmetic processing has been completed. Also in the subsequent cycles, a wait state in which no data is processed until the next array data d [1] to be processed comes.

(Step 2-8) Cycle # 8 The CPU 100 reads the array data e from the function memory 130.
Load [0]. (Steps 2-9 and thereafter) Cycle # 9 and thereafter The CPU 100 thereafter executes only the processing of the CPU 100 and repeats the processing up to the cycle # 10 or the cycle # 11 for each element of the array (0 to 999). All the processing ends.

That is, after a part of the data processing is executed by the CPU 100, the array data is sent to the function memory 130,
When performing an operation using the function memory 130, the function memory 130 refers to a normal protocol between the CPU and the memory, stores necessary array data in advance in a FIFO memory in the function memory 130, Furthermore, the array data received last from the CPU 100 is received, and the data stored in the data line of the bus 120 and the last bank designating unit 526 is referred to by the arithmetic start determining unit 532 to perform data processing. By generating an operation start determination signal 580 indicating that the operation is started, and starting the operation in the function memory 130 in accordance with this signal, the operation can be started when the necessary data is collected in the function memory 130. become.

Further, when the CPU 100 performs an operation on the array data processed in the functional memory 130, the compiler adjusts the timing of the operation in the functional memory and the CPU 100 by adjusting the timing of the operation in the CPU 100.
Even when the CPU 100 is operated according to a general protocol between 0 and the memory, the CPU 100 can perform subsequent arithmetic operations.

Embodiment 2 FIG. 5 shows a functional memory according to Embodiment 2 of the present invention. The second embodiment is different from the first embodiment in that the function memory 130 includes an operation start signal 580 from the operation start determination unit 532.
Is temporarily received by the FIFO memory 640.
Here, the FIFO memory 640 is used as a buffer for temporarily holding the operation start signal 580 issued from the operation start determination unit 532. According to this configuration, a large amount of data processing occurs in the functional memory alone,
When the DMA transfer from the device is performed continuously and it takes time to write a plurality of words (d [0], d [1],...) To the functional memory at one time, all the FIs
Since the operation start signal 580 can be held until the array data necessary for the operation is prepared in the FO, the input timing to each FIFO memory can be adjusted, and the timing of the operation processing start can be adjusted.

[0045]

As described above, according to the functional memory of the present invention, in processing a large amount of array data such as digital image data, the processing load on the CPU can be reduced by performing the array calculation portion in the functional memory. it can. CP
U can obtain an array calculation result by performing input / output processing of array data to the functional memory according to a normal memory input / output protocol.

According to the data processing apparatus of the present invention, the array calculation can be performed by referring to the processing result of the CPU in the functional memory as needed.
, The processing can be continued with reference to the array calculation result in the functional memory, and the processing consistency of the entire apparatus can be maintained.

According to the compiler of the present invention, the program used for the data processing device is automatically converted to C
It is possible to compile and generate an execution program for CPU and an execution program for functional memory that are divided so that the resources of the PU and the function memory can be used optimally. The timing can be adjusted so that it can be referred to, and the processing consistency of the entire apparatus can be maintained.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a data processing device according to a first embodiment of the present invention;

FIG. 2 is a schematic configuration diagram of a functional memory according to the first embodiment of the present invention;

FIG. 3 is an explanatory diagram of an address map of a memory and a functional memory;

FIG. 4 is a diagram illustrating operation timing of the data processing device.

FIG. 5 is a schematic configuration diagram of a functional memory according to a second embodiment of the present invention.

FIG. 6 is a schematic block diagram of a conventional data processing device.

FIG. 7 shows an example of a data input / output program

FIG. 8 shows an example of a data input / output program

DESCRIPTION OF SYMBOLS 100 CPU 110 main memory 120 bus 122 read / write signal 124 address signal 126 data signal 130 functional memory 140 IO device 200 OS area 202 compiler area 204 program area 206 CPU execution program area 208 processing data area 500, 502, 504, 506, 508, 510, 6
40 FIFO memory 512 Instruction memory area 520 Memory part 524 Instruction part 525 Operation instruction part 526 Last bank specification part 527 Source bank specification part 630 Bus interface 532 Operation start judgment part 534 Input / output buffer 540 Operation part 550,552 Multiplier 560,562 Adder 570 Data access signal 580 Operation start judgment signal

Claims (6)

[Claims] 1. A memory, which is used in a data processing device having a CPU and a main memory and has an arithmetic processing function for assisting the processing of the CPU, wherein a plurality of Fs for storing data are provided.
An IFO memory bank, an instruction control unit, and the plurality of FIs.
An operation unit for receiving data from the FO memory bank and performing an operation; a source bank specifying unit for specifying a FIFO memory bank for storing data; and data required for the operation in the operation unit and processed by the CPU. A final bank designator for designating a FIFO memory bank for storing last reference data received last as reference data, and an operation is performed by determining that the last reference data has been written to the FIFO memory bank designated by the last bank designator. A command start determining unit for issuing a start signal; and a bus interface to an external bus.
According to the data received from the CPU, writing information to the source bank designating section and the last bank designating section, transferring data from the main memory to the FIFO memory bank, and detecting the issuance of an operation start signal by the operation start determining section. Transferring the data of the FIFO memory bank to the operation unit and causing the operation unit to execute the operation. 2. An operation start signal holding buffer for temporarily holding an operation start signal of the operation start judging section, wherein the operation start signal holding buffer stores the issued operation start signal of the operation start judging section. 2. The functional memory according to claim 1, wherein the instruction control unit detects after holding until data transfer from the main memory to the FIFO memory bank is completed. 3. A function memory according to claim 1, comprising: a CPU; a main memory; and the function memory, wherein the function memory can refer to processing data of the CPU in the processing, and the CPU can execute the function in the processing. A data processing device using a functional memory, which can refer to processing data in a memory. 4. A CPU, a main memory, and a functional memory according to claim 2, wherein said functional memory can refer to processing data of said CPU in its processing, and said CPU can execute said function in said processing. A data processing device using a functional memory, which can refer to processing data in a memory. 5. An execution program for a CPU which analyzes a program to be executed, and separates a part for processing the program in the CPU including sequential processing from a part for processing in the functional memory not including sequential processing. 5. A recording medium on which a compiler for a data processing device according to claim 3 or 4 is configured to generate an execution program for a functional memory. 6. The function memory execution program specifies a resource to be used for arithmetic processing and writes information to the source bank designation section and the last bank designation section, and transfers data from the CPU and main memory. Receiving the data, performing the calculation in the calculation unit,
A process for calculating the number of data referenceable cycles from when the final reference data is received from U to when the operation in the operation unit is completed and the result can be transferred to the CPU;
The execution program includes a process for receiving data transfer from the main memory, a process for performing an operation, and a function memory data reference process performed by referring to data from the functional memory. 6. A recording medium in which a compiler of the data processing apparatus according to claim 5, further comprising a process of adjusting the execution timing of the functional memory data reference process based on the data and receiving the data.