JPS62249256A - Data transfer control processing system - Google Patents

Abstract

PURPOSE:To speed up switching at the time of a data chain by prefetching and holding a parameter necessary for the data chain in an adapter. CONSTITUTION:When a command from a host 1 instructs data transfer through the data chin, plural data transfers are chained, and sequentially executed. At that time the adapter 3 prefetches the parameter necessary for data transfer in a chain data block part 6, and holds it. When the value of a hard counter 7 comes to zero in the 1st data transfer, a set of data for the 2nd transfer is set to the hard counter 7 and a hard memory address counter 8 from the chain data block part 6, and the 2nd data transfer is executed.

Description

[Detailed description of the invention] [(Already required)] In data transfer systems that include adapters.

When a data chain is performed, the adapter has a chain processing unit that has the function of holding the count part value and address part contents required for the primary chain in the adapter. It is disclosed that switching control is performed and execution is performed at high speed.

[Industrial application field]

The present invention provides a data transfer control processing method, particularly a data transfer system having an adapter, in which the next required information for a data chain is held in advance in the adapter, and switching at the time of chaining is performed at high speed. The present invention relates to a data transfer control processing method.

[Conventional technology]

A data processing system is known in which a host, a memory, and an adapter are connected on a bus, and the adapter transfers data between a terminal device and the memory based on data transfer instruction information from the host. In this type of system, when the above data transfer is performed by a data chain, when the value of a hard counter called a byte counter reaches zero, the adapter changes the parameter (count) related to the next chain data. section value, address section contents, etc.).

Based on this, data transfer was continued.

[Problem that the invention seeks to solve]

In the case of the above conventional method, especially as adapters become microprocessor controlled and require high-speed transfers to and from terminal devices such as disks,
If there is even a slight delay in acquiring the above parameters, an overrun may occur.

[Means for solving problems]

The present invention solves the above problem by allowing the adapter to hold the next necessary parameters in advance when data chaining is performed.

FIG. 1 shows a basic configuration diagram of the present invention. In the figure, numeral 1 is a host, 2 is a memory, and 3 is an adapter.

4 is a terminal device, 5 is a chain processing unit, and 6 is a chain data block unit that holds parameters necessary for performing data chaining.

7 represents a hard counter, and 8 represents a hard memory address counter.

When the chain processing unit 5 enters the data chain execution mode, it takes in, for example, all the parameters necessary to execute the data chain one after another and stores them in the chain data block unit 6. It is designed to have a function.

[Effect]

For example, assume that a command from the host 1 instructs to transfer data using a data chain. In this case, multiple data transfers are chained and executed one after another, but the adapter 3 chains and sets the parameters necessary for each data transfer in advance.
The data is taken into the data block unit 6 and held.

That is, the combination of the value of the count section and the contents of the address section necessary for the first data transfer is taken in.

The above sets necessary for the second data transfer, the above sets necessary for the third data transfer, etc. are taken in advance and held in the chain data block unit 6. do. Then, data transfer is performed, and when the value of the hard carantuff becomes zero in the first data transfer, the data necessary for the second data transfer is sent from the chain data block section 6. The above set is set in the hard counter 7 and the hard memory address counter 8, and the second data transfer is performed in the form of a data chain. The same goes for the third and subsequent rounds.

〔Example〕

FIG. 2 shows a block diagram of the internal main parts of an adapter according to an embodiment of the present invention. Reference numerals 5.6 and 7.8 in the figure respectively correspond to those in FIG. 11 is a data transfer control unit that controls data transfer using the respective contents of the hard counter 7 and the hard memory address counter 8; 12 is a data transfer controller; Transfer end instruction section, 13 is a command register, 14 is a command register.
It represents a decoder.

When data chain transfer is instructed by the command section in the data transfer instruction information from the host 1, the command decoder 14 notifies the chain data parameter acquisition function section 9 of this fact. As a result, the chain data parameter import function section 9
For example, all parameters necessary for data transfer using the data chain are taken in and set in the chain data block unit 6. Also, the number of times there are chains is set in the counter 10.

Then, the parameters required for the first data transfer are:
The hard counter 7 and hard memory address counter 8 are set, and data transfer is performed by the data transfer control unit 11.

In the first data transfer, when the value of the hard counter 7 becomes zero (that is, when BC = 0), the data necessary for the second data transfer is sent from the chain data block section 6. parameters are set in hard counter 7 and hard memory address counter 8;
The value of the chain data number counter 10 is decremented by one. That is, the data transfer control unit 11 starts the second data transfer in the form of a data chain.

The same goes for the third and subsequent times. Note that the parameters necessary for the 9th data transfer are loaded into the chain data block unit 6 until the data transfer up to the (p-1)th time is completed.

After the first data transfer starts, the chain
The data/parameter import function section 9 may also operate.

When the above-mentioned data transfer is executed in the form of a data chain and the value of the chain data number counter lO becomes zero (that is, when CDL=0).

The data transfer end instructing unit 12 instructs the data transfer to end. Also, at this time, the adapter 3 reports this to the host 1.

〔Effect of the invention〕

As explained above, according to the present invention, the parameters necessary for the data chain are imported and held in the adapter in advance, so that when switching at the time of the data chain, the parameters are stored in the hardware. - It is only necessary to preset it in a counter, etc., and the switching will be performed at high speed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention, and FIG. 2 is a block diagram showing the internal main parts of an embodiment of the present invention. In the figure, 1 is a host, 2 is a memory, and 3 is an adapter. 4 is a terminal device, 5 is a chain processing section, 6 is a chain data block section, and 7 is a hard counter. 8 represents a hard memory address counter.

Claims (1)

[Scope of Claims] Upon data transfer, data transfer instruction information having at least a command section, a count section indicating the amount of data transferred, and an address section indicating an address on the memory used at the time of data transfer is received; The unit number of data corresponding to the contents of the count section is transferred to and from the terminal device (4), and the number of units to be transferred next is transferred onto the hard counter (7) when data chaining is performed. Set the memory address to hard memory address.
An adapter (with the function of setting it on the counter (8)
3), and the adapter (3) is connected to the terminal device (4).
In a data transfer system that performs transmission between
The adapter (3) is equipped with a chain data block section (6) that holds information necessary for the chain, and the chain processing section (5) stores the value and address section of the counter section necessary for the data chain. A plurality of pairs with the contents of
From the chain data block section (6), the sets are individually input to the hard counter (7) and the hard counter.
A data transfer control processing method characterized in that the data transfer control processing method is configured to preset a memory address counter (8).