JPH01170027A - 半導体実装方法 - Google Patents

半導体実装方法

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Publication number
JPH01170027A
JPH01170027A JP32734687A JP32734687A JPH01170027A JP H01170027 A JPH01170027 A JP H01170027A JP 32734687 A JP32734687 A JP 32734687A JP 32734687 A JP32734687 A JP 32734687A JP H01170027 A JPH01170027 A JP H01170027A
Authority
JP
Japan
Prior art keywords
semiconductor chip
circuit board
suction
chip
circuit substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32734687A
Other languages
English (en)
Inventor
Kazuyuki Iwata
和志 岩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP32734687A priority Critical patent/JPH01170027A/ja
Publication of JPH01170027A publication Critical patent/JPH01170027A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 （技術分野） 本発明は、半導体チップを回路基板に実装する方法に関
するものである。
（従来技術） 従来、第２図に示すように、回路基板４上にＬｓｉ等の
半導体チップ２を接合するには、回路基板４に接着用の
樹脂ペースト等のダイボンド剤３ａを塗布し、チップ吸
着コレットｌにより吸着したＬＳＩ等の半導体チップ２
の裏面を回路基板４上のグイボンド剤３ａ上で軽く加圧
し、加熱硬化してＬＳＩ等の半導体チップ２は回路基板
４に固定される（第２図、Ａ、Ｂ）。
しかる後、ボンディング用ワイヤ６により回路基板４の
電極５とＬＳＩ等の半導体チップ２の電極８との間をボ
ンディングした後（第１図、Ｃ）、電気的特性のチエツ
クがなされている。
このため、半導体チップに不良のものが混っていたり、
ダイシング又はワイヤボンディングの際、半導体チップ
が破損したりして、半導体チップを回路基板から交換す
る必要がある場合、半導体チップの交換ができず、基板
全体を廃棄せざるを得ない。よって歩留りが悪い欠点を
有していた。
（発明の目的） 本発明は、半導体チップを回路基板に実装するに際して
、電気的特性等の点検後において、回路基板から半導体
チップを交換することを容易とし、製品のみかけ上の歩
留りを向上させる方法を提供することを目的とするもの
である。
（発明の構成） 本発明は、前記目的を達成するために、半導体装方法と
して、予め回路基板との接合面側にＢステージダイボン
ド剤を塗布した半導体チップを用意し、この半導体チッ
プを吸着用穴部を形成した回路基板のグイボンドステー
ジ上に載置し、前記吸着用穴部を介して回路基板に半導
体チップを吸着した状態でワイヤボンディングを施し且
つ各種点検を行なった後、半導体チップと回路基板との
接合部を加熱してグイ接着を行なうことを特徴とするも
のである。
以下、本発明の実施例を図面に基づいて説明する。
本発明においては、回路基＋７ｉＥ　４に接着される半
導体チップ２には、半導体チップ２の接合面である裏面
に、従来用いられている導電性あるいは熱伝導性のエポ
キシ樹脂あるいはポリイミド樹脂からなる二液もしくは
一液性ペーストに代えて、Ｂステージエポキシによるグ
イボンド剤を用いている。Ｂステージエポキシ接着法と
は、ウェハ、フィルム等の上にエポキシペーストをスク
リーン印刷、塗布して、９０℃、２０分の加熱乾燥によ
りＢステージ化し、グイボンディング時に加熱接着しう
るものである。
本発明では、まず半導体チップ２の裏面にＢステージ状
のグイボンド剤３を塗布したものを用意する。
この半導体チップ２が接着される回路基板４には、接着
位置の中心部分に吸着用穴部７を穿孔する。
第１図（＾）に示されるように、ボンディング電Ｉｊｊ
５を備えた回路基板４に対して、Ｂステージ状ダイボン
ド剤３を設けた半導体チップ２をチップ吸着コレット１
により吸着保持して、ボンディング電極５を備えた回路
基板４上の定められた位置に取付ける。この際、回路基
板４には吸着用穴部７が半導体チップ２の取付位置の中
心に位置し、この吸着用穴部７には回路基板４の裏面側
に配置された、図示されていない真空ポンプ等が接続さ
れており、回路基板４に半導体チップ２を真空吸着して
いる。
第１図（Ｂ）では、回路基板４上に半導体チップ２が真
空吸着により固定された状態で、半導体チップ２と回路
基板４との各電極８，５の間にワイヤ６を超音波ワイヤ
ボンディングを施す。
この際、半導体チップ２が回路基板４上の適正な位置に
あるかどうかをパターン認識により判断するが、許容さ
れる範囲を越えている場合、半導体チップ２の位置を再
度調整することができる。
その後、この状態で電気的特性等の全体動作の点検が行
なわれ、その結果、所定の動作を得られず、この原因が
半導体チップにある場合、回路基板４上から半導体チッ
プ２とワイヤ６が取り除かれ、同様の工程により所定の
動作をなしうる他の半導体チップが取付けられる。
電気的特性が所定の条件を満たす半導体チップ２は、回
路基板４に真空吸着により似止めされた状態において、
半導体チップ２と回路基板４の接合部を加熱することに
よって、第１図（Ｃ）のように、半導体チップは回路基
板上に接着される。
以上のように、本発明の半導体装方法では、半導体チッ
プを回路基板に取付けるにあたり、半導体チップの接合
面にＢステージダイボンド剤を塗布し、且つ似止め手段
として半導体チップの裏面を回路基板に吸着固定しうる
吸着用穴部を設け、暇止めの状態でワイヤボンディング
を行ない、所定の動作の確認を経て、必要な場合は半導
体チップを交換することによって、全体的に製品の歩留
りを向上させることができる。
（発明の効果） 本発明の構成では、回路基板に半導体チップを装着する
方法として、Ｂステージダイボンド剤を用い且つ真空吸
着により似止め状態で各種点検を終えた後、その状態を
維持したまま加熱接着することができ、このため、適正
な半導体チップのみを回路基板に取付けることができる
効果を有し、よって完成品に到る製品の歩留りを著しく
向上させる利点を有する。
【図面の簡単な説明】
第１図（Ａ）　、　（Ｂ）　、　（ｃ）は本発明の半導
体装方法に関する説明図、 第２図（Ａ）　、　（Ｂ）　、　（Ｃ）は従来の半導体
装方法に関する説明図である。 ３・・・半導体チップの接合面に塗布したＢステージダ
イボンド剤、７・・・回路基板に設けた吸着用穴部。

Claims (1)

    【特許請求の範囲】
  1. 　予め回路基板との接合面側にＢステージダイボンド剤
    を塗布した半導体チップを用意し、この半導体チップを
    吸着用穴部を形成した回路基板のダイボンドステージ上
    に載置し、前記吸着用穴部を介して回路基板に半導体チ
    ップを吸着した状態でワイヤボンディングを施し且つ各
    種点検を行なった後、半導体チップと回路基板との接合
    部を加熱してダイ接着を行なうことを特徴とする半導体
    実装方法。
JP32734687A 1987-12-25 1987-12-25 半導体実装方法 Pending JPH01170027A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32734687A JPH01170027A (ja) 1987-12-25 1987-12-25 半導体実装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32734687A JPH01170027A (ja) 1987-12-25 1987-12-25 半導体実装方法

Publications (1)

Publication Number Publication Date
JPH01170027A true JPH01170027A (ja) 1989-07-05

Family

ID=18198111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32734687A Pending JPH01170027A (ja) 1987-12-25 1987-12-25 半導体実装方法

Country Status (1)

Country Link
JP (1) JPH01170027A (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03124639U (ja) * 1990-03-30 1991-12-17
US5120678A (en) * 1990-11-05 1992-06-09 Motorola Inc. Electrical component package comprising polymer-reinforced solder bump interconnection
US5721450A (en) * 1995-06-12 1998-02-24 Motorola, Inc. Moisture relief for chip carriers
US6242802B1 (en) 1995-07-17 2001-06-05 Motorola, Inc. Moisture enhanced ball grid array package
USRE43404E1 (en) 1996-03-07 2012-05-22 Tessera, Inc. Methods for providing void-free layer for semiconductor assemblies

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03124639U (ja) * 1990-03-30 1991-12-17
US5120678A (en) * 1990-11-05 1992-06-09 Motorola Inc. Electrical component package comprising polymer-reinforced solder bump interconnection
US5721450A (en) * 1995-06-12 1998-02-24 Motorola, Inc. Moisture relief for chip carriers
US6242802B1 (en) 1995-07-17 2001-06-05 Motorola, Inc. Moisture enhanced ball grid array package
USRE43404E1 (en) 1996-03-07 2012-05-22 Tessera, Inc. Methods for providing void-free layer for semiconductor assemblies

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